Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science

Development of an ASIC forreading out CCDS at the vertex

detector of the International Linear Collider

Presenter: Peter Murray

ASIC Design Group

Science & Technology Facilities Council

Rutherford Appleton LaboratoryHarwell Science & Innovation Campus

Didcot

Oxfordshire

OX11 0QXUnited Kingdom

•ILC will collide e+ e- beams at energies up to 500GeV.

•Interactions recorded by 2 detectors, each with a vertex detector.

•Vertex detector resolution < 5 microns, with low power and minimum material.

•Thus CCDs have been selected.

•Need to keep occupancy below 1% means that CCD pixel columns must be read out in parallel at 50Mhz.

•Low occupancy also makes on-chip data sparsification desirable.

Detector overview

Already fabricated CPR chips

Bump bond pads

Wire/Bump bond pads

CPR1

CPR2

Voltage and charge amplifiers 125 channels each

Analogue test I/O

Digital test I/O

5-bit flash ADCs on 20 μm pitch

Cluster finding logic (22 kernel)

Sparse readout circuitry

FIFO

Designed for readout of Column Parallel CCDs under development for LCFI (Linear Collider Flavour Identification)

CPR2 Size : 6 mm 9.5 mm

0.25 μm CMOS process (IBM)

•Chip reads out digitized pixel data only if it exceeds specified threshold.

•Charge from a particle may be shared between several CCD pixels.

•Hence sparsification logic sums data from every 2x2 array of pixels and compares with threshold.

•Chip also reads out data from pixels surrounding the hit pixels which triggered readout.

•Thus all interesting data guaranteed to be read out.

•Because of limited space for the logic the algorithm must be very simple.

CPR2A Sparsification algorithm

Sparsification algorithm

2 by 2 cluster above threshold : 6 by 4 output data

1 1 1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

22 2

2 2

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1

2

2 2

1 1 1 1

1 1 1 1

1

1

1

1

1 1 1 1

1 1 1 1

CPR2A readout format – case 1

Output data format

Colour coding: Address (H) Address(L) Gap (00000) Time-stamp Data

Simplest case: 6 words of 5-bit data


4 by 2 input cluster,

Output data: 6+8 by 4

1111 11

1111 11

111 12 2

111 12 2

111 12 2

111 12 2

1111 11

1111 11

1 1

1 1

1 1

1111 11 1111 11

111

1111

1

221 1

1 1221 1

1 1221 1

1 1221 1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1

1111 11



1111 11

111 12 2

111 12 2

1111 11

1111 11

1 1

1 1

1 1

1 1

111

11

1

1 1

1 1

22

1 1

1 11 1

1 11 1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1


1111 11

1111 11

1111 11

1111 11

1111 11

1111 11

1111 11

111 12 2

111 12 2

1111 11

2 2

1 1

1

1 1

1

1 11 1

1 11 1

1 11 1

1 1

1 1

111

1111

1

1 1

1 1

111

1111

1

1 1

1

1 1

1

111 1

1111 11

1 1

1 1

11

1 122

2 2

1111 11

2 input clusters, separated by 9 time steps

Output data: 6+8+8 by 4

Maximum separation that is stored as a single data block


01020304050607080901000

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50CPR2A Input Data: clusters_sv3.txt

01020304050607080901000

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35

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50CPR2A Output Data: signalscan_sv3.dump

When vertical cluster separation < 10 pixels data stored in column memory as single data block since only one timestamp needed. When sep>10 data is stored as 2 separate data blocks.

Address (H) Address(L) Gap (00000) Time-stamp Data

Extended data: 12 words in 2 groupsTime-stamp repeated, no break in header signalGap between groups of data, to identify new time-stamp

Output data format

CPR2A Verilog simulations based on physics data (100 channels, 100 time steps)

Near-perfect readout over 100 time steps (44 hit pixels, occupancy 0.44%)

One missing data point in the output (channel 92, time stamp 4)

CPR2A Verilog simulations based on physics data (128 channels, 5000 time steps)

Good efficiency for top end of plot : later time stamps

Poor efficiency at bottom end of plot: clusters have lower priority and can be overwritten

0204060801001204820

4840

4860

4880

4900

4920

4940

4960

4980

5000

CPR2A Input Data: Large127_6000.dat

0204060801001204820

4840

4860

4880

4900

4920

4940

4960

4980

5000

CPR2A Output Data: signalscan_05_03_07.dump

0

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30

Readout system components

X 16

6 bit chip output(5bit pixel dataPlus header)

Data present

x16

Intermediatememory

Co

lum

n m

em

ory

Co

lum

n m

em

ory

Co

lum

n m

em

ory

First level multiplexerFirst level multiplexer

x16

Intermediatememory

Co

lum

n m

em

ory

Co

lum

n m

em

ory

Co

lum

n m

em

ory

First level multiplexerFirst level multiplexer

Top level multiplexer (driven at 8x front end frequency)

Multiplexers are based on rotating pointers in shift registers. During operation pointer positions becomerandomised ensuring all parts of the CCD have equal chance of being

read out .

Cluster processingLayout segment 40 microns x1.7mm

State machine

Logic

Buffer registers

Time-stamp registers

Memory cells (38 words)

Header memory (38 bits)

5 bit ADC output(encoded)

Code converter

1 clock delay reg

5 bit adder

Partial sumPartial sum of Next channel6 bit adder

Dig thresholdRegister (local)

Dig comparator

Memory controller

Raw data fromCode converter

Header register(36 bits)

3 word timestampPixel data memory(shift register type, 38 words)

Output to intermediate memoryvia first level multiplexer

Logic or of header regInitiates readout by mux

Extract data signal(from lev 1 mux)

Cell: 1 2 3 4 5 6 7 8 9 10 Register cells on 4 m pitch

Mirrored layouts : Nwells of adjacent cells are butted together, to minimise transistor separations

Layout is 3 times more compact than CPR2non-mirrored layout

Sections of digital layout

Layout of 16 columns:320 m x 3.5 mm

Code converter

Logic:

Adders

Threshold store

Comparators

State machine (front end)

State machine (back end)

Layout of 2 columns : 40 m x 30 m

Area 320 x 315 m

• Provides local storage of data and header bits

• Interface between first and second level mux stages

• New compact layouts - 6 bits in separate blocks over 320 microns

intermediate memory

ConclusionsStatus

• CPR2A chip has been designed to build on the success of the CPR2, but with greater memory depth to reduce dead time problems.

• CPR2A layout largely completed.

• Final verifications with realistic simulated physics data are being performed.

• Submission by October

Next steps

• Plan to realise further versions of the readout chip on 0.13m technology.

• Next version will have more memory and a more sophisticated sparsification algorithm to reduce dead time problem.

Documents

Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science