DevelopmentofATLASLiquidArgon CalorimeterFrontend ... · Outline 1. IntroducGon* 2. Analogfrontend – 65nm – 130nm – SiGe* 3. ADCs* 4. OpGcallinks – LaserdriverarrayASICs

Development of ATLAS Liquid Argon Calorimeter Front-‐end Electronics

for the HL-‐LHC

Andy Tiankuan Liu on behalf of

the ATLAS Liquid Argon Group

Outline 1.  IntroducGon 2.  Analog front-‐end

–  65 nm –  130 nm –  SiGe

3.  ADCs 4.  OpGcal links

–  Laser driver array ASICs – OpGcal transmiNer array module

5.  Summary

2 Tiankuan Liu, TWEPP, Karlsruhe, Germany, September 27, 2016

ATLAS LAr Detector and Phase-‐II Upgrade

Preamp + shaper Func;onally the Same as the current detector

New Approach Trigger-‐less readout DigiGze and ship all digital data

LAr Detector @ 87K not change except

potenGal upgrade of FCal


The back end will also be replaced to readout the new front-‐end

Upgrade ObjecGves

•  Detector capacitance 0.2 to 1.5 nF •  Signal dynamic range ~ 16 bits •  Noise requirements ~ 100 nA •  Selectable input impedance 25 or 50 Ω for cable terminaGon •  Moderate radiaGon tolerance requirements ~300 krad, 1013 cm-‐2

1-‐MeV eq. neutrons •  DigiGze all 128 channels/FEB @ 14 bits, 40 or 80MS/s with 2 gain

scales. •  Ship data from all channels off detector (trigger-‐less readout). •  Keep the power dissipaGon to the current one or lower.


Op;ons Being Explored

1.   Mul;ple-‐ASIC solu;on – Preamplifier + shaper – ADC – Encoder + serializer – Laser drivers and op;cal transmiLers

2.   Front-‐End System-‐On-‐Chip (FESOC) solu;on – Preamplifier + shaper + ADC + serializer – Laser drivers and op;cal transmiLers



–  65 nm –  130 nm –  SiGe



5.  Summary


Front-‐End System On Chip •  FESOC (front-‐end system

on a chip): proposed •  HLC1: 8-‐ch analog FE

ASIC –  Dual range –  Programmable gain –  Programmable

terminaGon –  Programmable filter

•  To be integrated with ADCs and mux/encoder/serializers

•  Power dissipaGon ~1.2 W •  CMOS 65 nm


Preamp in 65 nm -‐ Design •  New concept •  Fully differenGal amplifier •  Very stable terminaGon (R and N independent of signal current)

Noiseless capaciGve feedback sehng the gain


Preamp in 65 nm -‐ Performance •  Equivalent noise at

the input ENI ~57nA rms at 260pF, 40ns

•  Nonlinearity now within 0.1% at 9mA, within 0.5% at 10mA

•  Power dissipaGon ~100 mW/channel from single 1.2V supply

•  The layout design is being finalized, and the test chip submission is imminent.


40 ns

57 nA

Peaking Gme sehng

Analog FE in 130 nm -‐ Design

Noise

Line termina;on


Analog FE in 130 nm -‐ Performance

10 kHz

1 MHz

100 MHz

Frequency (Hz)

Inpu

t impe

dance (Ω

)

25.5Ω @1MHz

High gain (0-‐1-‐mA)

High gain (1-‐10 mA)

Integral nonlinearity with CR-‐RC2 (40 ns peaking Gme)

Impedance flat from 10 kHz to 100 MHz < 1 Ω variaGon versus current due to Super Common base Zin variaGon

Noise dominated by R0 and NMOS: 150 nA with 1.5 nF

±0.2%

±0.2%


FE analog in 130 nm -‐ Prototype

LAUROC : 8 Channel prototype •  Super Common Base type Preamp •  Programmable Zin: 25 or 50Ω •  2 Gain Ranges: 2 or 10mA •  Input Noise eq. < 10Ω •  High current SaturaGon miGgaGon •  Preamp Power 7mA @ 2.5V ~ 18mW •  SubmiNed April 2016


Compare 130 nm and 65 nm: •  Test boards/benches similar •  ComparaGve measurements of 65/130 nm chips Goal -‐ Converge

FE Analog in SiGe (180 nm) •  Similar to the current design which is implemented with discrete components •  Bonding opGon for 25/50 Ω. No impedance/dynamic range tuning •  Might be marginal at High frequency (> 30 MHz) and large current •  Good noise performance on simulaGon : 25 Ω preamp : 86 mW, 97 nA for 1.0 nF

with CR-‐RC2 shaping •  Layout exists. Submission is under discussion



–  65 nm –  130 nm –  SiGe



5.  Summary


ADC in -‐ Specs

•  High resoluGon: 14 bits •  High speed: 40-‐80 MS/s •  Low power, small area •  RadiaGon-‐tolerant

Detector Output Signal

Phase-II Upgrade FEB (On detector)

MUX

& Serializer

Optical Links

To Back-end -1000 200400600800100012001400

0

0.5

1

Time [ns]

Nor

mal

ized

Am

plitu

de

Analog Shaper

ADC

Preamp

ADC

16-bit DR 10 Gbps ?

15 15 Tiankuan Liu, TWEPP, Karlsruhe, Germany, September 27, 2016

Chip Architecture


•  The work is sGll “in-‐progress” and the chip FEB2 context study started

•  65 nm CMOS •  8-‐channel 14-‐

bit ADCs at 40 MS/s

•  QFN package preferred (100 pins, 0.5 mm pitch, 12 mm x 12 mm

Power cut

Possible Layout


Power cuts

Digital side

Analog side

ADC channels. Silicon space 0.2 mm x 1 mm per channel

References •  Chip produces

data volume of 5.12 Gbit/s

•  Die size 1.98 x 1.95 mm

•  136 die I/O pads


–  65 nm –  130 nm –  SiGe



5.  Summary


OpGcal Links: Overview •  The opGcal link part will take advantage of lpGBT and VersaGle Link +, together

aiming at the development of rad-‐tol opGcal links. •  The major parts (Mux, encoder and serializer) of lpGBT (65-‐nm CMOS technology)

will be integrated with the analog front-‐end and ADCs. •  Laser array driver ASICs and opGcal transmiNer modules are designed for VersaGle

Link +.


Related talks: •  Paulo Moreira, RadiaGon hard High-‐Speed OpGcal Links for HEP, 9:00-‐9:45, Thursday. •  Csaba Soos, VersaGle Link PLUS Transceiver Development, 11:10 AM, Thursday.

GBTLDD

TIA PD

Laser

TRx

Versatile Link FPGA

On-DetectorCustom Electronics & Packaging

Radiation HardOff-Detector

Commercial Off-The-Shelf (COTS)Custom Protocol

Timing and Trigger

DAQ

Slow Control

Timing and Trigger

DAQ

Slow Control

GigaBit Laser Driver (GBLD)

Mux+ENC +SER

Laser Driver Array: Design and Layout


Two-‐stage pre-‐driver

VLAD output driver

lpVLAD output driver

1.9 mm

1.7 mm Pitch 0.25 mm

1.9 mm

VLAD (VCSEL Array Driver) and lpVLAD (low-‐power VCSEL Array Driver) are 4-‐channel, 10-‐Gbps-‐per-‐channel VCSEL array driver ASICs designed in a 65-‐nm CMOS technology with different output structures.

Related Talk: Di Guo, Developments of two 4 × 10-‐Gbps radiaGon-‐tolerant VCSEL array drivers in 65 nm CMOS, 3:40 PM, Wednesday. Poster: Zhiyao Zeng, LDQ10P: A Compact Low-‐Power 4x10 Gb/s VCSEL Driver Array IC, today.

Laser Driver Array: OpGcal mulG-‐channel test Results •  Total jiNer = 48 ps •  Total power consumpGon 33.9 mW/ch

•  10 Gbps opGcal eye with adjacent channel working simultaneously

•  Input: diff, swing 200 mV, PRBS 27-‐1 •  Tested rad-‐tol above to 300 Mrad.

•  Signal source: Agilent J-‐BERT N4903B (12.5 Gb/s)

•  Oscilloscope: Agilent DSA91204A (12 GHz) with opGcal receiver Agilent 81495

•  Total jiNer 35 ps •  Total power consumpGon 21.6 mW/

ch. This is a world record now.


100 ps 845 µW 100 ps 975 µW

VLAD lpVLAD

Laser Driver Array: Module Development •  ATx (Array opGcal TransmiNer) is a 12-‐channel,10 Gbps-‐per-‐channel opGcal transmiNer module

developed, based on the MOI and Prizm from US Connec and the AZ8 connector from Samtec with custom acGve-‐alignment method for the module assembly.

•  ATx is used as a test vehicle for VLAD/lpVLAD. •  MOI and prizm tested rad-‐tol up to 96 Mrad.


ATxfootprint:10mmx15mm.MOIwithaPrizmconnecttoa12-wayfiberribbon.

2mm

1.51mm1.78mm

Thebasewillbereducedfrom2mmto1.2mm.ATxmoduleswillbe5.3mmtallfornow.Inthefinaldesignwehopetoreducetheheightto4.5mm.

1.2mm

Summary

•  The ATLAS LAr front-‐end readout electronics without trigger is under development to meet the high luminosity requirements.

•  An approach of System-‐On-‐Chip is being targeted: integraGng all front-‐end funcGonal blocks (preamplifiers/shapers/ADCs/mux/encoders/serializers).

•  Three analog front-‐end ASICs in early development stages show promising performances within terminaGon, capacitance range, input signal dynamic range and power requirements.

•  New ADC design has been started. •  Two radiaGon-‐tolerant laser driver array ASICs and an opGcal transmiNer modules are prototyped and tested.


Documents

Developmentof*ATLAS*Liquid*Argon* Calorimeter*Frontend ... · Outline* 1. IntroducGon* 2. Analog*frontend* – 65nm – 130nm – SiGe* 3. ADCs* 4. OpGcal*links* – Laser*driver*array*ASICs*

DevelopmentofATLASLiquidArgon CalorimeterFrontend ... · Outline 1. IntroducGon* 2. Analogfrontend – 65nm – 130nm – SiGe* 3. ADCs* 4. OpGcallinks – LaserdriverarrayASICs