Digital And Logic Devices No.5 (DLD Basic Devices(Basic Flip Flop (Sequential Circuit)) From APCOMS

8/14/2019 Digital And Logic Devices No.5 (DLD Basic Devices(Basic Flip Flop (Sequential Circuit)) From APCOMS

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Combinational

CircuitMemory

elements

Inputs

Outputs

Block diagram of a Sequential Logic

Circuit


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Q

QS (set)

R (reset)1

0

1

0

1

2

S R Q Q

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

(after S=1, R=0)

(after S=0, R=1)

Basic flip-flop circuit with NOR gates

(Asynchronous Sequential Circuits)

(a) Logic Diagram

(b) Truth Table


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Q

Q

S (set)

R (reset)

1

2

1

0

1

0

S R Q Q

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

(after S=1, R=0)

(after S=0, R=1)

Basic flip-flop circuit with NAND gates

(Asynchronous Sequential Circuits)

(a) Logic Diagram

(b) Truth Table


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1

1

Q

Q

1

2

(a) Logic diagram

Q S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 Indeterminate

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 indeterminate

(c) Characteristic table

Q Q

R S

X 1

1 X 1

00 01 11 10Q

0

1

SR S

RQ(t+1) = S+RQ

(b) Graphical Symbol

(d) Characteristic equationClocked RS flip-flop

SR = 0

R

CP

S

CP


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3

4

Q

Q

1

2

5

(a) Logic diagram with NAND gates

Q Q

D


Q D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

1

1

0

1

0 1

Q(t+1) = D

(c) Characteristic table (d) Characteristic equation

Clocked D flip-flop

D

CP

R

S

CP

Q

D


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(a) Logic diagram

Q

Q

Clocked JK

flip-flop

Q Q

K J

J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

1 1

1 1

00 01 11 10Q

0

1

JK J

KQ(t+1) = JQ+KQ

(d) Characteristic equation(b) Graphical Symbol (c) Characteristic table

K

CP

J

CP


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(a) Logic diagram

Q

Q

Clocked T

flip-flopCP

T

Q Q

T


CP

Q T Q(t+1)

0 0 0

0 1 11 0 1

1 1 0

(c) Characteristic table

1

1

0

1

0 1Q

T

Q(t+1) = TQ+TQ

(d) Characteristic equation


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Positive Pulse Negative Pulse

Positive-

edge

Negative-

edge

Negative-

edge

Positive-

edge

Definition of clock pulse transition

1

0


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Master

S

R

Slave

S

R

S

R

Q

Q

CP

MASTER-SLAVE FLIP-FLOP

Logic diagram of master-slave flip-flop

Y

Y


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Timing relationships in a master-slave flip-flop

S

Q

Y

CP

S=1, R=0 S=0, R=1


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13

42

5

6

Q

Q

7

8

9

K

CP

J Y

Y

Clocked master-slave JK flip-flop


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1

2

3

4

5

6

CP

S

R

Q

Q

R Q

1 0 0 1

1 1 0 1

1 1 0

1 1 1 0

0 1 1

(NC)

(NC)

S=R=1 for steady state values

When S=1 & R=0 : Q=0

When S=0 & R=1 : Q=1

D-type positive-edge-triggered flip-flop


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1

2

3

4

CP=0

S

D=0

1

2

3

4

CP=0

S

D=1

0

1

1

1

1

1

1

0

No Change at the outputs of the flip flop whether D = 0 or 1

(a) With CP = 0

Operation of the D-type edge-triggered flip-flop

So Q = 0 & Q = 1


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1

2

3

4

CP=1

S

D=0

1

2

3

4

CP=1

S

D=1

0

1

0

1

1

0

1

0

Operation of the D-type edge-triggered flip-flop

(b) With CP = 1

So Q = 0 & Q = 1 So Q = 1 & Q = 0So Q = 1 & Q = 0


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Q Q

K J

Function TableInputs Outputs

Clear Clock J K Q Q

0 x x x 0 1

1 0 0 No Change

1 0 1 0 1

1 1 0 1 0

1 1 1 Toggle

CP

Direct Inputs

Asynchronous

JK flip-flop with direct clear

Clear


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yx

A

B

R Q

S Q

xA

x

A

B

B

R Q

S Q

x

B

x

B

A

A

CP

Example of clocked sequential circuit

(Analysis)

Input = x (External)

Output = y

Clocked RS flip-flop


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Next State Output

Present State x=0 x=1 x=0 x=1

AB AB AB y y

00 00 01 0 0

01 11 01 0 0

10 10 00 0 1

11 10 11 0 0

State table for circuit


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00

11

01 10

0/0

0/0

0/00/0

1/01/0

1/0

1/1

State diagram for the circuit


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1 1 1

1

A

0

1

Bx B

x

00 01 11 10

A

1

1 1 1

A

0

1

Bx B

x

A

00 01 11 10

A(t+1) = Bx+(B+x)A B(t+1) = Ax+(A+x)B

(a) A(t+1) = Bx + (Bx) A (b) B(t+1) = Ax + (Ax) B

A(t+1) = S+ RA B(t+1) = S+ RB

State equations for flip-flops A and B

Q(t+1) = S+ RQ

SR=0


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SA = B x RA = Bx

SB = Ax

RB = Ax y =

ABx

Analysis of clocked sequential circuit


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yx

A

B

R Q

S Q

xA

x

A

B

B

R Q

S Q

x

B

x

B

A

A

CP

Clocked sequential circuit

Input = x (External)

Output = y

Clocked RS flip-flop


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K Q

J Q

A

A

B

C

x

B

C

x

B

y

CP

JA = BCx + BCx and KA = B+y

Implementation of the flip-flop input functions


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a

b

d

f

c

e

g

0/0

1/0

1/1

0/0

0/0

0/0

0/0

0/0

0/0

1/01/0

1/1

1/1

1/1

Present State a a b c d e f f g f g a

Input Value 0 1 0 1 0 1 1 0 1 0 0

Output Value 0 0 0 0 0 1 1 0 1 0 0

State diagram

The problem of state-

reduction is to find ways of

reducing the number of

states in a sequential circuit

without altering the input-

output relationships.

minimizes the cost of

circuit by reducing flip-

flops & gates.

Consider the input

sequence 01010110100

starting from present state a.

We are interested only in

output sequences caused by

input sequences..


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Next State Output


a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g a f 0 1

State Table

R d i h S T bl


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Next State Output


a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1f g f 0 1

g a f 0 1

Reducing the State Table

State a a b c d e d d e d e aInput 0 1 0 1 0 1 1 0 1 0 0

Output 0 0 0 0 0 1 1 0 1 0 0

d

de


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Next State OutputPresent State x=0 x=1 x=0 x=1

a a b 0 0

b c d 0 0c a d 0 0

d e d 0 1

e a d 0 1

Reduced State Table


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001

a

010

b

100

d

011

c

101

e

0/01/0

1/1

0/0

0/0

0/0

0/01/1

1/01/0

Reduced State diagram

m flip-flops can represent

up to 2m distinct states (i.e.

if m=3, 8 states => 000-

111)

For five states, 3 flip-

flops are required.

Fewer states do not

guarantee a saving in the

number of flip-flops or

number of gates.


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10100001101

10100101100

00100001011

0010001101000010001001

x=1x=0x=1x=0Present StateOutputNext State

Reduced State Table with binary assignment 1

011111101e

101101100d

010011011c

100010010b

000000001a

Assignment3Assignment2Assignment 1State

Three possible binary state assignments

Fli fl h t i ti t bl


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S R Q(t+1) J K Q(t+1)

0 0 Q(t) NC 0 0 Q(t) NC

0 1 0 0 1 0

1 0 1 1 0 1

1 1 ? 1 1 Q(t)

D Q(t+1) T Q(t+1)

0 0 0 Q(t) NC

1 1 1 Q(t)

(a) RS (b) JK

(c) D (d) T

Flip-flop characteristic tables


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Q(t) Q(t+1) S R Q(t) Q(t+1) J K

0 0 0 X 0 0 0 X

0 1 1 0 0 1 1 X

1 0 0 1 1 0 X 1

1 1 X 0 1 1 X 0

Q(t) Q(t+1) D Q(t) Q(t+1) T

0 0 0 0 0 0

0 1 1 0 1 1

1 0 0 1 0 1

1 1 1 1 1 0

(a) RS (b) JK

(c) D (d) T

Flip-flop excitation tables


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Design Procedure for Sequential Logic Circuits

1. The word description of the circuits behavior is stated. This may beaccompanied by a state diagram, a timing diagram, or other pertinentinformation.

2. From the given information about the circuit, obtain the state table.

3. The number of states may be reduced by state reduction methods if thesequential circuit can be characterized by input-output relationshipsindependent of the number of states.

4. Assign binary values to each state if the state table obtained in step 2 or3 contains letter symbols.

5. Determine the number of flip-flops needed and assign a letter symbol toeach.

6. Choose the type of flip-flop to be used.7. From the state table, derive the circuit excitation and output tables.

8. Using the K-Map or any other simplification method, derive the circuitoutput functions and the flip-flop input functions.

9. Draw the logic diagram.


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00

10

01 110

1

1

1

1

0

0

0State diagram

Design the clocked sequential circuit

using JK flip-flops from the given state

diagram.

Next State Output

Present State x=0 x=1

A B A B A B

0 0 0 0 0 1

0 1 1 0 0 1

1 0 1 0 1 1

1 1 1 1 0 0

State Table

Q( ) Q( 1) J K


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Inputs of Combinational

Circuit Next state

Outputs of Combinational circuit

Present state Input Flip-flop inputs

A B x A B JA KA JB KB

0 0 0 0 0 0 X 0 X

0 0 1 0 1 0 X 1 X

0 1 0 1 0 1 X X 1

0 1 1 0 1 0 X X 0

1 0 0 1 0 X 0 0 X

1 0 1 1 1 X 0 1 X1 1 0 1 1 X 0 X 0

1 1 1 0 0 X 1 X 1

Q(t) Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Excitation table


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Combinational Circuit

A

A

B

B

Q Q

K J

Q Q

K J

A A B B

KA JA KB JB

CP

External

outputs

(none)

External Inputs

Block diagram of sequential circuit

x

B B


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1

X X X X

00 01 11 10A

0

1

Bx B

x

A

X X X X

1

00 01 11 10A

0

1

Bx B

1 X X

1 X X

00 01 11 10A

0

1

Bx B

X X 1

X X 1

00 01 11 10A

0

1

Bx B

JA = BxKA = Bx

JB = x KB = A . X = Ax + Ax

Maps for combinational circuit


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Q Q

K J

Q Q

K J

A

B

CP

x

Logic diagram of Sequential Logic Circuit

JA = Bx

KA = Bx

JB = x

KB = A x

Q: Design a sequential circuit using state table with assignment 1 employing


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Present state Input Next State Flip-flop Inputs OutputA B C x A B C SA RA SB RB SC RC y

0 0 1 0 0 0 1 0 X 0 X X 0 0

0 0 1 1 0 1 0 0 X 1 0 0 1 0

0 1 0 0 0 1 1 0 X X 0 1 0 0

0 1 0 1 1 0 0 1 0 0 1 0 X 0

0 1 1 0 0 0 1 0 X 0 1 X 0 0

0 1 1 1 1 0 0 1 0 0 1 0 1 0

1 0 0 0 1 0 1 X 0 0 X 1 0 0

1 0 0 1 1 0 0 X 0 0 X 0 X 1

1 0 1 0 0 0 1 0 1 0 X X 0 0

1 0 1 1 1 0 0 X 0 0 X 0 1 1

Excitation table

Q: Design a sequential circuit using state table with assignment 1 employing

RS flip-flops.

Q(t) Q(t+1) S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

C


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x x

1 1

x x x x

x x x

00 01 11 10

00

01

11

10

AB

A

C

x x x x

x x

x x x x

1

x x 1

x

x x x x

x x x

1 1 1

x x x x

x x x x

x x x

1 x

x x x x

1 x

x x 1

x 1

x x x x

x 1

x x

x x x x

1 1

SA=Bx RA=Cx SB=ABx

RB=BC+Bx SC=x y=AxRC=x

Maps for simplifying the sequential circuit

Cx

Cx

B

00 01 11 10AB 00 01 11 10AB

00 01 11 10AB00 01 11 10AB00 01 11 10AB00 01 11 10

Cx Cx

Cx Cx

00

01

11

10

00

01

11

10

00

01

11

10

Logic diagram


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S Q

R Q

S Q

R Q

S Q

R Q

y

A

A

B

B

C

CP

x

Logic diagram

SA = Bx, RA = Cx, SB = ABx, RB = BC + Bx, SC = x, RC =x & y = Ax

Example: Analyse the sequential circuit and determine the effect of unused states.


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p y q

001

011

100

010101

0/01/0

1/1

0/0

0/0

0/0

0/01/1

1/01/0

000

110

111

0/0

0/0

0/0

1/0

1/1

1/1

000 0 0

0 0 1

110 1 1

1 1 1

111 1 1

1 1 1

Unused states

The circuit is

self-starting and

self-correcting

since it

eventually goes

to a valid state

from which it

continues to

operate as

required. State diagram of the circuit


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000

111

110

101

100

011

010

001

State diagram of a 3 bit binary counter


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Count sequence Flip-flop inputs

A2 A1 A0 TA2 TA1 TA0

0 0 0 0 0 1

0 0 1 0 1 1

0 1 0 0 0 1

0 1 1 1 1 1

1 0 0 0 0 1

1 0 1 0 1 1

1 1 0 0 0 1

1 1 1 1 1 1

1

1

0

1

00 01 11 10A21 1

1 1

A1A0

1 1 1 1

1 1 1 1

A1

A2

A0TA2 = A1A0

TA1 = A0 TA0 = 1

Maps for a 3-bit binary counter

Excitation table for a 3-bit binary counter

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0

0A2

1

0A2

1

00 01 11 10A1A0

00 01 11 10A1A0

Logic diagram 0f a 3-bit binary counter


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Logic diagram 0f a 3 bit binary counter

CP

A2 A1 A0

TA2 = A1A0

TA1 = A0

TA0

= 1

1


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A B C

0 0 0

0 0 1

0 1 0

5 0 0

1 0 1

7 1 0

JA

0

0

1

X

X

X

KA

X

X

X

0

0

1

JB

0

1

X

0

1

X

KB

X

X

1

X

X

1

JC

1

X

0

1

X

0

KC

X

1

X

X

1

X

Flip-flop inputsCount sequence

Excitation table

Q(t) Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Dont care

011

111

Q: Design a counter that counts a repeated sequence as

shown below using JK flip-flop

Counting Sequence : 0, 1, 2, 4, 5 and 6

Dont care: 011 & 111


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x 1

x x x x

A

0

1

00

x x x x

x 1

A

0

1

1 x x

1 x x

A

0

1

x x x 1x x x 1

A

0

1

1 x x

1 x x

A

0

1

x 1 x x

x 1 x x

A

0

1

01 11 10 00 01 11 10

00 01 11 1000 01 11 10

00 01 11 10 00 01 11 10

KA = B

KB = 1

KC = 1

JA = B

JB = C

JC = B

BC

BC

BCBC

BC

BC

B


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1

Q Q

K J

Q Q

K J

Q Q

K J

B

Count

Pulses

(a) Logic Diagram

of Counter

000

001 110

010 101

100

111

011

(b) Logic Diagram

of Counter

Using K-maps

JA = B

KA = BJB = C

KB = 1

JC = B

KC = 1

Counter is self-starting

Unused states

011

111


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Design with State EquationPresent

State

Input Next

StateA B x A B

0 0 0 0 0

0 0 1 0 1

0 1 0 1 0

0 1 1 0 11 0 0 1 0

1 0 1 1 1

1 1 0 1 1

1 1 1 0 0

With D Flip Flops

Characteristic equation

Q(t+1) = D

Example # 1: State equations from the given table are:

A(t+1) = DA(A,B,x) = (2,4,5,6)

B(t+1) = DB(A,B,x) = (1,3,5,6)

DA = AB + Bx

DB = Ax + Bx +ABx

1

1 1 1

0

1

00 01 11 10A

Bx

1 1

1 1

0

1

00 01 11 10A

Bx Q Qt D

0 0 0

0 1 1

1 0 0

1 1 1DA = AB + BxDB = Ax + Bx

+ABx


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D Q

D Q

A

A

B

B

CP

x

DA = AB + Bx

DB = Ax + Bx +ABx Logic diagram


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Example # 2 : Design a sequential Circuit as per given conditions using D flip flops:-

A(t+1) = C + D

B(t+1) = A

C(t+1) = BD(t+1) = C

So

DA = C + D

DB = A

DC = BDD = C

Q D Q D Q D Q DAB

CP

CD

Example # 3:- Design a Sequential Circuit with JK flip-flops to satisfy


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p g q p p y

the given equations:-State Equations [Characteristic equation of JK flip-flops = Q(t+1) = (J) Q + (k) Q ]

A(t+1) = ABCD + ABC + ACD + ACD

B(t+1) = AC + CD + ABC

C(t+1) = BD(t+1) = D

Algebraic manipulations for matching characteristic equation of JK flip-

flops:

A(t+1) = (BCD + BC) A + (CD + CD)A

= (J)A + (K) A

J = BCD + BC = BC ------------(i)

(K) = (CD +CD) = CD + CD------(ii)

B(t+1) = (AC +CD) + (AC)B

B(t+1) = (AC + CD)(B+B) + (AC)B= (AC + CD) B + (AC + CD + AC) B

= (J)B + (K) B

J = AC + CD -------------(iii)

(K) = (AC + CD + AC) = AC + AD ---------- (iv)


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C(t+1) = B = B(C + C) = BC + BC

= (J) C + (K) C

J = B ----------(v)

(K) = B -------(vi)

D(t+1) = D = 1.D + 0.D

= (J) D + (K) D

J = K = 1

J = 1----------(vii)(K) = (O) = (K) = 1-----------(viii)

JA = BC ----------(i) KA = CD + CD-----------(ii)

JB = AC + CD --------(iii) KB = AC + AD -------(iv)

JC = B ---------(v) KC = B ----------(vi)JD = 1 ----------(vii) KD = 1 ------------(viii)

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Digital And Logic Devices No.5 (DLD Basic Devices(Basic Flip Flop (Sequential Circuit)) From APCOMS