Digital Circuit Testing and Testability

Parag K. Lala Ekctncal Enginecnng IVpartmcrt Nonh Caiottna Agncultural ind Tecimical Stale Univrixity Greensboro. Nocih Carolina

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v'ii Contents

Chapter 3 Testable Combinational Logic Circuit Design

3.1 The Reed-Muller Expansion Technique 3.2 Three-Level OR-AND-OR Design 53 3.3 Automatic Synthesis of Testable Loeic '** 3.4 Testable Design of Multilevel Combinational Circuits ^

3.4.1 Single Cube Extraction ^ 3.4.2 Double Cube Divisor ^

3.4.3 Extraction of a Double Cube Divisor and Its Complement « 3.5 Synthesis of Random Panem Testable Combmational Circuits Z. 3.6 Path Delav Fault Testable Combinational Logic Design ! 3.7 Testable PLA Design '^

References 77

Chapter 4 Test Generation for Sequential Circuits 79

4.1 Testing of Sequential Circuits as Iterative Combinational Circuits 79 4.2 State Table Verification gj 4.3 Test Generation Based on Circuit Structure 87 4.4 Functional Fault Models 92 4.5 Test Generation Based on Functional Fault Models 94

References 100

Chapter 5 Design of Testable Sequential Circuits 101

5.1 Controllability and Obser\ability 1 1 5.2 Ad Hoc Design Rules for Improving Testability 1^ 5.3 Design of Diagnosable Sequential Circuits 5.4 The Scan-Path Technique for Testable Sequential Circuit Design 5.5 Level-Sensitive Scan Design (LSSD)

5.5.1 Clocked Hazard-Free Latches 5.5.2 LSSD Design Rules 5.5.3 Advantages of the LSSD Technique

107 110 114 114 116 121 122

5.6 Random Access Scan Technique ^5 5.7 Partial Scan p-^ 5.8 Testable Sequential Circuit Design Using Nonscan Techniques ^'^ 5.9 Crosscheck 133 5.10 Boundary- Scan I3jl

References

140 Chapter 6 Built-in Self Test

141 6.1 Test Panem Generation for BiST 141

6.1.1 Exhaustive Testing |43 6.1.2 Pseudo-Exhaustive Pattem Generation

Contents 6.L3 ^^udo-Random Pattem Generator G.I.4 Deterministic Testing , ^

6.2 Output Response Analysis S\ 6.2.1 Transition Count , „ 6.2.2 Syndrome Checking 6.2.3 Signature Analvsis

6.3 Circular BIST

6.4 BIST Architectures 15<)

6.4.1 B I L B O (Buil t-In Logic Block Observer* »« 6.4.2 —^.- u.v i . \7ijMrivcri

Chapter 7 Testable Memory Design

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153 153 154 155

162

6.4.3 LOCST (LSSD On-Chip Self-Test) *^^ References 165

166

169 7.1 RAM Fault Models

169 7.2 Test Algorithms for RAMs .^2

7.2.1 GALPAT (Galloping Os and Is) 172 7.2.2 Walking Os and Is 173 7.2.3 March Test 173 7.2.4 Checkerboard Test 174

7.3 Detection of Pattern-Sensitive Faults 174 7.4 BIST Techniques for RAM Chips 179 7.5 Test Generation and BIST for Embedded RAMs 184

References 191

Appendix Markov Models ^"^

Index 195