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Digital Circuits II

An Overview of Altera FPGA Cyclone III Device

Family: EP3C16F484C6

References:

1) Cyclone III FPGA Family,

http://www.altera.com/devices/fpga/cyclone3/cy3-index.jsp

2) Cyclone III FPGA Handbook,

http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.p

df

Spring 2015

Paul I-Hai Lin, Professor

Dept. of Computer, Electrical and Information Technology

Indiana University-Purdue University Fort WayneProf. Paul Lin

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Outline

Overview of Cyclone III Family

The Architecture of the Cyclone III FPGA

Major Components of the Cyclone III

Design Resources

References• Altera Cyclone III Device Handbook Vol I,

http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pd

• The Cyclone III FPGA Architecture, http://www.altera.com/devices/fpga/cyclone3/overview/architecture/cy3-architecture.html

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The Altera Cyclone III FPGA Architecture

LVDS – Low Speed Differential Signals

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The Altera Cyclone III EP3C16F484C6 FPGA

Cyclone III FPGA Family Overview, http://www.altera.com/devices/fpga/cyclone3/overview/cy3-overview.html

Altera Cyclone III Device Handbook Vol I, http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf , 348 pages

Altera Cyclone III EP3C16F484C6

• 15408 LEs (Logic Elements)

• 56 M9k (9-Kbit) Embedded memory blocks/504 k total RAM bits

• 56 embedded multipliers

• 4 PLLs (Phase-Locked Loop, http://www.altera.com/support/devices/pll_clock/basics/pll-basics.html )

• 346 user I/O pins

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The Altera Cyclone III EP3C16F484C6 FPGA

The Logic Array Block (LAB) consists of 16 LEs and a LAB-wide control block.

Altera Cyclone III EP3C16F484C6 -15408 LEs (Logic Elements)

The Logic Element (LE)• An LE is the smallest unit of

logic in the Cyclone III device family architecture.

• Each LE has 4-inputs, a 4-input look-up table (LUT), a register, and output logic.

• The 4-input LUT is a function generator that can implement any function with four variables.

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The Altera Cyclone III EP3C16F484C6 FPGA

Memory Blocks Each M9k memory block of the Cyclone III device family

provides nine Kbits of on-chip memory.

Operating at up to 315 MHz for Cyclone III and up to 274 MHz for Cyclone III LS devices

This embedded memory structure consists of M9K memory block columns that you can configure as RAM, first-in-first-out (FIFO) buffers, or ROM.

Clock Networks and PLLs Include 20 global clock networks

PLLs (Phase Lock Loop) provide robust clock management and synthesis.

PLLs can be used for device clock management, external system clock management, and I/O interfaces

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The Altera Cyclone III EP3C16F484C6 FPGA

I/O Features Has eight I/O banks

All I/O banks support single-ended and differential I/O standards

Clock Networks and PLLs Include 20 global clock networks

PLLs (Phase Lock Loop) provide robust clock management and synthesis.

PLLs can be used for device clock management, external system clock management, and I/O interfaces

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The Altera Cyclone III Device Packaging Info

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The Altera Cyclone III EP3C16F484C6 FPGA – Logic

Element

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The Altera Cyclone III EP3C16F484C6 FPGA

The Logic Element

An LE is the smallest unit of logic in the Cyclone III device family architecture.

Each LE has the following features• A 4-inputs, a 4-input look-up table (LUT); The 4-input LUT is

a function generator that can implement any function with four variables.

• A programmable register

• A carry chain connection

• Each LE has outputs that drive the Local, Row, Column, Register Chain, Direct link

Programmable Register • Each register has data, clock, clock enable, and clear inputs

• Can be configure as D, T, JK or SR flip flops

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The Altera Cyclone III EP3C16F484C6 FPGA – Logic

Element

Altera Cyclone III Device Handbook Vol I, http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf , page 28

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The Altera Cyclone III EP3C16F484C6 FPGA

The Logic Element

LE Operating Modes:

• Normal mode For general purpose logic applications and combinational

functions

• Arithmetic Mode for implementing adders, counters, accumulators, and

comparators

The Quartus II software automatically chooses the appropriate mode for common functions:

• Counters

• Adders

• Subtractors, and

• Arithmetic functions

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The Altera Cyclone III EP3C16F484C6 FPGA

The Logic Element

Normal Mode• Inputs (six inputs)

4 data inputs from the LAB (Logic Array Block) interconnect are inputs to a 4-input LUT

The LE carry-in from the previous LE carry chain

The Register chain connection

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The Altera Cyclone III EP3C16F484C6 FPGA

The Logic Element

Arithmetic Mode • For implementing adders, counters, accumulators, and

comparators

• An LE arithmetic mode implements one 2-bit full adder and basic carry chain

• Can drive out registered and unregistered version of the LUT output

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Logic Array Blocks (LABs)

Each LAB consists of the following features

• 16 LEs, LAB control signals, LE carry chain, Register

chains, Local interconnect

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Summary & Conclusion

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