Digital Control of Switching Mode Power Supply Simone Buso 3

8/13/2019 Digital Control of Switching Mode Power Supply Simone Buso 3

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Simone Buso - UNICAMP - August 2011 1/74

Digital control of switching mode power supplies

Digital control of switching mode

power supplies

Simone Buso

University of Padova ITALY

Dept. of Information Engineering DEI


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Lesson 3

Continuous time controller discretization strategiesEffects of the computation delay

Derivation of a discrete time domain converter dynamic model

Digital proportional integral controller

Digital predictive (dead beat) controller

Physical approach to the derivation of the dead-beat controllerState space approachBasic robustness analysis of the dead beat controller


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kTS(k-1)TS (k+1)TS t

Forward

Euler

Backward

Euler

kTS(k-1)TS (k+1)TS t

Digital current mode control: PI current regulator

Discretization strategies: Euler and trapezoidal integration

Examples of numerical integration methods. Euler (left) and trapezoidal (right)


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The basic concept behind these discretization methods is very simple: wewant to replace the continuous time computation of integrals with some form of

numerical approximation. The two basic methods that can be applied to thispurpose are known as Euler integration and trapezoidal integration method.

As can be seen, the area under the curve is approximated as the sum of

rectangular or trapezoidal areas. The Euler integration method can actually beimplemented in two ways, known as forwardand backwardEuler integration,the meaning being obvious.

Writing the rule to calculate the area as a recursive function of the signal

samples, applying Z-transform to this area function, and imposing theequivalence with the Laplace transform integral operator, gives a directtransformation from the Laplace transform independent variable sto theZ-transform independent variable z.




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STz

1zs

=

20f

fS>

ST

1zs

=

20f

fS

>

1z1z

T2s

S += 10

ffS >Trapezoidal (Tustin)

Forward Euler

Backward Euler

3% distortion limitZ-formMethod




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Since the numerical integration methods imply a certain degree of

approximation, if we compare the frequency response of the controller beforeand after discretization, some degree of distortion, also known as frequencywarping effect, can always be observed.

The table also shows the condition that has to be satisfied to make thedistortion lower that 3% at a given frequency f. The condition is expressed as alimit for the ratio between the sampling frequency fS= 1/TSand the frequencyof interest, f.

As can be seen, the trapezoidal integration method, that generates the so-called Tustin Z-form, is more precise than the Euler method, and, as such,guarantees a smaller distortion at each frequency or, equivalently, an higher3% distortion limit, that is as high as one tenth of the sampling frequency.




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Ideally, it is also possible to pre-warp the controller transfer function so as tocompensate the frequency distortion induced by the discretization method and

get an exactphase and amplitude match of the continuous time and discretetime controllers at onegiven frequency, that is normally the desired crossoverfrequency. Nevertheless, the overall performance improvement is normallynegligible.

Lets apply backward Eulers discretization to our PI current controller.



sK

Ks1

K)s(PI I

P

I

+

=

Substituting the appropriate Z-form we get:


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( )1z

zTKK

1z

KzTKK

Tz

1z

K

K

Tz

1z1

K)z(PISIP

PSIP

S

I

P

S

I

+=

+=

+

=



Discrete time integrator

The above rational transfer function can be simplified to give the discrete time

implementation of the PI controller. As we can see, the final expressioncomprises a discrete time integrator, preserving the basic PI structure. Aparallel implementation of the discrete time PI is immediate to derive.


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K

P

+ m(k)

KITS

+

I(k)

z-1

+

+

mP(k)

mI(k)

z-1

m(k-1)

calculation delay



Block diagram representation of the digital PI controller


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Discrete time PI current controller: implementation issues


The following issues need to be clarified with respect to the discrete time PIcontroller implementation:

- the use of different discretization strategies;- the large signal behavior of the digital integrator;- the role of the computation delay;

We will discuss all of them in the following.

The use of Tustin Z-form, determines a different rational transfer function fo the

digital PI. The differences with respect to the previous result can be better putinto evidence by transforming the PI mathematical expression into analgorithm, that can be directly programmed into any microcontroller or DSP.


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+=+=

+=

)k(m)k(K)k(m)k(m)k(m

)1k(m)k(TK)k(m

IIPIP

IISII

Euler based digital PI algorithm: please note that index krepresents in acompact form the time instant kT

S, where T

Sis the sampling period.

Tustin based digital PI algorithm.

+=+=

++

=

)k(m)k(K)k(m)k(m)k(m

)1k(m

2

)1k()k(TK)k(m

IIPIP

III

SII


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As can be seen, the structure of the two expressions is similar, the only

difference being determined by the computation of the integral part that, in theTustin PI algorithm, is not based on a single current error value, but rather onthe moving average of the two most recent current error samples.

This relatively minor difference is responsible for the lower frequencyresponse distortion of the Tustin transform.

It is worth noting that the proportional and integral gains for the two differentversions of the discretized PI controller are exactly the same. As can be

seen, in both cases we find that the proportional gain for the digital controlleris exactly equal to that of the analog controller, while the digital integral gaincan be obtained simply by multiplying the continuous time integral gain andthe sampling period.


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and the implementation of the proper control algorithm. Note that even theapplication of pre-warping does not change much the values of the controllergains, especially when a relatively high ratio between the sampling frequencyand the desired crossover frequency is possible.

In summary, we have seen that, given a suitably designed analog PIregulator, the application of any of the considered discretization strategies

simply requires the computation of the digital PI gains, as in the following:

=

=

Pdig_P

SIdig_I

KK

TKK


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10

20

30

40

50

Magnitude[dB

]

102

103

104

105

-90

-45

0

Phase[deg]

Frequency [rad/s]

Bode plots of the different PI realizations.

This is further confirmed bythese Bode plots, that refer

to. the original continuoustime PI controller and to eachone of its three discretizedversions (Euler, Tustin and

pre-warped). As can beseen, with our designparameters and samplingfrequency, the plots arepractically undistinguishable.


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The integral part wind-up phenomenon can take place any time the PIcontrollers input signal, i.e. the regulation error, is different from zero for

relatively large amounts of time.

This typically happens in the presence of large reference amplitude variationsor other transients, causing inverter saturation. The problem is determined by

the fact that, if we do not take any countermeasure, the integral part of thecontroller will be accumulating the integral of the error for the entire transientduration.

Therefore, when the new set-point is reached, the integral controller will bevery far from the steady state and a transient will be generated on thecontroller variable, that typically has the form of an overshoot.


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It is fundamental to underline that this overshoot is not related to the small signalstability of the system. Even if the phase margin is high enough, the transient willalways be generated, as it is just due to the way the integral controller reacts to

converter saturation.

3 4 5 6 7 8-30

-20

-10

0

10

20

30

[ms]

[A]

3 4 5 6 7 8-30

-20

-10

0

10

20

30

[ms]

[A]

3 4 5 6 7 8-30

-20

-10

0

10

20

30

[ms]

[A]

I

IOREF

IO

Dynamic behaviour of the PI controller during saturation.


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The solution to this problem is based on the dynamic limitation of the integralcontroller output during transients. Transients can be detected monitoring the

output of the controller proportional part: in a basic implementation, any timethis is higher than a given limit, the output of the integral part of the controllercan be set to zero. Integration is resumed only when the regulated variable isagain close to its set-point, i.e. when the output of the proportional part getsbelow the specified limit.

More sophisticated implementations of this concept are also possible, wherethe limitation of the integral part is done gradually, for example keeping the sumof the proportional and integral outputs in any case lower or equal than a

predefined limit.

This implementation, of course, requires a slightly higher computational effort,that amounts to the determination of the following quantity, where mMAX is the

controller output limit: |LI(k)| = mMAX - |Kp

I(k)|.


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KP

+ m(k)

KITS+

I(k)

z

-1

+

+

mP(k)

mI(k)

Anti wind-up

mMAX

LI(k)

Block diagram representation of the digital PI controller with anti wind-up action


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3 4 5 6 7 8-30

-20

-10

10

20

30

[ms]

[A]

3 4 5 6 7 8-30

-20

-10

10

20

30

[ms]

[A] I

OREF

O

Dynamic behaviour of the PI controller during saturation with anti wind-up


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In our discussion, we have shown how the delay effect associated to theDPWM operation can be taken care of. An additional complication we have todeal with is represented by the fact that the digital control loop actually hides asecond, independent source of delay: this is the control algorithm computationdelay, i.e. the time required by the processor to compute a new m value, giventhe input variable sample.

Although digital signal processors and microcontrollers are getting faster andfaster, in practice, the computation time of a digital current controller alwaysrepresents a significant fraction of the modulation period, ranging typicallyfrom 10% to 40% of it. A direct consequence of this hardware limitation is that,

in general, we cannot compute the input to the modulator during the samemodulation period when it has to be applied. In other words, the modulatorinput, in any given modulation period, must have been computed during theprevious control algorithm iteration. Dynamically, this means that the controlalgorithm actually determines an additional one modulation period delay.

Di it l t l f it hi d li


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One could consider this analysis to be somewhat pessimistic, becausepowerful microcontrollers and DSPs are available today, that allow the

computation of a PID routine in much less than a microsecond.

However, it is important to keep in mind that, in industrial applications, the costfactor is fundamental: cost optimization normally requires the use of theminimum hardware that can fulfil a given task. The availability of hardware

resources in excess, with respect to what is strictly needed, simply identifies apoor system design, where little attention has been paid to the cost factor.

Therefore, the digital control designer will struggle to fit his or her control

routine to a minimum complexity microcontroller much more often than he orshe will experience the opposite situation, where a high speed DSP will beavailable just for the implementation of a digital PI or PID controller.



Digital control of s itching mode po er s pplies


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The conventional approach to tackle the problem consists in assuming a wholecontrol period is dedicated to computations. In this case, in order to get from

the digital controller a satisfactory performance, the calculation delay effect hasto be included from the beginning in the analog controller design.

Practically, this can be done increasing the delay effect represented by thePad approximation TS. After that, the procedure for the controller synthesisthrough discretization can be re-applied.

It is important to underline once more that, if the analog controller is not re-designed and a significant calculation delay is associated to the implemented

algorithm, the achieved performance can be much less than satisfactory.



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An example of this situation is shown in the figure below, where a calculationdelay equal to one modulation period is considered. Note how the stepresponse tends to be under-damped.



0.01 0.0102 0.0104 0.0106 0.0108 0.011

6

7

8

9

10

11

12

13

14

[A]

IO

[s]

t



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In this case instead, the dynamic response of the re-designed controller issmoother, but a significant reduction of its speed can be observed.



Please note that the result has been obtained by reducing the crossover

frequency to fS/15, while keeping the same phase margin of the original design.

0.01 0.0102 0.0104 0.0106 0.0108

8

9

10

11

12

13

14

[A]

IO

t[s]



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The previous example shows that, when the maximum performance is required,this conventional approach may be excessively conservative. Penalizing the

controller bandwidth to cope with the computation delay, the synthesis procedurewill unavoidably lead to a worse performance, with respect to conventionalanalog controllers.

This is the reason why, in some cases, a different modelling of the digital

controller can be considered, that takes into account the exact duration of thecomputation delay and so, by using modified Z-transform, exactly models theduty-cycle update instant within the modulation period.

Doing this, a significant performance improvement can be achieved and thepenalization of the digital controller with respect to the analog one can beminimized.





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Digital PI current controller: discrete time synthesis


What we have described so far is a very simple digital controller designapproach. It is based on the transformation of the sampled data system into a

continuous time equivalent, that is used to design the regulator with the wellknown continuous time design techniques.

The symmetrical approach is possible as well. In this case, the sampled datasystem is transformed into a discrete time equivalent, that can be used to

design the controller directly in the discrete time domain.

A detailed and precise discrete-time converter model is generally based on theintegration of the linear and time-invariant state space equations, associated

to each switch configuration (i.e. turn-on and turn-off).

The state variable time evolutions, obtained separately for each topological orswitch state, are linked to one another exploiting their continuity, i.e. imposingthe final state of one configuration to be the initial state of the next.



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This approach, that requires the use of exponential matrixes, leads to ageneral discrete-time state-space model and precisely represents the systemdynamic behaviour in the discrete-time domain.

Therefore, in principle, it represents a very good modelling approach fordigitally controlled power electronic circuits.

Nevertheless, it is not very commonly used, mainly for two reasons:

i) the obtained discrete time model depends on the particular type ofmodulator adopted, as the sequence of state variable integrations, one for

each topological state, depends on the modulator mode of operation (leadingedge, trailing edge, etc.);

ii) the exponential matrix computation is relatively complex and, therefore, notalways practical for the design of power electronic circuit controllers.





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g g p pp

G(s)x(t)

xsREF(t)

Digitalcontroller

e-sTd

Converter

transferfunction

Pulse Width Modulator

ZOH

sx(t)

+ -

Computationdelay

xs(t)+

-c(t)

msr(t) m

s(t)

Reg(z)G(s)

x(t)x

sREF(t)

Digitalcontroller

e-sTd

Converter

transferfunction

Pulse Width Modulator

ZOHZOH

sx(t)

+ -

Computationdelay

xs(t)+

-c(t)

msr(t)m

sr(t) m

s(t)m

s(t)

Reg(z)

A more direct, equivalent, approach to discrete time converter modelling isdescribed in the figure below, where the PWM modulator is represented usingthe frequency domain model, PWM(s), G(s), the converter transfer function, isobtained from the continuous-time converter small-signal model, and xs(t) is thesampled output variable, that has to be controlled by the digital algorithm.





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g g p pp

Remember that the Zero Order Hold (ZOH) function that, when cascaded toan ideal sampler, models the conversion from sampled time variables intocontinuous time variables, is, in our case, internal to the PWM model, and,therefore, does not appear right after the sampler.

Now, if we want to correctly represent the transfer function between thesampled time input variable, msr, and the continuous time output variable of

the modulator, a gain equal to TShas to be added to the modulator transferfunction PWM(s) as we found out in Lesson 1.



PWM(s) G(s)e-sTd xs(k)msr(k)

GT(z)

PWM(s) G(s)e-sTd xs(k)msr(k)

GT(z)



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)]s(G)s(PWMTe[Z)z(G ssT

Td

=

This z-domain approach is very powerful: once the Z-transform of the termsincluded within the dashed box is calculated, it will be capable of correctlyquantifying the difference in the converter dynamics determined by the differentuniformly sampled modulator implementations (trailing edge, leading edge,triangular carrier modulation, etc..). In addition, it takes into account the exactduty-cycle update instant. The calculation to be performed is the following:

If we are not interested in the exact model, the calculation can be simplified ifwe observe that:

1. the computation delay is often equal to one modulation period. Therefore,a z-1 term can be used to model it instead of the continuous timeexponential term.

2. The PWM block transfer function can often be assumed to be equal to that

of an ideal ZOH.





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ZOH G(s)z-1xs(k)msr(k)

GT(z)

ZOH G(s)z-1xs(k)msr(k)

GT(z)



Under these simplifying assumptions the block diagram of the continuous timesub system reduces to:

We can rapidly perform the calculation considering a simpler expression forG(s) and the usual expression for the ZOH transfer function, i.e.

S

SDC

sL

TV2)s(G =

s

e1)s(H

SsT=and



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)1z(z

1

L

TV2

s

1Z)z1(z

L

V2

Ls

V2

s

e1Zz)z(G

S

SDC

2

11

S

DC

S

DC

sT1

T

S

=

=

=

=



It is immediate to find that, in this case:

It is interesting to observe that, with the particular G(s) expression weconsidered, the exact GT(z) turns out to be identical to the one above.



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Once the transfer function GT(z) is known, the PI controller design can beperformed directly in the discrete time domain. Several methods, e.g. pole

allocation, root locus, can be used as the design strategy.

The discrete time synthesis allows us to easily study a different situation, wherethe controller performance is optimized by implementing a minimum delayregulation loop.

Indeed, in some particular, very demanding cases, even the double updatemode of operation for the DPWM excessively penalizes the achievablecontroller performance.

Much better results can be obtained if the time distance between duty-cycleupdate and sampling is minimized.



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This can be obtained shifting the current sampling instant towards the duty-cycle update instant, leaving just enough time for the ADC to generate the new

input sample and to the processor for the control algorithm calculation.

Following this approach and thanks to the continuous increase ofmicrocontrollers computational power and to the use of DSPs and FPGAs,

which are able to compute the control algorithm in smaller and smallerfractions of the switching period, it is possible to reduce the control delay to alittle fraction of the sampling period.

The reduced delay, in turn, allows to push the controller bandwidth higher,

reducing the gap that separates purely analog and digital controlimplementations.

Digital current control with minimum computation delay




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PWM carrier

PWMupdate

PWMupdate

TC

x(t)

sampling

driver signalton tofftoff

c(t)

Td





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The situation under investigation is depicted in the figure, where Td is, onceagain, the time required by AD conversion and calculations.

Time TC is instead available for other non-critical functions or external controlloops.

As can be seen, since Td


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In order to quantify the effectiveness of this reduction, an accurate discrete-time model is needed. To this purpose, we can consider again the same block

diagram, and replace the PWM block with a Zero-Order-Hold (ZOH), which, aswe have seen, represents a very good approximation, especially in the case oftriangular carrier waveform.

Now, if the control delay Tdwere a sub-multiple of the sampling period TS, thecontinuous system could be easily converted into a discrete-time model usingconventional Z-transform and considering Tdas the sampling period. In ourcase, the delay Td is a generic fraction of sampling period TSand therefore,modified Z-transform has to be used to correctly model the system.



PWM(s) G(s)e-sTd x

s

(k)m

s

r(k)

GT(z)

PWM(s) G(s)e-sTd x

s

(k)m

s

r(k)

GT(z)



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If we define:

we can write the following relation for our block diagram.

S

d

TTp = 1

[ ] ),()()()()( 1110

)1(

)(1

pzGsGZTkTgzesGsHZ mdSk

kTps

sG

S

===

=

43421


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The modified Z-Transform maintains all the properties of the conventional Z-transform, since it is simply defined as the Z-transform of a delayed signal.

The results of the modified Z-transform application to particular cases of interestare usually available in look-up tables in digital control textbooks.

In our example case, the discrete-time transfer function between the modulatingsignal M(z), input of the DPWM, and the delayedinductor current IO(z) can bewritten as

)1z(z

)1p(pz

L

TV2

)z(M

)z(I

S

SDCO

=

Note that for p=0, we get the usual expression of slide 32.



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In order to quantify the advantages of exactly modelling the delay, i.e. ofconsidering p >0, let us take in to account, as a benchmark parameter, the

achievable current loop bandwidth.

We assume, for simplicity, that the current regulator is purely proportional andthat we want to achieve a given phase margin, for example equal to +50.

Varying parameter p, we now look for the frequency where the transfer functionbetween modulating signal and inverter current shows a -130 phase rotation.That will be the phase rotation of the open loop gain as well, as our controller ispurely proportional.

Therefore, we can define that as the achievable current loop bandwidth (BWi)meaning that a suitable proportional gain exists that makes the transferfunction crossover frequency equal to BWi.



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Achievable current loop bandwidth (BWi) versus p

fs/6.2f

s/9f

s/13.4BW

i

0.80.50p



same limit for analog design!



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Simply by shifting the sampling instant towards the duty-cycle update instant,a significant improvement in the achievable current loop bandwidth can be

obtained. For a 20% delay, we practically reach the same conditionconsidered for the analog design example.

It also possible to note that only with p = 0(sampling in the middle of turn-offtime) or p = 0.5 (sampling in the middle of turn-on time), the sampled currentis also the average inductor current, while, for other values of p, some kind ofalgorithm is needed for the compensation of the current ripple, possiblyaccounting for dead-time effects as well.

For this reason, the application of the concept here described to currentcontrol is fairly complicated, while it can be much more convenient for thecontrol of other system variables, where the switching ripple is smaller.



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Digital current mode control: predictive controller

We now move to a totally different control approach, describing the predictive,or dead-beat, current control implementation. In principle, the dead-beat controlstrategy we are going to discuss is nothing but a particular application case ofdiscrete time dynamic state feedback and direct pole allocation, and, as such,

its formulation for our VSI model can be obtained applying standard digitalcontrol theory. However, this theoreticalapproach is not what we are going tofollow here. Instead, we will present a different derivation, completely equivalentto the theoretical one, but closer to the physical converter and modulator

operation. We will discuss the equivalence of the two approaches later on.

L. Malesani, P. Mattavelli, S. Buso: Robust Dead-Beat Current Control for PWM

Rectifiers and Active Filters, IEEE Transactions on Industry Applications, Vol. 35,No. 3, May/June 1999, pp. 613-620.

G.H. Bode, P.C. Loh, M.J. Newman, D.G. Holmes An improved robust predictivecurrent regulation algorithm, IEEE Transactions on Industry Applications, Vol. 41,no. 6, Nov/Dec 2005, pp. 1720-1733.



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2VDC

S

SS

R

Ls1

1R1

+

IO

IOREF(k)

GTI

m(k)

Inverter gain Load admittance

Current transducer

( )sG

Microcontroller or DSP

( )kISO

I(k)

Dead beat control

algorithm

( )kESSGTE

ES

Voltage transducer



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LS RS

ES

+IO

VOC

+

kTS (k+1)TS (k+2)TS

TS

VOC

IO

VOC

IO

IOREF

Tlimit

-VDC

+VDC

t



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( ) ( )[ ]

( ) ( ) ( ) ( )[ ]kE1kEkV1kVL

T)k(I

1kE1kV

L

T)1k(I)2k(I

SSOCOC

S

S

O

SOC

S

S

OO

++++=

=++++=+

The reasoning behind the physical approach to predictive current control is quitesimple and can be explained referring to an average model of the VSI and itsload. At any given control iteration, we want to find the average inverter outputvoltage, , that can make the average inductor current, , reach its

reference by the end of the modulation period followingthe one when all thecomputations are performed. In other words, at instant kTSwe perform thecomputation of the value that, once generated by the inverter, during themodulation period from (k+1)TS to (k+2)TS, will make the average current equal

to its reference at instant (k+2)TS. The resulting control equation is:

OCV OI

OCV


Di i l d l di i ll


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Assuming now that the phase voltage ES is a slowly varying signal, as it isoften the case, whose bandwidth is much lower than the modulation andsampling frequency, it is possible to consider , thus obtainingthe following dead-beat control equation

where can be replaced by IOREF(k), the desired set-point.

( ) ( )kE1kE SS +

( ) ( ) [ ] ( )kE2)k(I)2k(IT

LkV1kV

SOO

S

S

OCOC +++=+

)2k(IO

+


Di it l t d t l di ti t ll


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( ) ( ) ( )[ ] ( )kEVG2

12)k(IkI

VG2

1

T

Lkm1km S_S

DCTE

S_OS_OREF

DCTIS

S

+

+=+

In general, the set-point for the average inverter output voltage it provides uswith, will have to be correctly scaled down, so as to fit it to the digital pulsewidth modulator. The fitting is normally accomplished normalizingthe output ofthe controller to the inverter voltage gain. In addition to this, the controlequation has to be modified also to properly account for the transducer gains ofboth current and voltage sensors. It is easy to verify that an equivalent controlequation, taking into account the transducer gains and voltage normalization, isthe following:


Digital current mode control predictive controller


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0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016-15

-10

-5

0

5

10

15IO

[A]

[s] t




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0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016-15

-10

-5

0

5

10

15IO

[A]

[s] t

9.8 9.85 9.9 9.95 10 10.05 10.1 10.15 10.2

x 10-3

7

8

9

10

11

12

13

14IO

[A]

[s] t




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Derivation of the predictive controller through dynamic state feedback


+=

+=

DuCxy

BuAxx&

Our VSI can be described in the state space that, as we recall from the

discussion reported in Lesson 1, can be used to relate average inverterelectrical variables. In this case x = [ ] is the state vector, u = [ , ]T is theinput vector, y = [ ] is the output variable and the state matrixes are:OI

OCV SEOI

A = [-RS/LS], B = [1/LS, -1/LS], C = [1], D = [0, 0]




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It is possible to derive a zero order hold discrete time equivalent of theprevious continuous time model considering the following system

where, by definition, and .

Computation of and yields:

( ) ( ) ( )

( ) ( ) ( )

+=

+=+

kDukCxky

kukx1kx

STAe

= ( ) BAI 1 =

=

==

S

S

S

S0R

S

TLR

S

TLR

0RT

L

R

TA

L

T

L

T

R

1e

R

1e

1ee

S

SS

SSS

S

SS

S

S

S




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( ) ( ) ( ) ( )

( ) ( )

=

+=+

kIky

kEL

TkV

L

TkI1kI

:

O

S

S

SOC

S

SOO

We can derive the predictive controller as a particular case of state feedbackand pole placement. In order to show that, we may re-write the stateequations explicitly. We get the following result:

( ) ( ) ( ) ( )kIkIKkVK1kV OOREF1OC2OC +=+

We can then represent the controller by means of the following stateequation:




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+1z

+1

1

S

S

L

T

+ +

-OCV

SE

y =OI

ideal disturbance

compensation

- IOREF

( )kIO

1z

+

+

K1

K2

controller with

calculation delay

( )kVOC

A

SE

+

approximated

disturbance

compensationSE

K3




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( ) ( ) ( ) ( )

( ) ( ) ( ) ( )[ ] ( )

( ) ( )( )

=

++=+

+=+

kV

kI]01[ky

kEKkIkIKkVK1kV

kEL

TkV

L

TkI1kI

:

OC

O

S3OOREF1OC2OC

S

S

SOC

S

SOO

A

The interconnection of and the controller feedback generates a new,augmented, dynamic system, indicated by A. This is described by the followingequations:

that correspond to the state vector augmentation to xA = [ ]T, to the new

input vector uA = [ IOREF ]T and to the approximated compensation of the

exogenous disturbance, governed by gain K3.

OI OCV

SE




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CA = [1 0], DA = [0 0]

=

21

S

S

A

KK

L

T1[ ]

==

13

S

S

2A1AA

KK

0L

T

The corresponding state matrixes are the following:




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g p

1K,T

L

K 2S

S

1 ==

the eigenvalues of A move to the origin of the complex plane. As is wellknown, this is a sufficient condition to achieve a dead-beat closed loop

response from the controlled system. Alternatively, the position of poles on thecomplex plane can be chosen to achieve a different closed loop behaviour, forexample one equivalent to that of a continuous time, first order, stable system,characterized by any desired time constant. Indeed, with the direct discrete

time design of the regulator, the designer has, in principle, complete freedomin choosing the preferred pole allocation.

It is possible to determine parameters K1, K2 and K3 to get the desired poleallocation and disturbance compensation. It is easy to verify that choosing:




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g p

Applying standard state feedback theorems and after simple calculations wefind:

which corresponds, as expected, to a dynamic response equivalent to a pure

two modulation period delay. Similarly, we can compute the closed looptransfer function from the disturbance to the output. We find:

( ) ( ) 22A1AAOREF

O

z

1zICz

I

I==

( ) ( ) ( )3SS

21A

1

AA

S

O

K1zL

T

z

1

zICzE

I

+==




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As can be seen, there is no value of K3 that can guarantee a zero transferfunction from disturbance to output. This is due to the fact that thecompensation term of the controller equation is one step delayed with respect tothe control output and, as such, is only approximated. In these conditions, thebest we can do is to minimize the transfer function between disturbance and

output. It is easy to verify that the choice K3 = 2 achieves this minimization.Rewriting the equation in the time domain and imposing K3 = 2 we find:

that, under the assumption of slowly varying ES, guarantees the minimumdisturbance effect of the output. Having determined the controller parametersK

1

, K2

and K3

, we are now ready to explicitly write the control equation, thatturns out to be:.

( ) ( )[ ]2kE1kEL

T)k(I SS

S

S

O +=

( ) ( ) ( ) ( )[ ] ( )kE2kIkIT

LkV1kV SOOREF

S

SOCOC ++=+




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A simple improvement of the predictive controller is obtained deriving anestimation equation, that allows to save the measurement of the phase voltageES. As in the control equations case, the estimation equation can be derived bysimple physical considerations. Indeed, re-writing the control equation one stepbackward we get

from which we can extract an estimation of ES(k-1). Simple manipulations of(3.2.17) yield

It is typically possible to improve the quality of the estimation by using someform of interpolation or filtering, that can remove possible estimator instabilities.

( ) ( )[ ]1kE1kVL

T)1k(I)k(I

SOC

S

S

OO =

( ) ( ) ( ) ( )[ ]1kIkITL

1kV1kE OOS

S

OCS =




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Robustness of the predictive controller

( ) ( ) [ ] ( )kE2)k(I)2k(IT

LLkV1kV

SOO

S

SS

OCOC ++

+=+

Considering the dead beat control equation, we see that several parameterscontribute to the definition of the algorithm coefficients, each of them being a

potential source of mismatch. To give an example of the analysis procedure wecan apply to estimate the sensitivity of the controller to the mismatch, we beginby referring, for simplicity, to the following simplified equation, where the onlyparameter we need to take into account is inductor LS.

Note that parameter LShas been replaced by LSLS, thus putting intoevidence the possible presence of an error, LS, implicitly defined as apositive quantity.




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The analysis of the impact of LS on the systems stability requires thecomputation of the systems eigenvalues. Referring to the procedure outlined inbefore, we can immediately find the state matrix corresponding to the previousequation and the usual control equation. This turns out to be:.

=

1T

LL

L

T1

S

SS

S

S

'

A

It is now immediate to find the eigenvalues of the above matrix. These aregiven by the following expression:

'

A

S

S

2,1

S

S

2,1L

L

L

L =

=




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From the above result we see that the magnitude of the closed loop systemseigenvalues is limited to the square root of the relative error on LS. This meansthat, unless a higher than 100% error is made on the estimation of LSor,equivalently, unless a 100% variation of L

Stakes place, due to changes in the

operating conditions, the predictive controller will keep the system stable.

Please note that, interestingly, this result is independentof the samplingfrequency.

Of course, even if instability requires bigger than unity eigenvalues, the goodreference tracking properties of the predictive controller are likely to get lost,even for smaller than unity values of the relative error.




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0.0096 0.0098 0.01 0.0102 0.0104 0.0106 0.0108

2

4

6

8

10

12

14

LS = 0.5LS

LS = 0.95LS

IOREF




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As it might be expected, the robustness of the predictive controller tomismatches gets worse if the estimation of the phase voltage is used insteadof its measurement. The analytical investigation of this case is a little moreinvolved than the previous one, but still manageable with pencil and papercalculations. The procedure consists in writing the system, controller andestimator equations, either solving them using Z-transform to find thereference to output transfer function, or, equivalently, arranging them to get

the state matrix, and, finally, examining the characteristic polynomial of thesystem. Following this procedure, we get:

( )S

S

S

S3

LL2z

LL3zz =





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1

-1

1

(a)

(b)(c)

(c)(b)

(c)(b)

Re(z)

Im(z) Plot of the closedloop systemeigenvalues asfunctions of the

parameterLS

mismatch.

a) LS

= 0.

b) LS = 0.2LS.

c) LS

= 0.3LS.




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Converter dead-times are another non-ideal characteristic of the VSI that is nottaken into account by the model the predictive controller is based on. In a

certain sense, their presence can be considered a particular case of modelmismatch. We know from previous lessons that the presence of dead-timesimplies a systematic error on the average voltage generated by the inverter.The error has an amplitude that depends directly on the ratio between dead-time duration and modulation period and a sign that depends on the load

current sign. As we did before, we can model the dead times effect as asquare-wave disturbance having a relatively small amplitude (roughly a fewpercent of the dc link voltage) and opposite phase with respect to the loadcurrent. We can consider this disturbance as an undesired component that is

summed, at the system input, to the average voltage requested by the currentcontrol algorithm.




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The disturbance should be, at least partially, rejected by the currentcontroller. The effectiveness of the input disturbance rejection capabilitydepends on the low frequency gain the controller is able to determine forthe closed loop system. And here is where the dead-beat controller showsanother weak point. We have seen how the dead-beat action tends to getfrom the closed loop plant a dynamic response that is close to a pure delay.Unfortunately, this implies a very poor rejection capability for any input

disturbance. To clarify this point we can again compute the closed looptransfer function from the exogenous disturbance to the output .Indeed, this is the transfer function experienced by the dead-time inducedvoltage disturbance. Simple calculations yield:

SEOI

( ) ( )1zL

T

z

1z

E

I

S

S

2

S

O+=





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In terms of disturbance rejection this result is rather disappointing. Plotting thefrequency response we find that it is practically flat from zero up to the Nyquistfrequency, i.e. there is no rejection of the average inverter voltage disturbance.

Consequently, we cannot expect the deadbeat controller to compensate thedead times effect. This means that, unless some external, additionalcompensation strategy is adopted, a certain amount of current distortion islikely to be encountered.



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Dead time compensation strategies


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The dead-beat controller requires some form of dead time compensation.Compensation methods can be divided into: i) closed loop or on-line and ii)open loop or off-line.

The best performance is offered by closed loop dead time compensation,that requires, however, the measurement of the actual inverter average outputvoltage. Its comparison with the voltage set-point provided to the modulatorgives sign and amplitude of the dead-time induced average voltage error, that

can therefore be compensated with minimum delay, simply by summing to theset-point for the following modulation period the opposite of the measurederror.

The need for measuring the typically high output inverter voltage requires theuse of particular care. The estimation of the inverter average output voltage isnormally done by measuring the duration of the voltage-high and voltage-lowparts of the modulation period, i.e. by computing the actual, effective outputduty-cycle.






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However, much more often, off line compensation strategies are used. Theseoffer a lower quality compensation, but can be completely embedded in themodulation routine programmed in the microcontroller (or DSP), requiring no

measure.

The off line compensation of dead-times is based on a worst case estimation ofthe dead-time duration and on the knowledge of the sign of the output current,that is normally inferred from the reference signal (not from the measured

output current, to avoid any complication due to the high frequency ripple).Given both of these data, it is possible to add to the output voltage set-point acompensation term that balances the dead-time induced error.

The method normally requires some tuning, in order to avoid under or over

compensation effects. The results are normally quite satisfactory, unless a veryhigh precision is required by the application, allowing to eliminate the amplitudeerror and to strongly attenuate the crossover distortion phenomenon.


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