DIGITAL CONTROL SYSTEMS IV - MWEBhome.mweb.co.za/rf/rfitch/eidbs4/DbsStGds.pdf · DIGITAL CONTROL SYSTEMS IV ... Nagle H.T., Digital Control System Analysis and Design. c) Kuo,

VUT Vaal University of Technology

DIGITAL CONTROL SYSTEMS IV

Learning Guide: Second Semester 2017

Module Code: EIDBS4A

iiLearning Guide – Digital Control Systems IV

INDEX PART I Module Information 1. Word of welcome ……………..………………………….….……………… iii 2. Contact persons …………………………………………………………….. iii 3. Rationale for the module ……...……………………………………………. iii 4. Prerequisites ………………………………………………………………… iii 5. Learning material and reference textbooks .………………………………… iii 6. Assessment ……………………………………………………………...….. iii 7. Icons used in this study guide .…….………………………………...……... v PART II Learning Units

Unit 1

1. Chapter 1 – Sampled Data Systems .…………..………………….…….…… 1-1 2. Chapter 2 – Transfer Functions …………..…………...………….….…....…. 2-1 3. Chapter 3 – Time Domain Analysis …….…………………...…………....…. 3-1 Unit 2

4. Chapter 4 – Stability Analysis ……………....….…………...………….......... 4-1 5. Chapter 5 – Root Locus Techniques ……….………...……...…………....…. 5-1 6. Chapter 6 – Digital Controller Design …….…………...……….………....…. 6-1 Unit 3

7. Project 7.1 Project outcome ……..……………...…………………….....…...…… 7-1 7.2 Project schedule ……….………………...….……………...……...…. 7-1 7.3 Assessment …………...………..……………..….....………………… 7-10 7.4 Apendix …......………...………..……………..….....………………… 7-10

iiiLearning Guide – Digital Control Systems IV

1. WORD OF WELCOME The Department of Process Control and Computer Systems, welcomes you as a student to the Faculty of Engineering at the Vaal University of Technology. The department strives towards integration of existing knowledge with new knowledge and to afford the student the ability to think logically, gain knowledge of Electrical Engineering, and specifically Digital Control Systems, in order to make a positive contribution to the field of Industrial Instrumentation and Electrical Engineering.

2. CONTACT PERSONS

Title and Surname Office Telephone number and e-mail addressProf MO Ohanga (HOD) R007 016 950 9323 [email protected] Ms. R Mwale (Administrator) R007 016 950 9254 [email protected] Mr. R Fitchat (Lecturer) S115 016 950 9432 [email protected]

3. RATIONALE FOR THE MODULE On completion of this module you should be knowledgeable in the basic concepts underlying modern digital control systems, z transforms, pulse transfer functions, stability analysis, root locus techniques and digital controller design.

4. PREREQUISITES A firm understanding of classical control systems as well as complex algebra, is essential in the study of Digital Control Systems IV. It is therefore strongly recommended that students successfully complete the courses in Control Systems III (EIBEH III) and Mathematics II (AMISK II), before commencing with their studies in Digital Control Systems IV.

5. LEARNING MATERIAL AND REFERENCE TEXTBOOKS This learning guide as well as the course material and previous evaluations, will be made available to students at the beginning of the semester. Additional reference textbooks: a) Ogata, Katsuhiko, Discrete-Time Control Systems. b) Phillips C.L., Nagle H.T., Digital Control System Analysis and Design. c) Kuo, Benjamin C., Automatic Control Systems. d) Min J.L.,Schrage J.J., Designing Analog and Digital Control Systems. Additional information may be available from: http://home.mweb.co.za/rf/rfitch

6. ASSESSMENT Module assessment will take place on a continuous basis, and for this purpose the module is divided into three units.

Unit 1: Chapters 1 to 3 (weight = 40%) Unit 2: Chapters 4 to 6 (weight = 40%) Unit 3: Project (weight = 20%)

ivLearning Guide – Digital Control Systems IV

i) Module assessment: To successfully complete each unit, students must receive a unit mark of at least 50%. To successfully complete the module, students must complete all the units. A student that successfully completes the module will receive a module mark according to the following summative assessment schedule:

Module% = 0.4Unit1% + 0.4unit2% + 0.2unit3%

The continuous assessment programme does not allow for supplementary or rewritten examinations. Students that fail to complete this module, must resume their studies by completing all units again during a subsequent semester.

ii) Unit 1 assessment (1½ hour session): Assessment of unit 1 is scheduled for

Thursday 24 August 2017 at 10h00. Students that fail to receive 50% for unit 1, will be offered a second and final opportunity to complete unit 1 on Thursday 26 October 2017 at 10h00. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 1. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 1. A student that fails to receive 50% for the final attempt to complete unit 1, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus.

iii) Unit 2 assessment (1½ hour session): Assessment of unit 2 is scheduled for Thursday 21 September 2017 at 10h00. Students that fail to receive 50% for unit 2, will be offered a second and final opportunity to complete unit 2 on Thursday 26 October 2017 at 11h35. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 2. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 2. A student that fails to receive 50% for the final attempt to complete unit 2, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus.

iv) Unit 3 assessment: For the purpose of assessing unit 3 (project), each student will prepare and demonstrate a hardware simulation of a water level control system, constructed according to the guidelines given in the learning guide for unit 3. A clear photograph showing the project with the student’s student card (or other clear identification), must also be available for assessment and moderation. Unit 3 will be assessed in the lecture room, on the date and time scheduled by the lecturer. Students that fail to receive 50% for unit 3, will be offered a second and final opportunity to complete unit 3 on the date and time scheduled by the lecturer. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 3. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 3. A student that fails to receive 50% for the final attempt to complete unit 3, fails the module.

vLearning Guide – Digital Control Systems IV

v) Module Portfolio: Students will not be required to assemble a module portfolio individually. The lecturer, however, will assemble a module portfolio that will include all question papers and memoranda, as well as the study guide, mark sheets and class registers. The examination office currently archives all examination scripts in order to be available as assessment evidence for unit 1 and unit 2. Lecturers should include each student’s project photograph in the module portfolio as assessment evidence for unit 3. The module portfolio must be safeguarded for at least three years for moderation purposes.

7. ICONS USED IN THIS STUDY GUIDE

1

2

3

4

5

6

Estimated study time

Opening remarks and introduction

Outcomes Study the following passage thoroughly

Practical work

Exam questions and assessment

7.

Section still under construction

1-1EIDBS4 Sampled Data Systems Learning Guide Unit 1

1. LEARNING GUIDE - UNIT 1: SAMPLED DATA SYSTEMS

The objective of this learning unit is to introduce students to the fundamental properties of sampled data systems.

You should spend approximately 15 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:

Describe the basic elements of a digital control system and the fundamental process of sampling a continuous signal.

Express the input output relationship of digital systems in terms of difference equations.

Define the impulse function and step function. Determine the z transform of important time functions. Use z transform techniques to solve difference equations.

2-1EIDBS4 Transfer Functions Learning Guide Unit 1

2. LEARNING GUIDE – UNIT 1: TRANSFER FUNCTIONS

The objective of this learning unit is to introduce students to the methods used to determine the transfer function of single input, single output discrete control systems.




Visualise the sampling process to be composed of an ideal sampling action followed by a hold action.

Determine the transfer function of discrete cascaded systems and feedback systems.

Obtain the transfer function of a plant preceded by a zero order hold device.

3-1EIDBS4 Time Domain Analysis Learning Guide Unit 1

3. LEARNING GUIDE – UNIT 1: TIME DOMAIN ANALYSIS

The objective of this learning unit is to introduce students to the methods used to analyse the transient response of digital control systems.




Analyse the transient behaviour of a prototype second order continuous system.

Map between values in the s plane and the z plane. Judge the response of discrete systems by relating the essential

discrete characteristics to the properties of a similar and more familiar continuous system.

View the transient response of discrete systems in terms of the position of the roots of the characteristic equation in the z plane.

Determine the steady state behaviour of digital control systems.

4-1EIDBS4 Stability Analysis Learning Guide Unit 2

4. LEARNING GUIDE – UNIT 2: STABILITY ANALYSIS

The objective of this learning unit is to introduce students to the methods used to establish the stability properties of digital control systems.




Use the Jury test to judge the stability of discrete control systems. Prescribe the set of conditions that will guarantee stable operation

of a digital control system.

5-1EIDBS4 Root Locus Techniques Learning Guide Unit 2

5. LEARNING GUIDE – UNIT 2: ROOT LOCUS TECHNIQUES

The objective of this learning unit is to introduce students to the analysis of discrete control systems by means of root locus techniques. You should spend approximately 15 hours on this learning unit.



Construct the root locus from the characteristic equation of a system.

Analyse transient and stability behaviour of systems by means of the root locus.

6-1EIDBS4 Digital Controller Design Learning Guide Unit 2

6. LEARNING GUIDE – UNIT 2: DIGITAL CONTROLLER DESIGN

The objective of this learning unit is to introduce students to some of the techniques used to design digital controllers. You should spend approximately 15 hours on this learning unit.



Improve system response with controller design based on root locus methods.

Determine digital forms of the PID control algorithm. Realize PID controllers.

7-1EIDBS4 Project Learning Guide Unit 3

7. LEARNING GUIDE – UNIT 3: PROJECT – LEVEL CONTROL

The objective of this learning unit is to give students the opportunity to study the operation of a digital proportional and integral controller. A water level control system will be electronically simulated.


7.1 Project Outcome

After completion of this project, students will appreciate some of the properties of the important PI control algorithm, implemented in a digital control environment.

7.2 Project Schedule

To complete this project, students will be required to construct a circuit representing a water level control system. A block diagram of the system is shown in Figure P1.

Setpoint (tank 50% or half full)

Controller output

Control valve

Measured value of

water level (float position)

Controlled variable (water level)

Manipulated variable (water inflow)

PI control algorithm

Disturbance variable (water outflow)

Water supply

Figure P1


The system must monitor the water level in the container, and use a proportional and integral control strategy, to regulate the water inflow into the container; with the aim to keep the water level in the tank as close as possible to the set point value (we will assume a value of 50% for this model). The water level (or measured value) is presented to the PI controller which calculates an appropriate value for the valve position of the control valve (water inflow). This value will be sampled and transmitted to the control valve, which then will adjust the water inflow accordingly. The water inflow will then remain constant until the start of the next sampling period.

7.2.1 Container, water level and inlet An elegant way to represent the water tank, water inflow and water outflow, is with a capacitor and parallel resistor, fed by a current source, as shown in Figure P2. The water level is represented by the voltage v, across the capacitor, the water outflow by the current iL (which is proportional to the voltage across the capacitor), and the inflow by the current i0, injected into the parallel combination. The current i0, is supplied by a voltage controlled current source which is controlled by a voltage u that represents the control valve pneumatic signal.

Using a 1000 F capacitor and maximum source current of 200 A, a real world situation is simulated, where it takes in the order of one minute to fill up the tank. Changing the water outflow will be simulated by varying the value of the resistor in parallel with the capacitor.

Many ways exist to implement a voltage controlled current source, but the circuit in Figure P3, built around a LM358 operational amplifier, was found to perform rather well. The source current, i0, will vary linearly between 0 and 200 A (approx), with the control voltage, u, varying between 0 and 8/9 volt. In order to change the simulated water outflow iL, two 47k resistors are provided. To increase the water outflow, the bottom 47k resistor may be short circuited.

Pneumatic signalto control valve

(represented by u)

Current source

i0

v

iL

Water level (represented by v)

Water inflow (represented by i0)

Water outflow (represented by iL) Figure P2

u


The maximum simulated water outflow with only one 47k across the capacitor (assuming a maximum voltage of 8V across the capacitor) will therefore be 170A. This means that the maximum simulated water inflow will always be able to counterbalance the maximum simulated water outflow. We should therefore in principle, retain control of the voltage level, under all circumstances.

Note: The current source (valve) and inflow current i0 (water inflow) and 1000 F capacitor (container) work just like a simple water tap filling up a bucket with a big hole (47k + 47 k resistors) in it. If u = 0 V (tap closed) the water level (v) will start to drop to 0 and if u = 9 V (tap fully open) the bucket will begin to fill up (v will begin to rise to 8/9 V). For the benefit of interested students, an analysis of the current source circuit is given in Appendix A1.

In order to measure the capacitor voltage without disturbing the charging and discharging process, the second operational amplifier in the LM358 package is used to buffer the capacitor voltage, as shown in Figure P3. The output of this amplifier is the measured value MV of the controlled variable and can be confidently measured at this point with any voltmeter.

MV

Volt- meter

0-10V

1000F (64 volt)

v

9V battery

+

½LM358

5

7

6 4

8

10 M

1

2

3 8

4

390 k

+ 47k

i0

iL ½LM358

10 M

390 k

1.5 k

u

Current source Parallel RC circuit Measured value sensor

The voltage controlled current source (i0), represents the flow control valve in Figure P1

The capacitor represents the water tank and the current iL through the two 47k resistors, represents the water outflow in Figure P1. 4 3 2 1

5 6 7 8 LM358

Top view

Figure P3

47k


This section of the simulation forms a unit, and students are encouraged to build and test this section first, before proceeding with the proportional and integral control section. The value of ‘u’ may be varied by connecting ‘u’ to the battery + rail (fill up the tank) and by connecting ‘u’ to the battery – rail (drain the tank), as shown in Figure P4. A small 9 volt battery will be an adequate power source for the circuit.

If the bottom 47k resistor is short circuited while the capacitor voltage is increasing, the rate at which the capacitor voltage rises, will be slowed down a little bit and this may be verified by careful observation of the voltmeter reading. Similarly, when the capacitor voltage is going down (that is when u = 0), the rate at which the voltage diminishes, may be accelerated by short circuiting the bottom 47k resistor. (This of course corresponds to the behaviour of the water level in a container when the outflow is increased while filling it up or when the water outflow is increased when draining the vessel.) Students that successfully complete this section of the project, demonstrating that they can control the charging and discharging of the capacitor by switching the control voltage (u) between plus and negative supply, will receive a minimum mark of 50% for unit 3.

7.2.2 A proportional and integral controller For the sake of simplicity, we will not use a digital computer to calculate the appropriate proportional and integral control action, but rather an analog computer. This analog device is depicted in Figure P5. The aim with this part of the project is to establish a continuous control system and when finished, we will progress to the third and final part of this project, when we will convert the system into a discrete system by sampling the controller output.

9V

Currentsource

i0

v

Figure P4

u

0-10V

+ 5

7

6 4

8 MV

u = 9V and i0 200 A MV should rise to approx. 8V

u = 0V and i0 = 0A MV should fall to 0V

47k

47k 1000F


Referring to Figure P5, the set point value, SP, is fixed and obtained as the mid point voltage between two 10 k resistors that serve as a voltage divider. This will fix the set point to half the battery voltage. The set point or desired value will therefore correspond to a container that is half or 50% full. In terms of our model, this will mean that the controller will try to drive the capacitor voltage to half the battery voltage or 50% of the maximum voltage that could develop across the capacitor.

The circuit in Figure P5 will calculate the difference between the capacitor voltage at any moment (MV) and the desired value (SP). This will produce the error value e=MV-SP. From this, the proper proportional and integral control action, u, will then be computed. (Quite amazing for one op-amp, one capacitor and two resistors – credit also to Dr. H van Rensburg for suggesting this circuit. An analysis of the controller is given in Appendix A2.)

This section can be tested in conjunction with the first section (the same battery is used for both sections). The controller output, u, should be connected to the input of the current source, while the feedback loop is closed, by feeding back the measured value, MV, to the controller. The measured value, will now be forced to follow the set point value, according to the proportional/integral control law, established by the controller. For clarity, a block diagram showing the connection of the controller to the system, is shown in Figure P6.

The behaviour of the measured value MV, when a load change (or disturbance) occurs, may be studied by putting a short circuit across the bottom 47 k resistor in Figure P3, causing an increase in the simulated water outflow from the container.

100 k (R1) MV

10 F (C) 100 k (R2)

2

3

1

4

8

10 k

SP

10 k

Figure P5

u ½LM358

9V battery

+


It is very interesting also to monitor the control voltage u, to observe the controller behaviour in its effort to keep the level close to set point, when the outflow is changed. It is safe to measure the voltage u at the output of the PI controller op-amp output in Figure P5, without disturbing the system operation. As given in Figure P5, the controller will produce a proportional gain setting of KP = R2/R1 = 1 and the integral gain setting is KI = 1/R1C = 1. Students should experiment with these values (C may be electrolytic).

Students that successfully complete the basic continuous control system, depicted in Figure P6, and demonstrate that the measured value (MV) will be driven to set point after switch on and revert back to set point after a disturbance (short circuiting one 47k resistor), will receive a minimum mark of 60% for unit 3.

7.2.3 Sample and hold Again, to keep the system as simple as possible, only the controller signal (u) will be sampled. A 555 timer will be used to supply the master clock that drives a CD4022 ring counter to provide a short high going pulse to activate one of the analog switches in a CD4066 that together with a RC circuit and op-amp, will provide the sample and hold function for the controller signal. This arrangement is shown in Figure P7.

The sampling clock is provided on pin 2 of the CD4022 counter. The operation of the 555 master clock and CD4022 ring counter may be verified by connecting a LED test probe at this point. The LED should produce a short flash every second. This clock pulse will enable (pin 6) the third switch available on the CD4066. The controller signal (u) is now connected to pin 8 of the CD4066 and the sampled value will appear on pin 7. The sampled value is stored for the duration of the sampling period via a 1 k resistor on a 10 F capacitor connected to one amplifier on a LM358 package. The sampled version of u, u*, is available at the output of this amplifier and it may also be safely monitored with a voltmeter at this point. Some additional design information for the 555 timer is given in Section 7.2.6 and the pin out configuration for the CD4022 and CD4066 is given in section 7.2.5.

A block diagram of the complete system is given in Figure P8. The complete system may derive its power from the same 9V battery. The total current consumption of the prototype system was measured and found to be in the neighbourhood of 7 mA.

MV MV u Water level controlsystem (Figure P3)

PI controller (Figure P5)

Figure P6

9V

+


Before the signal u* is used to control the current source, it may be a good idea to still operate the system in continuous mode and just connect the continuous output u from the PI controller, to the input of the sampler and confirm, by monitoring the signal u* with a voltmeter, that a discrete version of the continuous signal u, is obtained. When satisfied that the sampler is working, the signal u* may replace u to control the current source in a discrete fashion.

MV u*

u*MV MV u Water level control system (Figure P3)

PI controller (Figure P5)

Figure P8

9V

+

Sample & hold(Figure P7)

u

u*

T0.125s

LED

1 k

10 k

6

7

5

4

8

½LM358

9V battery

+

10F

1 k

+

10F

4 3 2 1

5 6 7 8

555

1 k

+

Figure P7

inhibit reset

clock

9

8 7 6 5 4 3 2 1

13 14 1516

CD4022

101112 9 8

7 6 5 4 3 2 1

1314

CD4066

101112

T1s

u


A model and transfer function will be developed for this system in the future. Students may however experiment with the PI controller. It was found with the prototype that when C in Figure P5 was changed to 1 F, the system was still stable in continuous mode but unstable in digital mode. The sample period was chosen to be approximately 1 second. Changing the sampling period, is easily accomplished by changing the RC timing components of the 555 timer. For example, changing RA (see Figure A3 and P7) from 1 k to 100k, changes the sampling period to approximately 7 seconds. The prototype definitely displayed instability with this sampling period.

Students that successfully complete the project including the sampling of the controller signal will be awarded a minimum mark of 70% for unit 3.

7.2.4 Practical note The LM385 package contains two operational amplifiers, with pin out configuration as shown in Figure P9. If it is suspected that the LM385 operational amplifier is faulty, a simple technique to check whether both amplifiers are working is to connect each one in voltage follower mode, shown in Figure P9. If the non-inverting input is connected to the positive supply (+9V), the output should be high (8V) while if connected to the negative rail, the output should be zero volt. If the non-inverting input is left open, the output should be high.

7.2.5 Pin out details for CD4022 and CD4066

3, 5

2, 6

+ 4 3 2 1

5 6 7 8

LM358

Top view

1, 7

8

4

9 V

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

4022

CP1

CP0

CP2

CP5

CP6

NC

CP3

GND

Vcc

Reset

Clock

Inhibit

Carry out

CP4

CP7

NC

1

2

3

4

5

6

7 8

9

10

11

12

13

14

4066

1X

1Y

2Y

2X

S2 Enable

Vcc

S1 Enable

S4 Enable

4X

4Y

3Y

3X

S3 Enable

GND

Figure P9


7.2.6 Additional information on 555 timer Figure P10, shows the 555 timer connected as an astable multivibrator. The low period is given by: TL = 0.7RBC The high period is given by: TH = 0.7(RA + RB)C The total period, is given by: T = 0.7(RA + 2RB)C

7.2.7 Parts list 1×555 (timer) 2×LM358 (dual operational amplifier) 1×CD4022 (8 bit counter) 1×CD4066 (quad switch) 3×1 k (¼ watt resistor) 1×1.5 k (¼ watt resistor) 3×10 k (¼ watt resistor) 2×47 k (¼ watt resistor) 2×100 k (¼ watt resistor) 2×390 k (¼ watt resistor) 2×10 M (¼ watt resistor) 2× 10 F ( 64 V electrolytic capacitor) 110 F ( 64 V non-electrolytic capacitor) 1×1000 F ( 64 V electrolytic capacitor) 1×LED (red)

+

C

4 3 2 1

5 6 7 8

555

RA

RB

Output +

TL TH

T

time Output

Figure P10


7.3 Assessment Schedule Students will prepare this project and demonstrate their work in class on the scheduled date and time. A very clear photograph (A4 computer printout is preferred), showing the project together with the student’s student card (or other clear identification), will also be prepared as part of the demonstration and assessment. A student that demonstrates a

control system in which the controlled variable manages to stay close to set point if disturbed, will meet the required outcome for this unit, and will receive at least 50% for unit 3.

Please note: 1. A project submitted without accompanying photo, will NOT be assessed, and a

photograph displayed on a camera or cell phone or sent via email, will not be acceptable, as a hard copy is needed for final assessment and moderation of the project. A well defined photo printed on a color printer (A4), is preferred.

2. Students that demonstrate a system crudely constructed on a medium such as breadboard, with only the simulation of the container and valve operating correctly, will receive 50 %. If, in addition, a functioning continuous PI control system is demonstrated, 10% will be added. If, in addition, a functioning digital control system is demonstrated, 10% will be added. If, in addition, special attention is given to the construction (for example the circuit is assembled on veroboard), 5% will be added. Additional marks may be awarded according to the judgment and discretion of the assessor. Construction on PC boards will not be allowed.

3. Students that will demonstrate a partial system, must state beforehand which part or parts they are demonstrating so as to facilitate in proper assessing of the project.

7.4 APPENDIX

A1. Analysis of current source circuit Refer to the circuit in Figure A1 At node N1: (u – v’)/R = (v’ – v0)/R1 Riu – R1v’ = Rv’ – Rv0 Rv’ + R1v’ = Rv0 + R1u v’ = (Rv0 + R1u)/(R + R1) ………...…….(1)

And at node N2: (v” – v’)/R1 = v’/R Rv” – Rv’ = R1v’ Rv” = Rv’ + R1v’ v” = [(R + R1)/R]v’ And using v’ from (1): v” = [(R + R1)/R][(Rv0 + R1u)/(R + R1)]

v” = (Rv0 + R1u)/R ……………..……….(2)

u

R1

N3

N2

N1

v’R

R

R1

R0

i0

v”

vo

Figure A1


Finally at node N3: (v’ – v0)/R1 = i0 + (v0 – v”)/R0 R0v’ – R0v0 = R0R1i0 + R1v0 – R1v” R0R1i0 = R0v’ + R1v” – (R0 + R1)v0 Using now v” and v’ from (1) and (2): R0R1i0 = R0[(Rv0 + R1u)/(R + R1)] + R1[(Rv0 + R1u)/R] – (R0 + R1)v0 R0R1i0 = [R0/(R + R1) + (R1/R)][Rv0 + R1u] – (R0 + R1)v0 Assuming now that R0 << (R + R1) and R0 << R1, then,

R0R1i0 (R1/R)(Rv0 + R1u) – R1v0 R0R1i0 R1v0 + (R12/R)u – R1v0

R0R1i0 (R12/R)u

i0 uR

0R

1R

A2. Analysis of the proportional and integral controller

At node N1 in Figure A2: i = 1RSP-MV …….…..……………………...………… (1)

Also i = Cdt

cdv ………………………………………...…………....…………… (2)

From (1) and (2): dt

cdv =

C1RSP-MV ……………………………………………… (3)

For loop N1N2 in Figure A2, by KVL: SP – iR2 – vc – u = 0

SP – 1R2R

(MV – SP) – vc – u = 0; from (1)

vc = SP – 1R2R

(MV – SP) – u

dt

cdv =

dtd (SP) –

1R2R

dtd (MV – SP) –

dtdu

= 0 – 1R2R

dtd (MV – SP) –

dtdu ; because SP = constant

N2

i

vc

SP

SP

N1

SP Figure A2

MV

C R2

u

R1 i

iR2

SP

vC

u


dt

cdv = –

1R2R

dtd (MV – SP) –

dtdu ……………………………………….... (4)

From (3) and (4): C1RSP-MV =

1R2R

dtd (MV – SP) –

dtdu

dtdu = –

1R2R

dtd (MV – SP) –

C1RSP-MV =

1R2R

dtd (SP – MV) +

C1R1 (SP – MV)

We now recognise that the difference between the set point SP and the measured value MV, is in fact the error signal e = SP – MV

dtdu =

1R2R

dtde +

C1R1 e

dtdtdu = dt

dtde

1R2R

+ edtC1R

1 du = de1R2R

+ edtC1R

1

u = 1R2R

e + edtC1R

1 ………………………………………..………….. (5)

Therefore from (5) and with KP = 1R2R

and KI = C1R

1 :

u = KPe + KIedt ……………………………………………………….….. (6)

We conclude therefore from Equation (6) that the circuit in Figure P3, provides a

PI control law with a proportional gain KP = 1R2R

and an integral gain KI = C1R

1 .

Documents

DIGITAL CONTROL SYSTEMS IV - MWEBhome.mweb.co.za/rf/rfitch/eidbs4/DbsStGds.pdf · DIGITAL CONTROL SYSTEMS IV ... Nagle H.T., Digital Control System Analysis and Design. c) Kuo,