Digital Electronics & Logic Design ( 214443)

Unit I –

Logic Families

2. TTL & CMOS Logic families

Switching Element

Digital Circuit are in the Integrated Circuit (IC) form. element used for building such circuit are diodes,resistors,tranisitors and MOSFET.

diodes,resistors,tranisitors and MOSFET are used as switches, so they are known as switching element.

Prepared by K.T. NG 2

3

Logic Families

The types of digital circuit devices are classified in families that based on the specific circuit technology. Among them, the most important are TTL and CMOS TTL (Transistor-Transistor Logic), made of bipolar transistors

It is called transistor–transistor logic because the logic function (e.g., AND) and amplification is performed by transistors

CMOS (Complementary Metal Oxide Semiconductor) made from MOSFET transistors In the modern world, CMOS is the dominate technology used to

construct digital circuit components, especially large-scale integrated circuits

The logic families differ from each other primarily in output current capability, power dissipation, propagation delay time, and operating power supply voltage

Digital Logic Families

RTL: Resistor-Transistor Logic

DTL: Diode-Transistor Logic

TTL: Transistor-Transistor Logic

ECL: Emitter-coupled Logic

MOS: Metal-Oxide Semiconductor

CMOS: Complementary MOS

Low power dissipation, currently the MOST DOMINANT

BiCMOS: Bipolar CMOS

CMOS and TTL for additional current/speed

GaAs: Gallium-Arsenide

earliest, now obsolete

high-speed operation

widely used

compact

very high-speed operation

5

Characteristics of an Ideal Logic Family

The ideal logic family should have or be:

Low power

High speed

Easy to use

Many different logic functions

Clear voltage levels for 0 (LOW) and 1 (HIGH)

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The Bipolar Junction Transistor (BJT)

The bipolar junction transistor (BJT) is the active switching element used in all TTL circuit

The 3 terminals for a BJT are the collector, base, and emitter

BJT has 2 junctions: the base-emitter and the base-collector

The symbol for an npn BJT

7

The Ideal Switching Action of the BJT Consider a bipolar transistor in logic circuits

It is operated in either two states produces the two logic levels

Fully conducting state / saturated/turned onor

Fully non-conducting state / cut-off state

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Transistor-Transistor Logic(TTL)

In Transistor-Transistor logic or just TTL, logic gates are built only around transistors

TTL was developed in 1965 Through the years basic TTL has been improved to meet

performance requirements. There are many versions or families of TTL. For example Standard TTL High Speed TTL (twice as fast, twice as much power) Low Power TTL (1/10 the speed, 1/10 the power of “standard" TTL) Schhottky TTL etc. (for high-frequency uses )

Here we will discuss only basic TTL. Typically, all TTL logic families have three configurations for outputs Totem pole output Open collector output Tristate output

9

Part Numbers

Part numbers for 7400 TTL series logic devices often use the following naming convention

SN 74 ALS 245 A

manufacturer temperature range logic subfamily device

LS - Low Power Schottky

AS - Advanced Schottky

ALS - Advanced Low

Power Schottky

SN = Texas Instruments

DM = Fairchild

74 - commercial

54 – military (extended)

hundreds of different

devices in each family

package type, quality

grade, etc. (varies

widely by manufacturer)

IC Characteristics

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Properties of Digital ICs

When you work with digital IC's, you should be familiar, not only with their logical operation, but also with such operational properties as

Voltage & Current levels

Noise immunity

Power dissipation

Fan-in, and fan-out

Propagation delays

12

Supply Voltage Designations

The supply voltages for various families have names which are based on the type of transistors used in their construction:

TTL gates are made with bipolar transistors, which have a collector and an emitter, so the supply voltages are VCC and GROUND is occasionally given as VEE

CMOS gates are built with field-effect transistors which have a drain and a source, so the supply voltages are VDD and VSS

13

Voltage Limits

While the ideal voltage in TTL circuits are 0 (logic 0) and +5 volts (logic 1), the typical, or observed, voltages are different in practice

It is important to know what tolerances must be observed in order to guarantee the correct operation of a digital circuit

Four particular quantities are of interest in specifying the tolerance:1.2.3.4.

minIHV

maxILV

minOHV

maxOLV

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Voltage Limits (Cont.)

VIHmin: The minimum input voltage which will be accepted as a logic 1

VILmax: The maximum input voltage which will be accepted as a logic 0

VOHmin: The minimum output voltage representing a logic 1 state

VOLmax: The maximum output voltage representing a logic 0 state

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Voltage Limits (Cont.) For the 3 logic families listed as an example, the specified values of

these parameters are given in the following table

In other words, real gates should perform at least as well as the values listed

Note: For CMOS logic VDD can be as low as 3.5 V and as high as 15 V

What the above information means is that, (for instance), if input to a 74LS04 NOT gate is at greater than or equal to 2.0 volts, it will be considered "high", and so the output should be "low", i.e. at a voltage less than or equal to 0.5 volts

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Voltage Limits (Cont.) For each logic family, you should notice that the output voltage

limits are more strict than the input voltage limits

This is to provide noise immunity to the devices

Values outside the given range are not allowed – indeterminate region

VOL(max) is lower than VIL(max) to allow for noise and signal deterioration. Similarly VOH(min) is higher than VIH(min)

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Noise Immunity

Noise is the unwanted voltage that might add to the output of one gate. This may cause the voltage at the input to a logic circuit to drop below VIH or rise above VIL into the indeterminate or “illegal” region to produce undesired operation

In order not to be adversely affected by noise, a logic circuit must have the ability to tolerate noise signals which is referred to as the noise immunity

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Noise Margin

A measure of a circuit’s noise immunity is called the noise margin, which is expressed in volts

There are 2 values of noise margin specified for a given logic circuit: the HIGH level noise margin (VNH) and the LOW level noise margin (VNL)

These parameters are defined by the following equations:

VNH = HIGH level noise margin = VOH(min) – VIH(min)VNL = LOW level noise margin = VIL(max) – VOL(max)

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Comparing TTL and CMOS Noise Margins

The noise margin is much better for the CMOS than for the TTL family

You may introduce almost 1.5 V of unwanted noise into the CMOS input before getting unpredictable results

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Worked Example

Given the following parameters, calculate the noise margin of 74LS series

Solution:

High Level Noise Margin, VNH = VOH(min) - VIH(min) = 2.7 V - 2.0 V = 0.7 V

Low Level Noise Margin, VNL = VIL(max) - VOL(max) = 0.8 V - 0.4 V = 0.4 V

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Current Limits

Similar to that of voltage limits, there are limits to the input and output currents of each individual gate. Four particular quantities are of interest in specifying the tolerance:

1.

2.

3.

4.

maxIHI

maxILI

maxOHI

maxOLI

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Current Limits (Cont.)

IIHmax: The maximum input current which must be supplied to a gate's input to guarantee the input will be high

IILmax: The maximum input current which must be drawn from a gate's input to ground to guarantee the input will be low

IOHmax: The maximum current which the gate can source through its output and still keep the output high

IOLmax: The maximum current which the gate can sink through its output and still keep the output low

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Current Direction

According to IEEE standards, currents are directed into devices. Therefore, If a current in a specification is positive, it is

entering the device

If a current in a specification is negative, it is leaving the device

The –ve sign means current direction is leaving the device rather than actual value

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Current-Sourcing and Current-Sinking Action

Current Sourcing It is the amount of current that

the driving gate produces as outgoing current that flow into the load gate

Current Sinking It is the amount of incoming

current that the driving gate receives from the loaded gate

Most of the TTL can sink up to 16 mA and source 250 A

Current sinking and sourcing rates are important while designing circuits. These ratings determine the current capacity to drive external devices

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Fan-in

Number of input signals to a gate

Not an electrical property

Function of the manufacturing process

NAND gate with a

Fan-in of 8

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Loading and Fan-Out

When the output of a logic gate is connected to one or more inputs of the other gates, a load on the driving gate is created

As more load gates are connected to the driving gate, the loading on the driving gate increases

There is a limit to the number of load gate inputs that a given gate can drive. The limit is called fan-out of the gate

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Fan-Out A measure of the ability of the output of one gate to drive the

input(s) of subsequent gates

Usually specified as standard loads within a single family

e.g., An input to an inverter in the same family

For TTL devices, the number of standard loads is limited by the amount of input current each load requires as compared to the current that the driving gate can deliver. It is generally considered to be the smaller of the following two items:

May have to compute based on current drive requirements when mixing families

Although mixing families is not usually recommended

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Fan-Out (Cont.)

An illustration of fan-out and the associated source and sink currents

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Worked Example How many 74ALS00 NAND gate inputs can be driven by a

74ALS00 NAND gate outputs ?

Solution:Refer to data sheet of 74ALS00, the maximum values of

IOH = 0.4 mA, IOL = 8 mA, IIH = 20 A, and IIL = 0.1 mA

Hence, Fan-out (high) = IOH(max) / IIH (max) = 0.4 mA/20 A= 400 A/20 A = 20

Fan-out (low) = IOL(max) / IIL(max) = 8 mA/0.1 mA = 80,The overall fan-out = fan-out (high) or fan-out (low) whichever is lowerHence, overall fan-out = 20Note: If the fan-out has a fractional part, it should be dropped. In other words, you should always round down when calculating fan-out

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Another Example A unit load for some particular logic family is as follows:

1 UL = 50 A HIGH state

= 1 mA LOW state

Determine the fan-in and fan-out for a gate in this family that has the following parameters:

IOH = 400 A

IOL = 10mA

IIH = 150 A

IIL = 4 mA

Solution: Fan-in = 150/50 = 3 UL or 4/1 = 4 UL

Therefore fan-in = 3 or 3 UL

Fan-out = 400/50 = 8 UL or 10/1 = 10 UL

Therefore fan-out = 8 or 8 UL

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Fan-out for CMOS Devices

It is worth noting that fan-out is much higher for CMOS devices than for TTL devices IIL and IIH are extremely small for CMOS devices

(< 1 A)

Calculating fan-out as we did for TTL devices might yield a fan-out of 4000 for CMOS, compared to 10 for standard TTL

However, the input capacitance of CMOS gates affects propagation delay, so increased fan-out results in increased delay

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Timing Limits

Ideally changes to the inputs of a gate would be reflected at the output immediately, but in reality there is a slight delay

In general, the delay may be different depending on whether the gate's output is going from low to high or from high to low

Furthermore, the transitions themselves are not instantaneous, so they are defined as being at the 50% point of the voltage transitions

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Propagation Delay

Propagation delay is the time that it takes a gate to switch logic levels. Logic gates often have a different propagation delay switching from LOW to HIGH than from HIGH to LOW, so two types of delay are defined:

tPLH = Propagation delay when the OUTPUT switches from LOW to HIGH

tPHL = Propagation delay when the OUTPUT switches from HIGH to LOW The ‘lh’ (low to high) and the ‘hl’ (high to low) part refer to

OUTPUT change, NOT input change

Propagation delay: )(2

1PLHPHLp ttt +=

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Propagation Delay (Cont.)

The propagation delay of a gate limits the frequency at which it can be operated

The greater the propagation delay, the lower the maximum frequency

Thus, a higher speed circuit is one that has a smaller propagation delay

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Power Dissipation

Generally, as propagation delays decrease (increased speed), the power consumption and related heat generation increase

A logic gate draws current from the DC Supply voltage source

When the gate is in the HIGH output state, an amount of current designated by ICCH is drawn

In the LOW output state, a different amount of current, ICCL is drawn

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Power Dissipation (Cont.)

When a gate is pulsed, its output switches back and forth between HIGH and LOW and the amount of supply current varies between ICCH and ICCL

The average power dissipation depends on the duty cycle and is usually specified for a duty cycle of 50%

When the duty cycle is 50%, the output is HIGH half the time and LOW the other half

The average supply current, ICC, is therefore

ICC = (ICCH + ICCL)/2

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Power Dissipation (Cont.)

To determine the Average Power Dissipation PD of a gate the following equation is used:

PD = VCCICC = VCC × (ICCH + ICCL)/2

Power Dissipation in a TTL circuit is essentially constant over its range of operating frequencies

Power Dissipation in CMOS, however, is frequency dependent

It’s extremely low under (dc) conditions and increases as the frequency increases

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Example

A certain gate draws 2 mA when its output is HIGH and 3.6 mA when its output is LOW. What is its average power dissipation if VCC is 5 V and the gate is operated on a 50% duty cycle

Solution:

ICC = (ICCH + ICCL)/2 = (2 mA + 3.6 mA)/2 = 2.8 mA

PD = VCC × ICC = 5 V * 2.8 mA = 14 mW

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Speed Power Product

The Speed Power Product provides a basis for the comparison of logic circuits when both propagation delay and power dissipation are important considerations in the selection of the type of logic to be used in a certain application

The lower the speed power product, the better

The unit of speed power product is the pico-joule (pJ)

For example, an IC has An average propagation delay of 10 ns An average power dissipation of 5 mW The speed-power product = (10 ns) x (5 mW)

= 50 pJ Example: HCMOS has a speed power product of 1.2pJ at

100KHz while the LS TTL is 22pJ

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Interfacing Logic Families

To achieve optimum performance in a digital system, devices from more than one logic family can be used, taking advantages of the superior characteristics and function availability of each family for different parts of the system

When interfacing logic families, several considerations must be made The output voltage level of one family must be high and low

enough to meet the input requirements of the receiving family

Also, the output current capability of the driving gate (IOL, IOH) must be high enough for the input draw of the receiving gate or gates (IIL, IIH)

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Interfacing Logic Families (Cont.)

For such an arrangement to operate properly the following conditions are required to be satisfied:

1. VOH (Driving) VIH (Load)

2. VOL (Driving) VIL (Load)

3. –IOH (Driving) N × IIH (Load)

4. IOL (Driving) –N × IIL (Load)

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Example

Find the number of low power 74-series TTL gates which can be driven from a 74 C-series CMOS gate. Given the specification are as follows:

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Example (Cont.)

Solution: Since condition 1 & 2 are satisfied

VOH (Driving) VIH (Load)

VOH (CMOS) = 4.5 V VIH (TTL) = 2.0 V

VOL (Driving) VIL (Load)

VOL (CMOS) = 0.5 V VIL (TTL) = 0.7 V

–IOH (Driving) N × IIH (Load)

–IOH (CMOS) = 100 A N × IIH (TTL) = N × 10 A

N = 10

IOL (Driving) –N × IIL (Load)

IOL (CMOS) = 360 A –N × IIL (TTL) = N × 180 A

N = 2. Therefore, a 74 C-series CMOS gate can drive only

two 74-series low power TTL gates

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Data Sheets

Different manufacturers prepare data sheets slightly differently, but the same types of information are found in all of them. In some form, most data sheets should contain the following information:

Description

What the device is

Features

How this device differs from other similar ones, by this manufacturer or others

Pin Configuration

How electrical connections are made to the chip

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Data Sheet (Cont.) Internal Schematic

Functionally, how the inside appears (Physical appearance may be nothing like it)

Absolute Maximum Ratings Limits of conditions under which the device can survive. (It

may only function correctly over a much smaller range of conditions)

Recommended Operating Conditions Limits of conditions under which the device can function

correctly

Electrical Characteristics Parameters for use when the chip is operating within normal

limits

Sample Circuits Examples of how the device might be hooked up in a circuit.

Extremely useful

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Totem Pole Output

Below is the circuit of a totem-pole NAND gate, which has got three stages

Input Stage

Phase Splitter Stage

Output Stage

Standard TTL NAND gate

Totem pole output stage

phase splitter stage

multiple emitter input stage

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Totem Pole Output (Cont.)

Transistor Q1 is a two-emitter NPN transistor, which is equivalent to two NPN transistors with their base and emitter terminals tied together. The two emitters are the two inputs of the NAND gate

In TTL technology multiple emitter transistors are used for the input devices

Diodes D2 and D3 are protection diodes used to limit negative input voltages. When there is large negative voltage at input, the diode conducts and shorting it to the ground

diode equivalent for Q1

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Totem Pole Output (Cont.)

Q2 provides complementary voltages for the output transistors Q3 and Q4

The combination of Q3 and Q4 forms the output circuit often referred to as a totem pole arrangement (Q4 is stacked on top of Q3)

In such an arrangement, either Q3 or Q4 conducts at a time depending upon the logic status of the inputs

Diode D1 ensures that Q4 will turn off when Q2 is on (HIGH input)

The output Y is taken from the top of Q3

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TTL Logic States Analysis

LOW output HIGH output

When a transistor is ON it acts like a closed switch and when a transistor is OFF it acts like an open switch

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Advantages of Totem Pole Output Configuration

The features of this arrangement are

Low power consumption

Fast switching

Low output impedance

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TTL Logic Cascading

52

Unused Inputs on TTL devices Unused inputs on TTL gates behave as though a logic 1 is

connected to them This present a problem with OR or NOR gates With AND or NAND gates, the logic would not pose a problem

but for better noise immunity, the inputs should not be allowed to "float“

It is advisable to connect unused HIGH inputs to +5V through resistors (“pull-up” resistors) of 1k

Unused inputs should be connected as follows

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The Destruction Effect if Totem Pole Outputs are Tied Together If TTL gates with totem-pole outputs have their outputs tied

together, the gates may be destroyed

This is illustrated in below Figure where the LEFT gate has a HIGH output and RIGHT gate has a LOW output

Totem pole outputs tied together can produce harmful current through Q3Aand Q4B

ON

ON

OFF

OFF

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Open Collector Outputs

Figure below shows the circuit of a typical TTL gate with open-collector output

Observe here that the circuit elements associated with Q3 in the totem-pole circuit are missing and the collector of Q4 is left open-circuited, hence the name open-collector

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Open Collector Outputs (Cont.)

An open-collector output can present a logic LO output

Since there is no internal path from the output Y to the supply voltage VCC , the circuit cannot present a logic HIGH on its own

To function properly an external pull-up resistor, Rp is being used as shown

Use this symbol to Indicates open collector output

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Advantages of Open Collector Outputs Why should we use open-collector gates which

require the addition of a pull-up resistor in order to function properly when we could use a gate with a totem-pole output instead?

There are several reasons:1. Wired-ANDing - Open-collector outputs can be tied directly

together which results in the logical ANDing of the outputs. Thus the equivalent of an AND gate can be formed by simply connecting the outputs

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Advantages of Open Collector Outputs (Cont.)

2. Increased current levels - Standard TTL gates with totem-pole outputs can only provide a HIGH current output of 0.4 mA and a LOW current of 1.6 mA. Many open-collector gates have increased current ratings

3. Different voltage levels - A wide variety of output HIGH voltages can be achieved using open-collector gates. This is useful in interfacing different logic families that have different voltage and current level requirements

The big disadvantage of open-collector gates is their slow switching speed. This is because the value of pull-up resistor is in k, which results in a relatively long time constants

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Comparison of Totem Pole and Open Collector Output

The major advantage of using a totem-pole connection is that it offers low-output impedance in both the HIGH and LOW output states

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Tristate (Three-State) Logic Outputs

Tristate output combines the advantages of the totem-pole and open collector circuits

Three output states are HIGH, LOW, and high impedance (Hi-Z)

For the symbol and truth table, IN is the data input, and EN, the additional enable input for control

For EN = 0, regardless of the value on IN (denoted by X), the output value is Hi-Z

For EN = 1, the output value follows the input value

Variations: Data input, IN, can be inverted Control input, EN, can be inverted by

addition of "bubbles" to signals

IN OUT

EN

This requires two inputs: input and enable

EN is to make output Hi-Z

or follow input

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Hi-Impedance Outputs

Tristate gate utilize the high-speed operation of the totem-pole arrangement when input enabled

Permit outputs to be connected together

What is a Hi-Z value?

Both transistor are turned off in the totem-pole arrangement

This means that, looking back into the circuit, the output appears to be disconnected (open circuit)

An equivalent circuit for the tristate output in the high-Z state

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Use of Tri-state Buffers A bus (a collection of wires that serve a common purpose) is

created if several tristate devices are connected together As long as only one is selected at a time, there is no problem

TTL NOR Gate Circuit

B

AX

DC V

NO DATA

+5V

Q6

D1

Q5

Q3Q1

Q2 Q4

R4130

R31.6k

R14k

R24k

R51k

http://www.cs.nccu.edu.tw/~whliao/ds2003/Chapter08/Fg08-10.ckt

Comparison of TTL Series

CMOS Logic Family

Complementary metal oxide semiconductor (CMOS) replaced TTL devices in the 90’s due to advances in the design of MOS circuits made in mid 80’s.

Advantages:

Operate with a wider range of voltages that any other logic family.

Has high noise immunity.

Dissipates very low power at low frequencies.

It requires an extremely low driving current.

High fanout.

Disadvantages:

Power consumption increases with frequency.

Susceptible to ESD - electro-static discharges.

67

CMOS Technology

MOS stands for Metal Oxide Semiconductor Uses FETs

MOS can be classified into three sub-families: PMOS (P-channel)

NMOS (N-channel)

CMOS (Complementary MOS, most common)

The concept of CMOS was introduced in 1963 but become common until the 1980's

CMOS still dominates digital IC design today

68

MOSFET Circuit Symbol

The following simplified symbols are used to represent MOSFET transistors in most CMOS circuit diagrams:

negative voltage

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MOSFET Circuit Symbols (Cont.)

The gate of a MOS transistor controls the flow of the current between the drain and the source

The MOS transistor can be viewed as a simple ON/OFF switch

Transistors in Series/Parallel

nMOS in ParallelnMOS in Series

X

Y

a

b

X:X

Y:Y

a

b

pMOS in Series

X

Y

a

b

X:X’

Y:Y’

a

b

Path between points a and b exists if bothX and Y are 1 X•Y

Path between points a and b exists if bothX and Y are 0 X’•Y’

Path between points a and b exists if eitherX or Y are 1 X+Y

X Y

b

a

X:X Y:Y

b

a

pMOS in Parallel

X Y

b

a

X:X Y:Y

b

a Path between points a and b exists if eitherX or Y are 0 X’+Y’

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CMOS Logic

CMOS gates are built around the technology of the basic CMOS inverter

Transistors come in complementary pairs

Two Transistors are enhancement mode MOSFETs

N-Channel with its source grounded

P-Channel with its source connected to +V

Input: gates connected together

Output: drains connected

outin

Symbol

Vdd

OutIn

PMOS

NMOS

s

s

d

d

g

g

Fully Complementary CMOS NetworksBasic Gates

Fully Complementary CMOSComplex Gates

Given a function F:

1. Find and simplify F’. Make sure complements are down to the literal level.

2. Implement F’ as a nMOS net and connect it to GRD (pull-down net) and F.

3. Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F.

4. Connect switch inputs.

Fully Complementary CMOS NetworksComplex Gates - Example

F = AB’+AC+BC’

CMOS Sub - Families

40xx : Original CMOS family.

Fairly slow, but it has a low power dissipation.

74HCxx : High speed CMOS.

Better current sinking and sourcing than 40xx. It uses voltage supply between 2 and 6 volts.

Higher voltage →higher speed.

Lower voltage →lower power consumption. 74HCTxx : High speed CMOS, TTL compatible.

Better current sinking and sourcing than 40xx. It uses voltage supply of 5V. Compatible with TTL family.

74ACxx : Advanced CMOS.

Very fast. It can source and sink high currents. Not TTL compatible.

74ACTxx : Advanced CMOS, TTL compatible.

Same as 74ACxx, but it is compatible with TTL family.

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Pros and Cons of MOS Digital ICs

The Good:

Simple

Inexpensive to fabricate

Higher integration

Consumes little power

The bad:

Static-electricity damage

Slower than TTL

78

A Comparison of Some Common Logic Families

79

TTL vs. CMOS

TTL is good for

Where you have a good power supply

Where you want high speed

CMOS 4000 is good for

Battery equipment

Where speed is not so important

TTL differences from CMOS

Asymmetric input and output characteristics.

Inputs source significant current in the LOW state, leakage current in the HIGH state.

Output can handle much more current in the LOW state (saturated transistor).

Output can source only limited current in the HIGH state (resistor plus partially-on transistor).

TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS).

IC Interfacing

Connecting the output(s) of one circuit to the input(s) of another circuit that has different electrical characteristics.

Occurs often in complex digital systems, where designers utilize different logic families for different parts of system.

TTL driving CMOS

CMOS driving TTL

TTL driving CMOS

No problem with the current requirements (See Table 8-12)

VOH(min) of TTL is low compared to VIH(min) of some CMOS series (Table 8-9), use pull-up resistor to raise TTL output voltage (Figure 8-46)

TTL driving high-voltage CMOS (VDD of CMOS is greater than 5V) Use 7407 buffer

Use voltage level-translator (such as 4504B)

CMOS driving TTL

HIGH state:Table 8-9 and 8-12 indicate no special consideration the HIGH state.

LOW state: depends on the series used.