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Digital Logic Circuit Types
2
Combinational Circuit
Output depends only on
current inputs
No feedback loops
“memoryless”
Sequential Circuit
Output depends on past
history plus current
inputs
Contains feedback loops
Has memory
Up to this point, we have focused on “combinatorial logic circuits” (i.e. the output of the circuit is dependent on the current input ONLY).
Now we will shift our focus to “sequential logic circuits” (i.e. the output depends not only on the present input but also on the history of the input.
The basic building blocks for sequential logic circuits are “latches” and “flip-flops”
Sequential Logic Circuits
3
Memory is represented in the form of states.
“State” embodies all the information about the past needed to
predict current output based on current input.
State variables are one or more bits of information
representing logic signals in a circuit
Tell you “where the circuit is”
Used in conjunction with inputs to derive current outputs of a
sequential circuit
In combinational circuits, only need to look at the current
inputs to get the current output.
S-R Latch
4
A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type.
It can be constructed from NOR gates or NAND gates.
With two cross-coupled NOR gates, the latch responds to active-HIGH inputs.
With two cross-coupled NAND gates, the latch responds to active-LOW inputs.
S-R Latch
5
There are two versions of SET-RESET (S-R) latches.
S-R Latch (Remember This!)
6
Two inputs
S for set
R for reset
Two useful states (for normal operation)
When output Q = 1 and Q = 0, the latch is said to be in the set
state.
When output Q = 0 and Q = 1, the latch is said to be in the
reset state.
The “Old Q”-“New Q” Analysis
7
R
S
Q
X
new
old
old
Q R X
R Q S
R Q S
Input Output
S R Qnew
0 0 Qold
0 1 0
1 0 1
1 1 0
The “Old Q”-“New Q” Analysis (2)
8
X
QS
R
new
old
old
Q S X
S Q R
S Q R
Input Output
S R Qnew
0 0 1
0 1 1
1 0 0
1 1 Qold
“Old Q”/“New Q” Analysis
9
Input Output
S R Qnew
0 0 Qold
0 1 0
1 0 1
1 1 0
Input Output
S R Qnew
0 0 1
0 1 1
1 0 0
1 1 Qold
Expanded Version
10
Input s Output s Mode of Operation
Comment 𝑺 𝑹 𝑸 𝑸 0 0 NC NC Hold No change.
0 1 0 1 Reset For RESET ting Q to 0
1 0 1 0 Set For SETting Q to 1
1 1 0 0 Prohibited Invalid Condition
Q
Q
S
R
R
S
Q
Q
Inputs Outputs Mode
of Operation Comment
𝑺 𝑹 𝑸 𝑸 0 0 1 1 Prohibited Invalid Condition
0 1 1 0 Set For SETting Q to 1
1 0 0 1 Reset For RESETting Q to 0
1 1 NC NC Hold No change.
Short Version (Remember This!)
11
Q
Q
S
R
R
S
Q
Q
Inputs
Mode 𝑺 𝑹 0 1 SET
1 0 RESET
1 1 HOLD
Input Mode
S R
0 0 HOLD
0 1 RESET
1 0 SET
Operating S-R latch
12
Under normal conditions, both inputs of the latch remain at 0 unless the state is to be change.
The application of a 1 to the S input causes the latch to go to the set state.
The S input must go back to 0 before R is changed to 1 to avoid occurrence of the undefined state.
Applying a 0 to S with R = 0 leaves the circuit in the same state.
The application of a 1 to the R input causes the latch to go to the reset state.
We can then remove the one from R, and the circuit remains in the reset state.
Input Mode
S R
0 0 HOLD
0 1 RESET
1 0 SET
(1,1) Problem for S-R Latch
13
If a 1 is applied to both the inputs of the latch, both outputs
go to 0.
This produces an undefined state.
It results in an indeterminate or unpredictable next state
when both inputs return to 0 simultaneously.
In normal operation, these problems are avoided by making
sure that 1’s are not applied to both inputs simultaneously.
Operating S-R latch
14
Under normal conditions, both inputs of the latch remain at 1 unless the state is to be change.
The application of a 0 to the S input causes the latch to go to the set state.
The S input must go back to 1 before R is changed to 0 to avoid occurrence of the undefined state.
Applying a 1 to S with R = 1 leaves the circuit in the same state.
The application of a 0 to the R input causes the latch to go to the reset state.
We can then remove the 0 from R, and the circuit remains in the reset state.
Inputs
Mode 𝑺 𝑹 0 1 SET
1 0 RESET
1 1 HOLD
Example
15
Q
Q
S
R
Example
16
Q
Q
S
R
Input s
Mode 𝑺 𝑹 0 1 SET
1 0 RESET
1 1 HOLD
Gated Latch
17
A gated latch is a variation on the basic latch.
The gated latch has an additional input, called enable
(EN) that must be HIGH in order for the latch to
respond to the S and R inputs.
Gated Latch
18
R
SQ
Q
EN
This is the same as
the active-LOW
input latch!
A
B
Observe that:
A S EN S EN
B R EN R EN
EN A B
0 1 1
1 S R
Example: Gated S-R Latch
19
Exercise: Gated S-R Latch
20
Show the Q output with relation to the input signals. Assume Q
starts LOW.
S
R
EN
Q
Gated D latch
21
The D latch is a variation of the S-R latch.
Has only one input in addition to EN.
This input is called the D (data) input.
Combine the S and R inputs into a single D input.
D
EN
Q
QD
EN
Gated D Latch: Operation
22
A simple rule for the D latch is: Q follows D when the Enable is active/asserted. In this situation, the latch is said to be “open” and the path from D input to Q
output is “transparent”.
The circuit is often called a transparent latch for this reason.
When EN is LOW, the state of the latch is not affected by the D input. In this situation, the latch is said to be “close” The Q output retains its last value and no longer changes in response
to D, as long as EN remains negated.
Output is “latched” at the last value when the enable signal becomes not asserted.
Truth Table:Inputs
Comments
0
1
X
END
1
1
0
Outputs
0
1
Q0
1
0
Q0
RESET
SET
No change
Q0 is the prior output level before the
indicated input conditions were
established.
EN
D 𝑄
𝑄
Example: Gated D Latch
23
Q follows D when the Enable is active.
Q
QD
EN
Exercise: Gated D Latch
24
Determine the Q output for the D
latch, given the inputs shown.Q
QD
EN
EN
Q
D
Notice that the Enable is not active during these times, so the output is latched.
Latch: some final words….
25
Latch = A bistable digital circuit used for storing a bit.
RESET
1. The state of a latch when the output (Q) is 0.
2. The action of producing a RESET state.
SET
1. The state of a latch when the output (Q) is 1.
2. The action of producing a SET state.
Latch as a Contact-Bounce Eliminator
26
When the contacts of any mechanical switch bang together they rebound a bit before settling, causing bounce.
Debouncing is the process of removing the bounces.
The trigger
switches from
an old cheap
game-playing
joystick.
Mouse button
from an ancient
Compaq
computer
http://www.embedded.com/columns/breakpoint/18400810?_requestid=100290
Switch Bounce Phenomenon
27
Mechanical switch cannot be used as such
to produce a clean voltage transition.
The output makes several transitions
between 0 and +V volts for a few
milliseconds owing to contact bounce
before it finally settles at +V volts.
Although this random behavior lasts only
for a few milliseconds, it is unacceptable
for many digital circuit applications.
Contact-Bounce Eliminator (2)
28
Key Idea: The S-R latch is in “hold” mode for each bounce
and hence the final output does not change.
Logic Symbols: Latches and Flip-Flops
29
Flip-Flop
30
Latches sample their inputs (and change states) any time the
EN bit is asserted.
Flip-flops are synchronous: the output changes state only
at a specified point on the triggering input called the clock
(CLK)
In other words, changes in the output occur in synchronization
with the clock.
An edge-triggered flip-flop changes state either at the
positive edge (rising edge) or at the negative edge
(falling edge) of the clock pulse.
Edge-Triggered Flip-Flops
31
Positive edge-triggered (no bubble at C input)
Negative edge-triggered (bubble at C input)
“Edge-triggered flip-
flop” is redundant (all
flip-flops are edge-
triggered
Clock (CLK)
32
In digital synchronous systems, all waveforms are synchronized with a clock. The clock waveform itself does not carry information.
The clock is a periodic waveform in which each interval between pulses (the period) equals the time for one bit.
Notice that change in level of waveform A occurs at the rising edge of the clock waveform.
D Flip-Flop
33
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its D
input only on the rising edge of the clock.
The truth table for a negative-edge triggered D flip-flop is
identical except for the direction of the arrow.
Inputs
Comments
1
CLKD
Outputs
1
0 SET
0 0 1 RESET
Inputs
Comments
1
CLKD
Outputs
1
0 SET
0 0 1 RESET
(a) Positive-edge triggered (b) Negative-edge triggered
C
D 𝑄
𝑄
= clock transition LOW to HIGH
D Flip-Flop
34
Q follows D on the rising edge of the clock
Exercise
35
CLK
D
CLK
Q
Q
What specific function does this device perform?
Exercise
36
CLK
D
CLK
Q
Q
It is a D flip-flop hardwired for a toggle mode.
For example, if Q is LOW, Q is HIGH and the flip-flop will toggle
on the next clock edge. Because the flip-flop only changes on the
active edge, the output will only change once for each clock
pulse.
D Flip Flop: Implementation
37
Tie two D-latches together to make a D flip-flop
When C is 0 (C1 = 1), the master latch is open and follows
the D input.
When C is 1 (C1 = 0, C2 = 1), the master latch is closed and
its output is transferred to the slave latch.
The slave latch is open all the while that C is 1, but changes only
at the beginning of this interval, because the master is closed
and unchanging during the rest of the interval.
EN
D 𝑄
𝑄
EN
D 𝑄
𝑄
C
D
Master Slave
QM
C1 C2
D Flip Flop: Implementation
38
EN
D 𝑄
𝑄
EN
D 𝑄
𝑄
C
D
Master Slave
QM
C1 C2
1C C
C
2C C
MQ
Q
D
S-R Flip-Flop
39
J-K Flip-Flop
40
Has two inputs, labeled J and K (along with the CLK).
When both J and K = 1, the output changes states (toggles)
on the rising clock edge.
Inputs
Comments
1
1 1
1
CLKKJ
Outputs
1
Q0
Q0
Q0
Q0
0 SET
Toggle
0
0
00 0 1 RESET
No changeCLK
K
J
Q
Q
A J-K flip-flop connected for toggle operation is sometimes called a T flip-flop.
J-K Flip-Flop
41
Exercise: J-K Flip-Flop
42
CLK
Q
K
J
Set Toggle Set Latch
CLK
K
J
Q
Q Inputs
Comments
1
1 1
1
CLKKJ
Outputs
1
Q0
Q0
Q0
Q0
0 SET
Toggle
0
0
00 0 1 RESET
No change
Negative-Edge Triggered J-K FF
43
Caution
44
When designing a circuit, do not change input values at the
moment that the clock is rising.
This is the time that the flip-flops read the input values.
Asynchronous Inputs
45
Most flip-flops have other inputs that are asynchronous, meaning they affect the output independent of the clock.
Two such inputs are normally labeled preset (PRE) and clear (CLR).
These inputs are usually active-LOW.
A J-K flip flop with active-LOW preset and CLR is shown.
CLK
K
J
Q
Q
PRE
CLR
Example
46
Exercise
47
Set Toggle Reset Toggle
Set
Set
Reset
Latch
CLK
K
J
Q
PRE
CLR
CLK
K
J
Q
Q
PRE
CLR
Latches and Flip-Flops
48
The most basic storage elements are latches, from which flip-flops are usually constructed.
Can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states.
The major differences among the various types of latches and flip-flops are the number of inputs the process and the manner in which the inputs affect the binary state.
Although latches are most often used within flip-flops, they can also be used with more complex clocking methods to implement sequential circuits directly.
The design of such circuits is, however, beyond the scope of this class.
Logic Symbols: Latches and Flip-Flops
49
Some Applications
50
Divide the clock frequency by 2
Some Applications
51
Divide the clock frequency by 4
Counting in Binary
2
We have seen that the binary count sequence follows a
familiar pattern of 0‟s and 1‟s.
LSB changes on every
number.
The next bit changes on
every other number.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The next bit changes on
every fourth number.
Counter
3
A counter can form the same pattern of 0‟s and 1‟s with logic
levels.
The first stage in the counter represents the least significant
bit (LSB) – notice that these waveforms follow the same
pattern as counting in binary.
0 1 0 1 0 1 0 1 0
0 0 1 1 0 0 1 1 0
0 0 0 0 1 1 1 1 0
LSB
MSB
Ex: 2-bit Asynchronous Binary Counter
4
Asynchronous counter
5
Counters are classified into two broad categories according
to the way they are clocked:
1. Asynchronous counter
2. Synchronous counter
The term asynchronous refers to events that do not have a
fixed time relationship with each other and, generally, do not
occur at the same time.
Asynchronous counters
The FFs within the counter do not change states at exactly the
same time because they do not have a common clock pulse.
Asynchronous counter (con’t)
6
Commonly called ripple counters
The FFs are connected for toggle operation (J = 1, K = 1)
The first FF is clocked by the external clock pulse (CLK).
Each successive FF is clocked by the output of the preceding
FF.
Ex: 3-bit Asynchronous Counter
7
CLK
K0
J0
Q0
Q0
C C C
J1 J2
K1 K2
Q1 Q2
Q1
HIGH
CLK
Q0
Q1
Q2
1 2 3 4 5 6 7 8
10 10 10 10 0
10 10 01010
00 11 01100
(LSB)
(MSB)
Recycle back to 0
Ex: 3-bit Asynchronous Counter
8
CLK
K0
J0
Q0
Q0
C C C
J1 J2
K1 K2
Q1 Q2
Q1
HIGH
CLK
Q0
Q1
Q2
1 2 3 4 5 6 7 8
10 10 10 10 0
10 10 01010
00 11 01100
(LSB)
(MSB) The second flip-
flop is triggered
by the negative-
edges of Q0.
Ex: 3-bit Asynchronous Counter
9
CLK
K0
J0
Q0
Q0
C C C
J1 J2
K1 K2
Q1 Q2
Q1
HIGH
CLK
Q0
Q1
Q2
1 2 3 4 5 6 7 8
10 10 10 10 0
10 10 01010
00 11 01100
(LSB)
(MSB)The third flip-flop
is triggered by the
negative-edges of
Q1.
Ex: Four-bit binary ripple counter.
10
Summary: n-bit Binary Ripple Counter
11
Use a cascaded arrangement of FFs where the output of one flip-flop drives the clock input of the following flip-flop.
The clock input is applied only to the first FF, also called the input FF.
The clock input to any subsequent FF comes from the output of its immediately preceding flip-flop.
After the occurrence of each clock input pulse, the counter has to wait for a time period equal to the sum of propagation delays of all flip-flops before the next clock pulse can be applied.
(Also called asynchronous counter or serial counter)
Modulus
12
The modulus (MOD number) of a counter is the number of
unique (logic) states through which the counter will sequence.
The maximum possible number of states (maximum modulus) of a
counter is 2n, where n is the number of FFs in the counter.
An n-bit counter that counts through all its natural states and does not
skip any of the states has a modulus of 2n.
Counters can be designed to have a number of states in their
sequence that is less than the maximum of 2n.
This type of sequence is called a truncated sequence.
To obtain a truncated sequence, it is necessary to force the counter
to recycle before going through all of its possible states.
Counters with Truncated Sequences
13
One common modulus for counters with truncated
sequences is ten (called MOD10).
Counters with ten states in their sequence are called decade
counters.
A decade counter with a count sequence of zero (0000)
through nine (1001) is a BCD decade counter because
its ten-state sequence produces the BCD code.
The BCD decade counter must recycle back to the 0000 state
after the 1001 state.
We will use a technique called partial decoding.
BCD Decade Counter (1)
14
A decade counter requires four FFs.
Three FFs are insufficient because 23 = 8.
Start with 4-bit asynchronous binary counter
Want to recycle here!
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
BCD Decade Counter (2)
15
This is used to
detect the
number 10
When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line.
0 1 2 3 4 5 6 7 8 9 0
BCD Decade Counter (3)
16
One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to the active-LOW CLR inputs of the FFs.
Partial Decoding: In our circuit, only Q1and Q3 are connected to the NAND gate
inputs. The two unique states (Ql = 1 and Q3 = 1) are sufficient to decode
the count of ten because none of the other states (zero through nine) have both Ql and Q3 HIGH at the same time.
CLK
K0
J0Q0
C C C
J1 J2
K1 K2
Q1 Q2
HIGH
C
J3
K3
Q3
CLR
10 Decoder
Q3 Q2 Q1 Q0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
K-Map Derivation of Partial Decoding
17
Q3 Q2 Q1 Q0 CLR
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
0
0
0
0
0
0
0
0
Q1
Q3
Q0
X
X
0
0
X
X
X
1
Q2
1 3Q Q
Ex: MOD12 Counter
18
Q3 Q2 Q1 Q0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
74x93
19
4-Bit Asynchronous Binary Counter
Consist of single flip-flop and a 3-bit asynchronous counter.
74x93
20
The counter can be extended to form a 4-bit counter by
connecting Q0 to the CLK B input.
Provide gated reset inputs, RO(1) and RO(2).
When both of these inputs are HIGH, the counter is reset to the
0000 state.
74x93 Applications
21
74x93 as a MOD10 counter
74x93 as a MOD12 counter
74x93 as a MOD16 counter
Exercise: Show how to connect a
74x93 4-bit asynchronous counter as
a MOD12 counter.
The qualifying label “CTR DIV N” indicates a counter with N states.
Synchronous Counters
22
The term synchronous refers to events that have a fixed time relationship with each other.
A synchronous counter is one in which all the flip-flops in the counter are clocked at the same time by a commonclock pulse.
Hence, all FFs in the counter change state at the same time in synchronism with the input clock signal.
Also known as a parallel counter.
Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes.
Caution!
23
The analysis and design of synchronous counter is significantly different from the analysis and design of asynchronous counter
Recall: Suppose we want to count from 0 to 9. For asynchronous counter,
we let the number 10 shows up first,
we detect it with a simple decoder,
then we use the detection to asynchronously clear all the FFs back to 0.
In other words, the number 10 actually shows up on the output but only for a short time (so short that you many not see it in the real circuit.)
Synchronous Counters (2)
24
We won‟t use the same technique (of asynchronously zeroing
all FFs) in synchronous design.
Reason: It is asynchronous!
We want to change the value of the states/outputs of the FFs
only at the rising edge of the clock.
In other words, if we let the number 10 shows up, it will be
there until the next rising edge of the clock.
So, we need to come up with a new technique.
Tabular analysis.
Caution!
25
We will study two techniques.
The first technique (tabular analysis) is here to give you some
intuition about the more-general second technique.
Once we are done with the first technique, we will move on
to the second technique and will not use the first technique
anymore!
Ex: 2-Bit Synchronous Binary Counter
26
Summary of Analysis
27
1. Find the equations that govern the relationship between the FF inputs (Ji, Ki) and the FF outputs (states: Qi).
2. Start with a relevant arbitrary state (combination of outputs). We will start with a state where every Qi is 0.
3. Calculate the value of the inputs (Ji, Ki) of all FFs. This tell us the modes of the FFs.
4. Find the next state (combination of outputs of the FFs) at the next clock pulse from the modes.
5. Repeat the last two steps until the counter recycles.
Outputs J-K Inputs
Q1 Q0 1 0J Q 1 0K Q 0 1J 0 1K
0 0 0 0 1 1
0 1 1 1 1 1
1 0 0 0 1 1
1 1 1 1 1 1
Ex: 3-bit Binary Synchronous Counter
28
This 3-bit binary synchronous counter has the same count
sequence as the 3-bit asynchronous counter shown
previously.
K0
J0
Q0
C C C
J1 J2
K1 K2
Q0Q1Q0 Q1 Q2
CLK
HIGH
Analysis of Synchronous Counters
29
A tabular technique for analysis is illustrated for the counter on the previous
slide. (1) Write the logic equation for each input.
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
Outputs Logic for inputs
(2) Put the counter in an arbitrary
state; then (3) determine the
inputs for this state.
0 0 0 0 0 0 0 1 1
(4) Use the new inputs to
determine the next state: Q2 and Q1
will latch and Q0 will toggle.
0 0 1 0 0 1 1 1 1
(5) Set up the next
group of inputs from
the current output.
(7) Continue like this, to complete the table.
The next slide shows the completed table…
0 1 0 (6) Q2 will latch again but both Q1 and Q0 will toggle.
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
Analysis of Synchronous Counters
30
Outputs Logic for inputs
0 0 0 0 0 0 0
0 0 1 0 0 1 1
0 1 0 1 1
1 1
1 1
1 1
1 1
1 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 1 1
0 0 0
1 1 1 1
At this point all states have been accounted for
and the counter is ready to recycle…
1 1
1 1
4-bit Synchronous Binary Counter
31
The 4-bit binary counter has
one more AND gate than the
3-bit counter just described.
The shaded areas show
where the AND gate outputs
are HIGH causing the next
FF to toggle.
BCD Decade Counter
32
With some additional logic, a binary counter can be
converted to a BCD synchronous decade counter.
After reaching the count 1001, the counter recycles to 0000.
CLK
J0
K0
C
HIGH
FF0 FF1 FF2 FF3
Q3
Q0
Q0
J1
K1
C
Q1
Q1
J2
K2
C
Q2
Q2
J3
K3
C
Q3
Q3
Q0
Q3
BCD Decade Counter: Tabular Analysis
33
Q3 Q2 Q1 Q0 3 3 0 3 0 1 2J K Q Q Q Q Q 2 2 0 1J K Q Q 1 1 0 3J K Q Q 0 0 1J K
0 0 0 0
BCD Decade Counter: Tabular Analysis
34
Q3 Q2 Q1 Q0 3 3 0 3 0 1 2J K Q Q Q Q Q 2 2 0 1J K Q Q 1 1 0 3J K Q Q 0 0 1J K
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 1
0 0 1 0 0 0 0 1
0 0 1 1 0 1 1 1
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 1
0 1 1 0 0 0 0 1
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 1
0 0 0 0
BCD Decade Counter Design
35
The previous slide shows that the given design works.
How can we get it in the first place?
In particular, where do these logic parts come from?
CLK
J0
K0
C
HIGH
FF0 FF1 FF2 FF3
Q3
Q0
Q0
J1
K1
C
Q1
Q1
J2
K2
C
Q2
Q2
J3
K3
C
Q3
Q3
Q0
Q3
BCD Decade Counter: Derivation
36
Q3 Q2 Q1 Q0 3 3J K 2 2J K 1 1J K 0 0J K
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
BCD Decade Counter: Derivation
37
Q3 Q2 Q1 Q0 3 3J K 2 2J K 1 1J K 0 0J K
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 1
0 0 1 0 0 0 0 1
0 0 1 1 0 1 1 1
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 1
0 1 1 0 0 0 0 1
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 1
0 0 0 0
Recall: Truth Table v.s. K-map
38
A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
C
A
B
0
0
0
0
0
1
1
1
C AB
Input Columns
Output Column
Recall: Karnaugh Map
39
The small number inside each cell is the corresponding row number
in the truth table, assuming that the truth table inputs are labeled
alphabetically from left to right (e.g. A, B, C) and the rows are
numbered in binary counting order.
Ro
w #
A B C
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Ro
w #
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
0
1
4
5
3
2
7
6
C
A
D
12
13
8
9
15
14
11
10
B
01 00 10 11
11
10
00
01
CD
AB
C
A
B
0
1
2
3
6
7
4
5
1 0
11
10
00
01
C
AB
BCD Decade Counter: Derivation
40
Q3 Q2 Q1 Q0 3 3J K 2 2J K 1 1J K 0 0J K
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 1
0 0 1 0 0 0 0 1
0 0 1 1 0 1 1 1
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 1
0 1 1 0 0 0 0 1
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 1
0 0 0 0
0
1
0
1
1
0
1
0
Q1
Q3
Q0
X
X
0
0
X
X
X
X
Q2
0
0
0
0
1
0
1
0
Q1
Q3
Q0
X
X
0
0
X
X
X
X
Q2
0
0
0
0
0
0
1
0
Q1
Q3
Q0
X
X
0
1
X
X
X
X
Q2
Caution!
41
Now we are done with the first technique for designing counter.
It is a fine technique but have some disadvantages:1. We need to work on the row-by-row basis. (The formula are
defined column-wise; so it seems that working with columns might be faster.)
2. We assume that we start from „0‟, find the next state (on the next row), and then keep finding the next state until we get back to „0‟, at which point we stop.
What would happen if we stat from a state which is not in the sequence above?
3. We assume that J = K. Can we have a simpler circuit if we don‟t use this assumption.
After we study 74x163, we will move on to the second technique and will not use the first technique anymore!
74x163
42
4-bit Synchronous Binary Counter
Has several extra features
Can be synchronously preset to any 4-bit binary number when the active-LOW LOAD input is activated.
The active-LOW clear input (CLR) synchronously resets all four FFs.
The two enable inputs, ENP and ENT must both be HIGH for the counter to sequence through its binary states.
CTR DIV 16(1)
(9)
(7)
(10)
C(2)
(3) (4) (5) (6)
(14) (13) (12) (11)
TC = 15(15)
Data inputs
Data outputs
CLR
LOAD
ENT
ENP
CLK
RCO
Q0 Q1 Q2 Q3
D0 D1 D2 D3
The ripple clock output
(RCO) goes HIGH when the
counter reaches the last state
in its sequence of fifteen,
called the terminal count
(TC = 15).
Example: 74x163
43
Example: 74x163
44
Example: 74x163
45
Example: 74x163
46
Copied
Example: 74x163
47
The ripple clock output
(RCO) goes HIGH when
the counter reaches the
last state in its sequence
of fifteen, called the
terminal count (TC =
15).
Example: 74x163
48
74x163: Logic Diagram
49
74x163: State Table
50
74x163: Application
51
Count from 0 to 10. Then, repeat.
74x163: Application
52
Count from 5 to 15. Then, repeat.
Exercise
53
What will this counter do?
Caution!
54
Now, we will present the second technique for designing
counter.
This technique is general enough for designing any sequential
circuit.
It is different from the first technique in many ways.
We start by listing all the possible states
For each state, we find out what would be the next state.
In particular, for the first technique, we find out the next state
by looking at the state value in the row below. This is not true
for the second technique. The next states are listed on the
column to the right.
Counter Design Technique
55
We want to design counters with arbitrary sequences.
Today, we will discuss in detail a commonly used technique for designing synchronous counters using J-K flip-flops or D flip-flops.
The design of the counters basically involves designing a suitable combinational logic circuit that
takes its inputs from the normal and complemented outputs of the FFs used and
decodes the different states of the counter
to generate the correct logic states for the inputs of the FFs such as J, K, D, etc.
We will start by learning sequential circuit design techniques.
Sequential Circuits
56
Also known as state machine.
A general sequential circuit consists of a combinational logic section and a memory section (FFs).
In a clocked sequential circuit, there is a clock input to the memory section.
Sequential Circuits
57
At any given time, the memory is in a state called the
present/current state.
The present state is represented by the state variables (Q0,
Q1, Q2, Q3,…)
It will advance to the next state on the clock pulse.
The next state is determined by the conditions on the
excitation lines and the current sate.
State Transition Diagram
58
The state transition diagram is a graphical representation of
different states of a given sequential circuit and the sequence
in which these states occur in response to a clock input.
Different states are represented by circles, and the arrows
joining them indicate the sequence in which different states
occur.
Ex. State transition diagram for
a MOD-8 binary counter.
Step 1: State Diagram
59
Specify the counter sequence and draw a state diagram.
As an example, here is a state diagram for a 3-bit Gray code counter.
001
011
010
110
100
101
111
000
Step 2: Next-State Table
60
List each state of the counter (current state) along with the
corresponding next state.
Present State Next State
Q2 Q0
0 00 10 10 0
Q1
0011
1 011 111 101 00
Q2 Q0
0 10 10 01 0
Q1
0111
1 111 101 000 00
001
011
010
110
100
101
111
000
Step 3: FF Excitation Inputs
61
Find the J and K inputs required for the transitions in the
Next-State Table
Current State Next State FF2 FF1 FF0
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
Step 3: FF Excitation Inputs
62
Find the J and K inputs required for the transitions in the
Next-State Table
Rearranged
to our
familiar form
Current State Next State FF2 FF1 FF0
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 1 1
1 1 1 1 0 1
We will first develop a transition table showing the FF inputs required for each transition.
FF Excitation/Transition Table
63
The excitation table lists the present state, the desired next state and
the flip-flop inputs (J, K, D, etc.) required to achieve that.
Excitation table of a D flip-flop.Excitation table of a J-K flip-flop.
An X indicates a “don't care” (the input can be either a 1 or a 0).
The transition table is always the same for a given type of flip-flop.
Current State Next State FF2 FF1 FF0
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 1 X
0 0 1 0 1 1 X 0
0 1 0 1 1 0 0 X
0 1 1 0 1 0 X 1
1 0 0 0 0 0 0 X
1 0 1 1 0 0 X 1
1 1 0 1 1 1 1 X
1 1 1 1 0 1 X 0
Step 3: Find Excitation Inputs to FFs
64
OutputTransitions
Flip-FlopInputs
QN QN+1
0 00 11 01 1
J K
0 X1 XX 1X 0
For the current state 000, Q0 goes from a present state of 0 to a next state
of 1. To make this happen, J0 must be a 1 and you don't care what K0 is (J0
= 1, K0 = X),
Step 3: Find Excitation Inputs to FFs
65
OutputTransitions
Flip-FlopInputs
QN QN+1
0 00 11 01 1
J K
0 X1 XX 1X 0
Current State Next State FF2 FF1 FF0
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
Step 4: Karnaugh Maps
66
Karnaugh maps can be used to determine the logic required
for the J and K inputs of each flip-flop.
FF0
J0 K0
1 X
X 0
0 X
X 1
0 X
X 1
1 X
X 0
0
There is a Karnaugh map for each input of each FF.
Review: Karnaugh Map
67
The small number inside each cell is the corresponding row number
in the truth table, assuming that the truth table inputs are labeled
alphabetically from left to right (e.g. A, B, C) and the rows are
numbered in binary counting order.
Ro
w #
A B C
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Ro
w #
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
0
1
4
5
3
2
7
6
C
A
D
12
13
8
9
15
14
11
10
B
01 00 10 11
11
10
00
01
CD
AB
C
A
B
0
1
2
3
6
7
4
5
1 0
11
10
00
01
C
AB
Step 5: Logic Expressions for FF Inputs
68
From the Karnaugh maps, we group the cells to generate the
logic expression for each FF input:
0 2 1 2 1 2 1
0 2 1 2 1 2 1
1 2 0
1 2 0
2 1 0
2 1 0
J Q Q Q Q Q Q
K Q Q Q Q Q Q
J Q Q
K Q Q
J Q Q
K Q Q
Step 6: Counter Implementation
69
Implement the expressions with combinational logic, and
combine with the FFs to create the counter.
0 2 1
0 2 1
1 2 0
1 2 0
2 1 0
2 1 0
J Q Q
K Q Q
J Q Q
K Q Q
J Q Q
K Q Q
Example: Arbitrary Counting Sequence
70
1
0 2
Method 1: Use D FFs
Current State Next State FF1 FF0
Q1 Q0 Q1 Q0 D1 D0
0 0 1 0 1 0
0 1 0 0 0 0
1 0 0 1 0 1
1 1 X X X X
1 1 0
0 1
D Q Q
D Q
C
D1 Q1
Q1
C
D0 Q0
Q0
CLK
Current State FF1 FF0 Next State
Q1 Q0 1 1 0D Q Q 0 1D Q Q1 Q0
0 0 1 0 1 0
0 1 0 0 0 0
1 0 0 1 0 1
1 1 0 1 0 1
1
0 2
3
K-maps
Check Answer
Example: Arbitrary Counting Sequence
71
1
0 2
C
J1 Q1
K1 Q1
1
C
J0 Q0
K0 Q0
CLK
Current State Next State FF1 FF2
Q1 Q0 Q1 Q0 J1 K1 J0 K0
0 0 1 0 1 X 0 X
0 1 0 0 0 X X 1
1 0 0 1 X 1 1 X
1 1 X X X X X X
1 0
1
0 1
0
1
1
J Q
K
J Q
K
Method 2: Use J-K FFs
K-maps
Example: Check Answer
72
Current State FF1 FF2 Next State
Q1 Q0 1 0J Q 1 1K 0 1J Q 0 1K Q1 Q0
0 0 1 1 0 1 1 0
0 1 0 1 0 1 0 0
1 0 1 1 1 1 0 1
1 1 0 1 1 1 0 0
C
J1 Q1
K1 Q1
1
C
J0 Q0
K0 Q0
CLK
1
0 23
Example: Comparison
73
C
D1 Q1
Q1
C
D0 Q0
Q0
CLK
1
0 2
3
C
J1 Q1
K1 Q1
1
C
J0 Q0
K0 Q0
CLK
Method 2: Use J-K FFs
1
0 23
Method 1: Use D FFs
Exercise
74
Design a counter which satisfies all of the following
requirements:
1. Have one-bit input signal called CTEN.
2. Have three-bit output signal called Y2, Y1, Y0.
3. The counting sequence agrees with the following state
diagram:
The numbers on the arrows indicate the values of CTEN.
4. Use exactly one D flip-flop and one XOR gate.
5. No additional gate allowed.
3 7
1
1
0 0
Exercise
75
Expected Waveform:
3 7
1
1
0 0
Solution
76
Sequential Circuits
77
In general, sequential circuits can be classified into two types
1. Moore circuits: the output(s) depend only on the present
internal state
2. Mealy circuits: the output(s) depend on both the present
state and the input(s).
Synchronous Cascading
78
Use
1. count enable (CTEN) On some devices, CTEN is labeled as G
2. terminal count (TC) Same as ripple clock output (RCO) on some IC counters
The next counter is enabled only when the TC of the previous stage is reached.
Cascaded Counters
79
Cascading is a method of achieving higher-modulus counters.
In essence, cascading means that the last-stage output of
one counter drives the input of the next counter.
Asynchronous Cascading:
Synchronous Cascading
80
Use
1. count enable (CTEN) On some devices, CTEN is labeled as G
2. terminal count (TC) Same as ripple clock output (RCO) on some IC counters
The next counter is enabled only when the TC of the previous stage is reached.
Example:
81
Determine the overall modulus of the following cascaded
counters:
The over all modulus is 8 12 6 1536
The over all modulus is 10 4 7 5 1400
Application: Digital Clock
82
Register
2
Flip-flops are used in a variety of application circuits, the
most common among these being
counting circuits and
frequency division and
data storage and transfer (data movement) circuits.
Counters and registers
Belong to the category of MSI sequential logic circuits.
Similar architecture: both comprise a cascaded arrangement of
more than one FFs.
Both constitute very important building blocks of sequential
logic
Register
3
A register, unlike a counter, has no specified sequence of
states, except in certain very specialized applications.
Application
Counters are mainly used in counting applications, where they
either measure the time interval between two unknown time
instants or measure the frequency of a given signal.
Registers are primarily used for the temporary storage of data
present at the output of a digital circuit before they are fed to
another digital circuit.
Register and Shift Register
4
The storage capacity of a register is the total number of
bits (1s and 0s) of digital data it can retain.
Since each FF can store one bit of data, the storage capacity of
the shift register equals the number of FFs used.
The shift capability of a register permits the movement of
data from stage to stage within the register or into or out of
the register upon application of clock pulses.
Shift Register
5
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.
Some basic data movements are illustrated here.
The basic building block in all shift registers is the FF, mainly
a D-FF.
Data in Data in
Data in
Data in
Data in
Data out Data out Data out
Data out Data out
Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out
Parallel in/parallel outSerial in/parallel out Rotate right Rotate left
Although in many of the commercial shift register ICs their internal circuit
diagram might indicate the use of S-R FFs, a careful examination will reveal that these S-
R FFs have been wired as D FFs only.
SISO SISO PISO
SIPO PIPO
Serial-in/Serial out Shift Register
6
Accept data serially: one bit at a time on a single line.
Each clock pulse will move an input bit to the next FF. For
example, a 1 is shown as it moves across.
Five-bit serial-in serial-out register.
C
FF0
CLK
C
FF1
C
FF2
C
FF4
D0 D1 D2 D4
Serialdataoutput
Serial
datainput
C
FF3
D3 Q4Q0 Q1 Q2 Q3
1 1 1 1 1 1
CLKCLKCLKCLKCLK
Basic Application: SIPO
7
An application of shift registers is conversion of serial data to parallel form.
For example, assume the binary number 1101 is loaded sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
They can be stored for any length of time as long as the FFs have dc power.
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q31
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q30 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q31 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q31 1 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q31X 1 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serialdatainput
C
FF3
D3Q0 Q1 Q2 Q31X 1 0 1
CLKCLKCLKCLK
SIPO Shift Register
8
PISO Shift Register
9
PIPO Shift Register
10
Memory
2
Memory is the portion of a computer or other system that
stores binary data.
The smallest unit of binary data, as you know, is the bit.
In many applications, data are handled in an 8-bit unit called
a byte.
Each storage element in a memory can retain either a 1 or a
0 and is called a cell.
Memory Capacity
3
The term word can have two meanings in computer
terminology.
In memories, it is defined as a group of bits or bytes that acts as
a single entity that can be stored in one memory location.
In assembly language, a word is specifically defined as two bytes.
A memory is identified by the number of words it can
store times the word size.
A 16k 8 memory can store 16,384 words of eight bits each.
The capacity of a memory is the total number of data units
that can be stored.
Memory Address
4
The location of a unit of data in a memory is called the
address.64 1
8 8
Memory Address (2)
5
The address depends on
how the memory is
organized into units of data.
Personal computers have
random-access memories
organized in bytes.
The smallest group of bits
that can be addressed is
eight.
64 8
Basic Memory Operations
6
The write operation puts data into a specified address in
the memory.
The read operation copies data out of a specified address
in the memory.
The addressing operation, which is part of both the write
and the read operations, selects the specified memory
address.
Data Bus
7
Data units go into the memory during a write operation and
come out of the memory during a read operation on a set of
lines called the data bus.
The data bus is bidirectional, which means that data can go
in either direction (into the memory or out of the memory).
Address Bus
8
For a write or a read operation, an address is selected by
placing a binary code representing the desired address on a
set of lines called the address bus.
The number of lines in the address bus depends on the
capacity of the memory.
•16-bit address code can
select 65,536 locations
(216) in the memory
•32-bit address code can
select 4,294,967,296
(4G) locations (232) in
the memory
3D Memory Array
9
Simplified Write Operation
10
Simplified Read Operation
11
Categories
12
Memory
RAM
DRAM
SRAM
ROM
EPROM
PROM
EEPROM
Mask
Hybrid
NVRAM
Flash
EEPROM
RAM: Random-Access Memory
13
All addresses are accessible in an equal amount of time and can be selected in any order for a read or write operation.
This is in contrast to sequential memory devices such as magnetic tapes in which the mechanical movement of the storage medium forces the computer to access data in a fixed order.
All RAMs have both read and write capability.
Volatile: lose stored data when the power is turned off.
Typically used for short-term data storage
Two major categories of RAM
1. Static RAM (SRAM)
2. Dynamic RAM (DRAM)
Computer Memory
14
People in the computer industry commonly use the term
“memory” to refer to RAM
A computer uses RAM to hold temporary instructions and
data needed to complete tasks.
This enables the computer’s CPU (Central Processing Unit), to
access instructions and data stored in memory very quickly.
These days, no matter how much memory your computer
has, it never seems to be quite enough.
In 1981, referring to computer memory, Bill Gates said, “640K
(roughly 1/2 of a megabyte) ought to be enough for anybody.”
RAM Family
15
SRAM and DRAM
16
Two major categories of RAM
1. Static RAM (SRAM) Generally use latches as storage elements
Can store data indefinitely as long as dc power is applied.
2. Dynamic RAM (DRAM) Use capacitors as storage elements
Can not retain data very long without the capacitors being recharged by a process called refreshing.
Data can be read much faster from SRAMs
DRAMs can store much more data for a given physical size and cost because the DRAM cell is much simpler, and more cells can be
crammed into a given chip area than in the SRAM.
SRAM and DRAM (2)
17
The first SRAM (256-bit) and DRAM (1024-bit) devices
were both created in 1970.
For the next few decades, both types of memory quadrupled
their capacities approximately every three years, but by the
beginning of the 21st century this had slowed to a doubling
every two to three years.
These days, DRAM (in its SDRAM incarnation) is used to
satisfy the bulk of a system’s RAM requirements, while
SRAM is used where speed is of the essence; for example, the
cache memory inside a CPU.
Address Multiplexing
18
DRAMs use a technique called address multiplexing to
reduce the number of address lines.
For example, consider a DRAM which have 10 address lines.
The ten address lines are time multiplexed at the beginning of a
memory cycle into two separate 10-bit address fields: the row
address and the column address.
First, the l0-bit row address is latched into the row address
latch. Next, the l0-bit column address is latched into the
column address latch.
The row address and the column address are decoded to select
one of the 1,048,576 addresses (220) in the memory array.
ROM: Read-only Memory
19
Nonvolatile: Retain stored data even if power is turned off
Data are stored permanently or semi-permanently.
Data can be read from a ROM, but there is no write
operation as in the RAM.
The ROM, like the RAM, is a random-access memory but
the term RAM traditionally means a random-access
read/write memory.
Memory Expansion: Word-Length
20
Memory can be expanded in either word length or word capacity or both.
Word-Length Expansion: the #bits in the data bus is increased
Example: One 65536 8 ROM from two 65536 4 ROMs
Word-Length Expansion (con’t)
21
Example: One 2m 2n RAM from two 2m n RAMs
Word-Capacity Expansion
22
When memories are expanded to increase the word capacity,
the number of addresses is increased.
Storage
23
Storage media are important, particularly in computer
applications, where they are used for mass nonvolatile
storage of data and programs.
Storage
Magnetic Storage
Magnetic Disk
Hard disk
Floppy disk
Zip diskTape
Optical (Laser) Storage
CD-R
(Recordable)
CD-RW
(Rewritable)
DVD-ROM
Spelling: Disc vs Disk
24
“Compact disc” (CD) is spelled with a “C”
A computer hard disk is spelled with a “K”
Disks are usually sealed inside a metal or plastic casing (often, a
disk and its enclosing mechanism are collectively known as a
"hard drive").
In modern technological contexts,
A disc refers to optical media, such as an audio CD, CD-ROM,
DVD-ROM, DVD-RAM, or DVD-Video disc
A disk refers to magnetic media, such as a floppy disk, the disk
in your computer's hard drive, an external hard drive.
CD: Layers
25
All optical media is constructed of layers of different materials.
The information is recorded as a series of pits (or bumps) on a polycarbonate substrate roughly 1.2 mm thick
The pits are coated with a thin layer of Al or gold (few 100s nm thick) and then protected by a 2-30 m shellac (lacquer)coating.
The lacquer coating is screen printed.
CD: Effect of Scratches
26
The bottom of a CD is made of a relatively thick piece of polycarbonate plastic.
Scratches on the polycarbonate are out of focus when the disc is read, and minor scratches are ignored completely.
It takes a deep scratch in the polycarbonate to affect the readability of a disc.
The top is protected by a thin coat of lacquer.
Even a small scratch in the lacquer can damage the reflector.
Scratching the top of a disc can render it unreadable, which is something to consider the next time you place a disc on your desk top-down “to protect it.”
CD: Pits and Spiral
27
The basic principle of storing data on a CD (and DVD) is the creation of pits and lands, which are translated into ones and zeros by a laser pickup head.
Pits are arranged as a single spiral. This spiral is over 3.7 miles (or 6 km) in length on a CD, and 7.8 miles (or 12.5
km) for a DVD.
The starting point for the spiral is towards the center of the disc with the spiral extending outward. Outer area: generally more prone to manufacturing defects
Facilitate adoption of smaller or larger diameter discs
CD: Pits and Spiral (2)
28
The disc is read and written from the inside out, which is the opposite of how hard drives organize data.
With spiral organization, there are no cylinders or tracks like those on a hard drive. (The term “track” refers to a grouping of data for optical media.)
The information along the spiral is spaced linearly, thus following a predictable timing.
Spiral contains more information at the outer edge of the disc than at the beginning.
If this information is to be read at a constant speed, the rotation of the disc must change between different points along the spiral.
CD: Some rough calculation
29
Playing time: 74 minutes and 33 seconds max (4473 sec)
Back-of-the-Envelope Calculation:
Original audio (data) bit rate
Disc Capacity
bit channel samples bits16 2 44.1k 1411200
channel sample sec sec
9bits secs bits bytes1.4M 4473 6.312 10 789 M
sec CD CD CD
CD and DVD
30
Little has changed in CD physics since the origin of CD audio discs in 1980.
Maintain physical compatibility with an established base of installed units
The structure of CD media was both groundbreaking and nearly ideal for this function.
DVDs are an evolutionary growth of CD’s with slight changes.
Considering the development of DVD follows the CD by 14 years, you can see that the CD was truly a revolutionary creation in its time.
DVD: Introduction
31
No single company “owns” DVD. The official specification was developed by a consortium of ten companies Hitachi, JVC, Matsushita, Mitsubishi, Philips, Pioneer, Sony, Thomson, Time
Warner, and Toshiba.
In May 1997, the DVD Consortium was replaced by the DVD Forum
Q: What Does DVD Stand For?
A: “Nothing.” The original meaning was digital videodisk. Some members of the DVD Forum have pointed out that DVD goes far
beyond video and have offered the painfully contorted phrase digital versatile disc as a solution, but this has never been officially accepted by the DVD Forum.
The DVD Forum decreed in 1999 that DVD, as an international standard, is simply three letters.
DVD: Capacity Increase
32
Introduced in the U.S. in 1997
Use the same diameter platter as a CD (120mm/4.75" diameter)
Hold 4.7GB rather than 700MB.
Use laser beam with a shorter wavelength (650 or 635 nm, compared with 780 nm for the CD)
Reduce the size of the beam spot
Allow the laser to focus on a smaller pit size and a closer track pitch
Pit length and track pitch are about half of CD’s 4x capacity More efficient recording algorithms (Mathematics) more capacity increase
DVD: Capacity (2)
33
Unlike the CD, which has one
substrate, the DVD consists of two
0.6-mm thick substrates bonded
back-to-back,
which gives it the necessary stiffness
to avoid disc wobble or tilt.
DVDs may record data on one side
only (single-sided) or on both sides
(double-sided).
Each side may have a single layer of
recording or two layers (dual-layer)
DVD Mastering and Stamping
34
Blu-ray Disc
35
Introduced in 2006
The Blu-ray name is a combination of "blue," for the color of
the laser that is used, and "ray," for optical ray.
The "e" in "blue" was purposefully left off because an
everyday word cannot be trademarked.
Electromagnetic Spectrum
36700 nm 400 nm
Blu-Ray Disc
37
DVD: 5x to 10x storage capacity of CD
Blu-ray Disc: 5x to 10x storage capacity of DVD
Use of a blue laser (which is where the format gets its name)
instead of a red laser
Converting Analog Signals to Digital
2
The real world is analog!
Interfacing between analog and digital is important.
Digitization
1. Sampling (and hold): Discretize the time
Get sampled values of the analog signal.
2. Quantization: Discretize quantity values
Convert each sampled value to a binary code.
Digitization (analog to digital)
3
Time
Vertical lines are
used for sampling
Horizontal lines are
used for quantization
001
000
010
011
100
101
110
111111
100
100
111
011
100
101
010
000
001 001
100111111100001000010100011001
Simplified block diagram of a digital
cellular phone
4
Digitization = loss of information?
5
At first glance, digitization of a continuous signal (audio,
image) appears to be an enormous loss of information,
because a continuous function is reduced to a function on a
grid of points.
Therefore the crucial question arises as to which criterion we
can use to ensure that the sampled points are a valid
representation of the continuous signal, i.e., there is no loss
of information.
Sampling
6
Sampling is the process of taking a sufficient number of discrete values of points on a waveform that will define the shape of wave form.
Suppose that we sample a signal at a uniform rate, once every Ts seconds.
We refer to Ts as the sampling period, and to its reciprocal fs
= 1/Ts as the sampling rate.
The more samples you take, the more accurately you can define a waveform.
Caution: If the sampling rate is too low, your may experience distortion (aliasing).
Example
7
This is the plot of sin(100t). What’s wrong with it?
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t
Example (con’t)
8
Signal of the form 0sin 2 f t have frequency 0f f Hz.
So, the frequency of sin 100 t is 50 Hz.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t
From time 0 to 1, it should
have completed 50 cycles.
However, our plot has only
one cycle.
It looks more like a plot of
sin 2 t
Example (con’t)
90 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t
Aliasing causes high-frequency
signal to be seen as low frequency.
Spectrum
10
We have been an example of a signal which contains only one
frequency.
Analog signals (sound, image, etc) usually contain a spectrum
of component frequencies.
Periodic signal can be expressed in terms of its components via
Fourier series.
In general, signal can be expressed in terms of its components
via Fourier transform.
Fourier Series
11
Example
12
Consider the following analog signal
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-4
-3
-2
-1
0
1
2
3
4
Time
Example
13
It can be written as
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-4
-3
-2
-1
0
1
2
3
4
Time
cos 2 2cos 4 sin 2x t t t t
Component Frequencies
14
cos 2 2cos 4 sin 2x t t t t
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Time
1f 2f 1f
Spectrum: Light
15
A source of light can have many colors mixed together
and in different amounts (intensities).
A rainbow, or prism, sends the different frequencies in
different directions, making them individually visible at
different angles.
Spectrum: Sound
16
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Time in seconds
sin(c*erf(t))
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.80
500
1000
1500
2000
2500
3000
3500
4000
sin(c*erf(t))
Time
Fre
quen
cy (
Hz)
0 0.5 1 1.5 2 2.5 3 3.5 4-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Frequency (kHz)
Pow
er/frequency (dB
/Hz)
sin(c*erf(t))
MATLAB’s demo
Spectrum: Voice
17
Sampling Theorem
18
In order to (correctly and completely) represent an analog
signal, the sampling frequency, fs, must be at least twice the
highest frequency component of the analog signal.
Given a sampling frequency, fs,
the Nyquist frequency is defined as fs/2.
If you've ever watched a film and seen the wheel of a rolling
wagon appear to be going backwards, you've witnessed
aliasing.
The movie's frame rate isn't adequate to describe the rotational
frequency of the wheel, and our eyes are deceived by the
misinformation!
Example (revisited)
19
Signal of the form 0sin 2 f t have frequency 0f f Hz.
So, the frequency of sin 100 t is 50 Hz.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
t
We need to sample at least
100 times per time unit.
Here, the number of
sample per time unit is 49,
which is too small to avoid
aliasing.
Demonstration of Aliasing of a
Sinusoidal Signal
20
http://www.dsptutor.freeuk.com/aliasing/AD102.html
Quantization
21
Quantization
22
