Digital IC Design Flow

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Digital IC Design FlowDigital IC Design Flow

Lecturer: Huai-Yi Hsu (許槐益 )

Date: 2004.02.27


pp. 2Huai-Yi HsuDigital IC Design Flow 2004.02.27

OutlineOutlineIntroductionIC Design FlowVerilog HistoryHDL concept



Moore’s Law: Driving Technology AdvancesMoore’s Law: Driving Technology Advances

Logic capacity doubles per IC at regular intervals (1965). Logic capacity doubles per IC every 18 months (1975).



Process Technology EvolutionProcess Technology Evolution



Chips SizesChips Sizes

Source: IBM and Dataquest



Shrinking Product CyclesShrinking Product Cycles

Shrinking product cycles Shrinking development turnaround times Need for productivity increase (remember the “design gap”)

PCS: Personal Communication Services



Design Productivity CrisisDesign Productivity Crisis

Human factors may limit design more than technology. Keys to solve the productivity crisis:

Design techniques: hierarchical design, SoC design (IP reuse, platform-based design), etc.

CAD: algorithms & methodology



Increasing Processing PowerIncreasing Processing Power Very high performance circuits in today’s technologie

s. Gate delays: ~27ps for a 2-input Nand in CU11 Operating frequencies: up to 500MHz for SoC/Asic, over 1G

Hz for custom designs

The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application

Enhanced Design Tools and Techniques Although not enough to close the “design gap”, tools are ess

ential for the design of today’s high-performance chips



IP-Based SoCsIP-Based SoCs An Evolutionary Path

Early days IP/Cores not really designed for reuse (no standard deliverable

s) Multiple Interfaces, difficult to integrate

IPs evolved: parameterization, deliverables, verification, synthesizable

On-Chip bus standards began to appear (e.g, IBM, ARM)

Reusable IP + Common on-chip bus architectures 1998: max number of cores > 30 cores

core content between 50% and 95%



IP / CoresIP / Cores Soft Core

Delivered as RTL verilog or VHDL source code with synthesis script (i.e: clock generation logic)

Customers are responsible for synthesis, timing closure, and all front-end processing

Firm Core Delivered as a netlist to be included in customer’s netlist (wit

h don't touch attribute) Possibly with placement information

Hard Core Due to their complexity, they are provided as a blackbox (GL

1/GDSII). Ex. Processors, analog cores, PLLs Usually very tight timing constraints. Internal views not be alt

erable or visible to the customer



Changes in the Nature of IC DesignChanges in the Nature of IC Design

(IEEE Spectrum Nov,1996)



Chasing the Design GapChasing the Design Gap



Evolution of Silicon DesignEvolution of Silicon Design

Source: “Surviving the SoC revolution – A Guide to Platform-based Design,” Henry Chang et al, Kluwer Academic Publishers, 1999



Methodology – Analysis and Verification Methodology – Analysis and Verification



IC Design and ImplementationIC Design and Implementation

IdeaDesign



Design FlowDesign Flow

Design Specification

Design Partition

Design Entry-VerilogBehavioral Modeling

Simulation/FunctionalVerification

Design Integration &Verification

Pre-SynthesisSign-Off

Synthesize and MapGate-Level Netlist

Post-Synthesis Design Validation

Post-SynthesisTiming Verification

Test Generation &Fault Simulation

Cell Placement, ScanChain & Clock Tree

Insertion, Cell Routing

Verify Physical &Electrical Design Rules

Extract Parasitics

Post-LayoutTiming Verification

Production-ReadyMasks

Production-ReadyMasks

Front End

Design Sign-Off

Back End



System SpecificationSystem Specification

From CIC



Algorithm MappingAlgorithm Mapping

RTL Level

System Level

From CIC



Gate and Circuit Level DesignGate and Circuit Level Design

From CIC



Physical DesignPhysical Design

From CIC



Behavioral ModelBehavioral Model

Transistor Level

Gate Level

Register Transfer Level

Architecture

Algorithm

System concept

Increasingbehavioralabstraction

Increasingdetailed

realization &complexity



Design DomainDesign Domain

Behaviorallevel of

abstraction

Design Model Domain

Abstract PhysicalStructural

System

Algorithm

RTL

Gate

Switch

ArchitectureDesign

StructuralDesign

LogicDesign

LayoutDesign

Verification

Verification

Verification

ArchitectureSynthesis

RTL levelSynthesis

Logic levelSynthesis



Introduction to HDLIntroduction to HDLHDL – Hardware Description Language

Why use an HDL ?Hardware is becoming very difficult to design

directlyHDL is easier and cheaper to explore different

design optionsReduce time and cost



Verilog HDLVerilog HDLBrief history of Verilog HDL

1985: Verilog language and related simulator Verilog-XL were developed by Gateway Automation

1989: Cadence Design System purchased Gateway Automation

1990: Cadence released Verilog HDL to public domain

1990: Open Verilog International (OVI) formed1995: IEEE standard 1364 adopted



Verilog HDLVerilog HDLFeature

HDL has high-level programming language constructs and constructs to describe the connectivity of your circuit.

Ability to mix different levels of abstraction freelyOne language for all aspects of design, test, and

verificationFunctionality as well as timingConcurrency performSupport timing simulation



Compared to VHDLCompared to VHDL Verilog and VHDL are comparable languages VHDL has a slightly wider scope

System-level modeling Exposes even more discrete-event machinery

VHDL is better-behaved Fewer sources of non-determinism

(e.g., no shared variables ???) VHDL is harder to simulate quickly VHDL has fewer built-in facilities for hardware

modeling VHDL is a much more verbose language

Most examples don’t fit on slides



The Verilog LanguageThe Verilog Language Originally a modeling language

for a very efficient event-driven digital logic simulator Later pushed into use as a specification language

for logic synthesis Now, one of the two most commonly-used languages

in digital hardware design (VHDL is the other) Combines structural and behavioral modeling styles



Different Levels of AbstractionDifferent Levels of Abstraction Architectural / Algorithmic

A model that implements a design algorithm in high-level language constructs

Register Transfer Logic (RTL) A model that describes the flow of data between registers

and how a design process these data. Gate

A model that describe the logic gates and the interconnections between them.

Switch A model that describes the transistors and the

interconnections between them.



Verilog HDL Behavior LanguageVerilog HDL Behavior Language Structural and procedural like the C programming lan

guage Used to describe algorithm level and RTL level Verilo

g models Key features

Procedural constructs for conditional, if-else, case, and looping operations.

Arithmetic, logical, bit-wise, and reduction operations for expressions.

Timing control.



Verilog HDL Structural LanguageVerilog HDL Structural LanguageUsed to describe gate-level and switch-level

circuits.Key features

A complete set set of combinational primitivesSupport primitive gate delay specificationSupport primitive gate output strength specification



Language ConventionsLanguage Conventions Case-sensitivity

Verilog is case-sensitive.Some simulators are case-insensitiveAdvice: - Don’t use case-sensitive feature!Keywords are lower case

Different names must be used for different items within the same scope

Identifier alphabet:Upper and lower case alphabeticals: a~z A~ZDecimal digits: 0~9Underscore: _



Language Conventions (cont’d)Language Conventions (cont’d) Maximum of 1024 characters in identifier First character not a digit Statement terminated by ; Free format within statement except for within quotes Comments:

All characters after // in a line are treated as a comment

Multi-line comments begin with /* and end with */ Compiler directives begin with // synopsys XXX Built-in system tasks or functions begin with $ Strings enclosed in double quotes and must be on a

single line “Strings”



Design EncapsulationDesign Encapsulation Encapsulate structural and functional details in a module

Encapsulation makes the model available for instantiation in other modules

module my_design (ports_list); ... // Declarations of ports go here

... // Structural and functional details go here endmodule



Port DeclarationPort DeclarationThree port types

Input port input a;

Output portoutput b;

Bi-direction port inout c;

net

net

netnet

input output

inout

reg or net reg or net

module

Port list

Port Declaration

module full_add (S, CO, A, B, CI) ;

output S, CO ; input A, B, CI ;

--- function description ---

endmodule



Two Main Data TypesTwo Main Data Types Nets represent connections between things

Do not hold their value Take their value from a driver such as a gate or

other module Cannot be assigned in an initial or always block

Regs represent data storage Behave exactly like memory in a computer Hold their value until explicitly assigned

in an initial or always block Never connected to something Can be used to model latches, flip-flops, etc.,

but do not correspond exactly Shared variables with all their attendant problems



Primitive CellsPrimitive Cells Primitives are simple modules Verilog build-in primitive gate

not, buf: Variable outputs, single input (last port)

and, or, buf, xor, nand, nor, xnor: Single outputs (first port), variable inputs

module full_add (S, CO, A, B, CI) ;

--- port Declaration ---

wire net1, net2, net3; xor U0(S,A,B,CI); and U1(net1, A, B); and U2(net2, B, CI); and U3(net3, CI, A); or U4(CO, net1, net2, net3); endmodule



How Are Simulators Used?How Are Simulators Used? Testbench generates stimulus and checks response Coupled to model of the system Pair is run simultaneously

Testbench System Model

Stimulus

ResponseResult checker



Example: TestbenchExample: Testbenchmodule t_full_add();wire sum, c_out;reg a, b, cin; // Storage containers for stimulus waveformsfull_add M1 (sum, c_out, a, b, cin); //UUTinitial begin // Time Out#200 $finish; // Stopwatchendinitial begin // Stimulus patterns#10 a = 0; b = 0; cin = 0; // Statements execute in sequence#10 a = 0; b = 1; cin = 0; #10 a = 1; b = 0; cin = 0; #10 a = 1; b = 1; cin = 0; #10 a = 0; b = 0; cin = 1; #10 a = 0; b = 1; cin = 1; #10 a = 1; b = 0; cin = 1; #10 a = 1; b = 1; cin = 1;endendmodule



Verilog SimulatorVerilog Simulator



Event-Driven SimulationEvent-Driven Simulation A change in the value of a signal (variable) during simulation is

referred to as an event Spice-like analog simulation is impractical for VLSI circuits Event-driven simulators update logic values only when signals

change



StylesStylesStructural - instantiation of primitives and

modulesRTL/Dataflow - continuous assignmentsBehavioral - procedural assignments



Structural ModelingStructural ModelingWhen Verilog was first developed (1984)

most logic simulators operated on netlistsNetlist: list of gates and how they’re

connectedA natural representation of a digital logic

circuitNot the most convenient way to express test

benches



Behavioral ModelingBehavioral ModelingA much easier way to write testbenchesAlso good for more abstract models of circuits

Easier to writeSimulates faster

More flexibleProvides sequencing

Verilog succeeded in part because it allowed both the model and the testbench to be described together



Style Example - StructuralStyle Example - Structuralmodule full_add (S, CO, A, B, CI) ;

output S, CO ;input A, B, CI ;

wire N1, N2, N3;

half_add HA1 (N1, N2, A, B), HA2 (S, N3, N1, CI);

or P1 (CO, N3, N2);

endmodule

module half_add (S, C, X, Y);

output S, C ;input X, Y ;

xor (S, X, Y) ;and (C, X, Y) ;

endmodule



Style Example – Dataflow/RTLStyle Example – Dataflow/RTL

module fa_rtl (S, CO, A, B, CI) ;


assign S = A ^ B ^ CI; //continuous assignmentassign CO = A & B | A & CI | B & CI; //continuous assignment

endmodule



Style Example – BehavioralStyle Example – Behavioral

module fa_bhv (S, CO, A, B, CI) ;


reg S, CO; // required to “hold” values between events.

always@(A or B or CI) //; begin S <= A ^ B ^ CI; // procedural assignment CO <= A & B | A & CI | B & CI; // procedural assignment end endmodule



How Verilog Is UsedHow Verilog Is Used Virtually every ASIC is designed using either Verilog

or VHDL (a similar language) Behavioral modeling with some structural elements “Synthesis subset”

Can be translated using Synopsys’ Design Compiler or others into a netlist

Design written in Verilog Simulated to death to check functionality Synthesized (netlist generated) Static timing analysis to check timing



An Example: CounterAn Example: Counter`timescale 1ns/1ns module counter; reg clock; // declare reg data type for the clock integer count; // declare integer data type for the count initial // initialize things - this executes once at start begin clock = 0; count = 0; // initialize signals #340 $finish; // finish after 340 time ticks end /* an always statement to generate the clock, only one statement follows the always so we don't need a begin and an end */ always #10 clock = ~ clock; // delay is set to half the clock cycle /* an always statement to do the counting, runs at the same time (concurrently) as the other always statement */ always begin // wait here until the clock goes from 1 to 0 @ (negedge clock); // now handle the counting if (count == 7) count = 0; else count = count + 1; $display("time = ",$time," count = ", count); end endmodule



An Example: Counter (cont’d)An Example: Counter (cont’d)Verilog using ModelSim

Assume working directory: VlogExamples/Counter Invoke ModelSim Change Directory to VlogExamples/Counter Copy file counter.v to the working directory Create a design library: vlib work Compile counter.v: vlog counter.v Start the simulator: vsim counter Run the simulation: e.g., run 200ns

> run 200# time = 20 count = 1# time = 40 count = 2# time = 60 count = 3# time = 80 count = 4# time = 100 count = 5# time = 120 count = 6# time = 140 count = 7# time = 160 count = 0# time = 180 count = 1# time = 200 count = 2



ModelSim SimulatorModelSim Simulator Creating a Project

Select Create a Project from the Welcome to ModelSim dialog box. Or select File >New > Project from the ModelSim Main window.



Add File to ProjectAdd File to Project



CompileCompile



Load DesignLoad Design



List SignalsList Signals



Run SimulationRun Simulation



Silos Verilog Logic SimulatorSilos Verilog Logic Simulator Free HDL simulator

Web:http://www.simucad.com/free_verilog_simulator/index.shtm



Edit Verilog FilesEdit Verilog Files



Create New ProjectCreate New Project



Add File to ProjectAdd File to Project



Starting SimulationStarting Simulation



Silos OverviewSilos Overview Silos is a logic simulation environment developed for use i

n the design and verification of electronic circuits and systems.

Silos can simulate designs at the behavioral, gate and switch levels that are modeled with the Verilog Hardware Description Language (HDL).

Silos can back annotate delays specified using the Standard Delay Format (SDF).



Debugging CapabilitiesDebugging Capabilities The mouse cursor can be held over variables and expressions i

n the source code to directly see their value at a time point. Drag and drop variables and expressions directly from the sourc

e file into the Data Analyzer waveform window, or from the Silos Explorer to the Data Analyzer window to provides easy access to the simulation results.

Unlimited traceback for behavioral and gate designs quickly isolates the cause of Unknown levels.

A graphical Finite State Machine entry, source code generation, documentation, and debugging tool.

Code Coverage reporting for Line reports and Operator reports display a purple dot beside any line or operator that was not executed by the testbench.



SummarySummaryIC design flowHistory of Verilog-HDLVerilog simulator

Next courseBasic concept of Verilog-HDL



Homework #0Homework #0Download the Verilog Simulator Setup the Verilog simulation environment.Opening new projectAdd Verilog file to projectRun simulation

Website: http://access.ee.ntu.edu.tw



Multiplexer Built From PrimitivesMultiplexer Built From Primitives

a

bsel

f

nsel f1

f2

g1

g2

g3g4

Verilog programs built from modulesEach module has an interface

Module may contain structure: instances of primitives and other modules

module mux(f, a, b, sel);output f;input a, b, sel;

and g1(f1, a, nsel),g2(f2, b, sel);

or g3(f, f1, f2);not g4(nsel, sel);

endmodule



Multiplexer Built From PrimitivesMultiplexer Built From Primitives

a

bsel

f

nsel f1

f2

g1

g2

g3g4

Identifiers not explicitly defined default to wires


and g1(f1, a, nsel),g2(f2, b, sel);

or g3(f, f1, f2);not g4(nsel, sel);

endmodule



Multiplexer Built With AlwaysMultiplexer Built With Always

a

bsel

f

Modules may contain one or more always blocks

Sensitivity list contains signals whose change triggers the execution of the block

module mux(f, a, b, sel);output f;input a, b, sel;reg f;

always @(a or b or sel) if (sel) f = b; else f = a;

endmodule



Multiplexer Built With AlwaysMultiplexer Built With Always

a

bsel

f

A reg behaves like memory: holds its value until imperatively assigned otherwise

Body of an always block contains traditional imperative code

module mux(f, a, b, sel);output f;input a, b, sel;reg f;

always @(a or b or sel) if (sel) f = a; else f = b;

endmodule



Mux with Continuous AssignmentMux with Continuous Assignment

a

bsel

f

LHS is always set to the value on the RHS

Any change on the right causes reevaluation


assign f = sel ? a : b;

endmodule



Mux with User-Defined PrimitiveMux with User-Defined Primitive

Behavior defined using a truth table that includes “don’t cares”

This is a less pessimistic than others: when a & b match, sel is ignored

(others produce X)

primitive mux(f, a, b, sel);output f;input a, b, sel;

table 1?0 : 1; 0?0 : 0; ?11 : 1; ?01 : 0; 11? : 1; 00? : 0;endtableendprimitive a

bsel

f



GLITCHES AND STATIC HAZARDSGLITCHES AND STATIC HAZARDS The output of a combinational circuit may make a transition even though the patt

erns applied at its inputs do not imply a change. These unwanted switiching transients are called "glitches."

Glitches are a consequence of the circuit structure and the application of patterns that cause the glitch to occur. A circuit in which a glitch may occur under the application of appropriate inputs signals is said to have a hazard.

A static 1-hazard occurs if an output has an initial value of 1, and an input pattern that does not imply an output transition causes the output to change to 0 and then return to 1.

A static 0-hazard occurs if an output has an initial value of 0, and an input pattern that does not imply an output transition causes the output to change to 1 and then return to 0.



STATIC HAZARDSSTATIC HAZARDS Static hazards are caused by differential propagation delays on reconve

rgent fanout paths.

Static hazards can be eliminated by introducing redundant cubes in the cover of the output expression (the added cubes are called a hazard cover).

For the hazard-free cover:F = AC + BC' + AB

A "minimal"realization:F = AC + BC'



DYNAMIC HAZARDS (Multiple glitches)DYNAMIC HAZARDS (Multiple glitches) A circuit has a dynamic hazard if an input transition is supposed

to cause a single transition in an output, but causes two or more transitions before reached its expected value.

Dynamic hazards are a consequence of multiple static hazards caused by multiply reconvergent paths in a multilevel circuit.

Dynamic hazards are not easy to eliminate. Elimination of all static hazards eliminates dynamic hazards. Approach: Transform a multilevel circuit into a two-level circuit a

nd eliminate all of the static hazards.



ExampleExample



STORAGE ELEMENTS: R-S LATCHSTORAGE ELEMENTS: R-S LATCH Storage elements are used to store information in a binary form

at (e.g. state, data, address, opcode, machine status). Storage elements may be clocked or unclocked. Two types: level-sensitive, edge-sensitive



STORAGE ELEMENTS: STORAGE ELEMENTS: TRANSPARENT LATCHESTRANSPARENT LATCHES

Latches are level-sensitive storage elements; data storage is dependent on the level (value ) of the input clock (or enable) signal. The output of a transparent latch changes in response to the data input while the latch is enabled. Changes at the input are visible at the output data



STORAGE ELEMENTS: FLIP-FLOPSSTORAGE ELEMENTS: FLIP-FLOPS Flip-flops are edge-sensitive storage elements; data storage is synchro

nized to an edge of a clock. The value of data stored depends on the data that is present at the data input(s) when the clock makes a transition at its active (rising or falling) edge.



MASTER-SLAVE FLIP-FLOPMASTER-SLAVE FLIP-FLOP

Documents

Digital IC Design Flow