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EE134 1

Digital Integrated Circuit (IC) Layout and Digital Integrated Circuit (IC) Layout and Design Design -- Week 4, Lecture 7Week 4, Lecture 7

! http://www.ee.ucr.edu/~rlake/EE134.html

EE134 2

ReadingReading

" Week 1 - Read Chapter 1 of text." Week 2 - Read Chapter 2 of text." Week 3 - Read Chapter 3 of text." Week 4 - Read Chapter 5 of text.

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EE134 3

ReviewReview" MOS Transistor (Ch. 3)

! Modes of Operation! Deep sub-micron MOS! Latch-up (finish up)

" Inverter (Ch. 5)! Voltage transfer curve (VTC)! Switching Point

NewNew

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CurrentCurrent--Voltage RelationsVoltage RelationsA good A good olol’’ TransistorTransistor

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

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EE134 5

Modes of Operation (Good Modes of Operation (Good olol’’ Transistor)Transistor)" Cutoff:

" Resistive or Linear:

" Saturation

VGS < VTID = 0

VDS < VGS - VT & VGS > VT

VDS > VGS - VTVGS > VT

( ) ( )DSTGSoxn

D VVVL

WCI λµ+−⋅⋅

⋅= 1

22

( ) ⎥⎦

⎤⎢⎣

⎡−⋅−⋅⋅⋅=

2

2DS

DSTGSoxnDVVVV

LWCI µ

EE134 6

A Model for Manual AnalysisA Model for Manual Analysis

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EE134 7

CurrentCurrent--Voltage RelationsVoltage RelationsThe DeepThe Deep--Submicron EraSubmicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D(A

)VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

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IIDD versus Vversus VDSDS

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EE134 9

Regions of Operation Regions of Operation -- SimplifiedSimplified

EE134 10

A Unified Model for Manual AnalysisA Unified Model for Manual Analysis

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EE134 11

Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS (V)

I D(A

)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

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Transistor Model Transistor Model for Manual Analysisfor Manual Analysis

I keep all signs positive for PMOS and use VSG, VSD, ISD.

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EE134 13

Ch. 5Ch. 5The CMOS Inverter: A First GlanceThe CMOS Inverter: A First Glance

Vin Vout

CL

VDD

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CMOS InverterCMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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EE134 15

Two InvertersTwo Inverters

Connect in Metal

Share power and ground

Abut cells

VDD

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CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin = VDD Vin = 0

VoutVout

Rn

Rp

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EE134 17

CMOS Inverter PropertiesCMOS Inverter Properties

" Full rail-to-rail voltage swing! VOH = VDD & VOL = 0

" Logic levels independent of transistor size! “Ratioless” logic

" Low output resistance (kΩ range)" High input resistance" No direct current path in steady state

(ignoring leakage)

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CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response

tpHL = f(Ron.CL)= 0.69 Rn CL

V outVout

R n

R p

V DDV DD

V in = V DDV in = 0

(a) Low-to-high (b) High-to-low

CLCL

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EE134

Voltage TransferVoltage TransferCharacteristicCharacteristic

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PMOS Load LinesPMOS Load Lines

VDSp

IDp

VGSp=-2.5

VGSp=-1VDSp

IDnVin=0

Vin=1.5

Vout

IDnVin=0

Vin=1.5

Vin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

Vout

IDnVin = VDD+VGSpIDn = - IDp

Vout = VDD+VDSp

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EE134 21

CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics

IDn

Vout

Vin = 2.5

Vin = 2

Vin = 1.5

Vin = 0

Vin = 0.5

Vin = 1

NMOS

Vin = 0

Vin = 0.5

Vin = 1Vin = 1.5

Vin = 2

Vin = 2.5

Vin = 1Vin = 1.5

PMOS

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CMOS Inverter VTCCMOS Inverter VTC

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS s atPMOS res

NMOS resPMOS sat

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EE134 23

Switching Threshold as a function of Switching Threshold as a function of Transistor RatioTransistor Ratio

100

101

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8M

V(V

)

W p/W

n

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Determining VDetermining VIHIH and Vand VILIL

VOH

VOL

Vin

Vout

VM

VIL VIH

A simplified approach

Vout

Vin0.5 1 1.5 2 2.5

0.5

11.

52

2.5

NMOS resPMOS off

NMOS satPMOS sat

NMOS offPMOS res

NMOS satPMOS res

NMOS resPMOS sat

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EE134 25

Inverter GainInverter Gain

0 0.5 1 1.5 2 2.5-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Vin (V)

gain

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Gain as a function of VDDGain as a function of VDD

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin (V)

Vou

t (V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

Vou

t(V)

Gain=-1

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EE134 27

Impact of Process VariationsImpact of Process Variations

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin (V)

V out(V

)Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal