Digital Manual

DIGITAL ELECTRONICS LAB

CYCLE 1

1. Verification of digital Logic gates

2. Verification of Boolean Theorems using Digital Logic Gates

3. Design and Implementation of Combinational Circuits using basic gates for arbitrary functions

4. Study of flip flops

5. Design and implementation of adders and subtractors using logic gates

6. Design and implementation of code converters using logic gates

1.BCD to excess-3 code and vice versa

2.binary to gray and vice versa

7. Design and implementation of 4 bit binary adder/subtractor and BCD adder

using IC 7483

CYCLE 2

8. Design and implementation of 2 bit magnitude comparator using logic gates 8 bit

magnitude comparator using IC 7485

9. Design and implementation of 16 bit odd/even parity checker generator using

IC 74180

10. Design and implementation of multiplexer and de multiplexer using logic gates and

study of IC 74150 and IC 74154

11. Design and implementation of encoder and decoder using logic gates and study of

IC 7445 and IC 74147

12. Construction and verification of 4 bit ripple counter and MOD -10/MOD-12 Ripple

counters

13. Design and implementation of 3-bit synchronous up/down counter

14. Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops

AUGMENTED EXPERIMENTS

1. Design and implementation of a synchronous counter using JK flip flop to

count the following sequence 7,4,3,1,5,0,7

2. To design and implement the given Boolean function using multiplexer

1. VERIFICATION OF DIGITAL LOGIC GATES

Aim:

To study the fundamental laws of Boolean algebra using AND, OR, NAND, NOR,

EXOR and NOT gates.

Equipments required:

Digital Trainer Kit

IC 7400 - NAND IC

IC 7402 - NOR IC

IC 7404 - NOT IC

IC 7408 - AND IC

IC 7432 - OR IC

IC 7486 - EXOR IC

Theory:

The elemental blocks in a logic device are called digital logic gates.

An AND gate has two or more inputs and a single output. The output of an AND

gate is true only if all the inputs are true.

An OR gate has two or more inputs and a single output. The output of an OR gate is

true if any one of the inputs is true and is false if all of the inputs are false.

An INVERTER has a single input and a single output terminal and can change a

true signal to a false signal, thus performing the NOT function.

An NAND gate has two or more inputs and a single output. The output of an

NAND gate is true if any one of the inputs is false and is false if all the inputs are true.

An NOR gate has two or more inputs and a single output. The output of an NOR

gate is true if all the inputs are false and is false if the inputs are different.

An EXCLUSIVE OR gate has two or more inputs and a single output. The output

of an EXCLUSIVE OR gate is true if the inputs are different and is false if the inputs are

the same.

Procedure: sthe power is off before you build anything.

1. Plug the chips you will be using into the breadboard. Point all the chips in the

same direction with pin 1 at the upper-left corner. (Pin1 is often identified by a

dot or a notch next to it on the chip package)

2. Connect +5V and GND pins of each chip to the power and ground bus strips on

the breadboard.

3. Connect the inputs of one of the gates to SW1 and SW2 (switches), and connect

the output of the gate to Logic Indicator A (an LED).

4. Turn power on.

5. Flip the switches and observe the LEDs to confirm that the chip works as it

should (for the switches, the up position is logic HIGH).

6. Test the possible combinations of inputs to verify the gate works as it should and

fill in the truth table.

7. Turn the power off.

8. Repeat the above steps for each of the remaining gates.

Result:

Thus the fundamental laws of Boolean algebra using AND, OR, NAND, NOR,

EXOR and NOT gates were studied.

Pin Diagrams:

AND GATE TRUTH TABLE

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

OR GATE TRUTH TABLE

NOT GATE TRUTH TABLE

EX-OR GATE TRUTH TABLE

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

A Y

0 1

1 0

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

NAND-GATE

NOR-GATE TRUTHTABLE

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

2. VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

Aim:

To study the fundamental theorems of Boolean algebra using logic gates


Digital Trainer kit

IC 7432 – OR IC

IC 7408 – AND IC

Procedure:

1. Design the circuit diagram using basic gates

2. Verify the truth table for both LHS & RHS of the following postulates and

theorems.

1. A+0=A

A.1=A

2. A+A’=1

A.A’=0

3. A+A=A

A.A=A

4. A+1=1

A.0=0

5. Involution

(A’)’=A

6. Commutative Law:

A+B=B+A

A.B=B.A

7. Associative Law:

A+(B+C) = (A+B)+C

A.(B.C) = (A.B).C

8. Distributive Law:

A.(B+C) = (A.B)+C

A+(B.C) = (A+B).(A+C)

9. DeMorgan’s theorem

(A+B)’=A’B’

(AB)’=A’+B’

10. Absorption Theorem

A+AB=A

A(A+B)=A

Result:

Thus the fundamental theorems of Boolean algebra were studied using logic gates

3. DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING

BASIC GATES FOR ARBITRARY FUNCTIONS

Aim:

To minimize and implement the Boolean functions by designing the combinational

circuits using logic gates

Equipments Required:

Digital Trainer Kit

IC 7400 - NAND IC

IC 7402 - NOR IC

IC 7404 – NOT IC

IC 7408 – AND IC

IC 7432 – OR IC

IC 7486 – EXOR IC

Theory:

Boolean algebra is an algebra that deals with binary variables and logic operations.

A Boolean function described by an algebraic expression consists of binary variables, the

constants 0 and 1, and the logic operation symbols. For a given value of binary variables,

the function can be equal to either 1 or 0. Consider as an example the following Boolean

function:

F = A + B’C

The function F is equal to 1 if A is equal to 1.or if both B’ and C are equal to 1. F is

equal to 0 otherwise. A Boolean function expresses the logical relationship between binary

variables. It is evaluated by determining the binary value of the expression for all the

possible values of the variables.

Gate implementation of F = A + B’ C

A Boolean function can be transformed from an algebraic expression into a circuit

diagram composed of logic gates. The logic circuit diagram for F is shown in the above

figure. There is an inverter for input B to generate the complement. There is an AND gate

for the term B’ C and an OR gate that combines the two terms. In logic-circuit diagrams,

the variables of the function are taken as the input of the circuit and the binary variable F is

taken as the output of the circuit.

Truth table for F = A + B’ C

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

A Boolean function can be represented in the truth table. A truth table is a list of

combinations of 1’s and 0’s assigned to the binary variables and a column that shows the

value of the function for each binary combination. The number of rows in the truth table is

2, where n is the number of variables in the function.

F

A

C

B

Procedure:

1. Design the circuit diagram

2. Draw the truth table for the given exercise problems using the above description.

3. Check the output.

Exercise:

1. Y=(A+B’+C’)(A+B’+C)

2. Y=A’B’C’+A’B’C+A’BC’+AB’C’+AB’C

Result:

Thus Boolean functions were implemented by designing the combinational circuits

using logic gates.

4. STUDY OF FLIP FLOPS USING ICS

Aim:

To study the characteristics of RS, JK, D and T flip flops using IC’s.


Digital trainer kit

IC 7476 – JK Flip Flop

Theory:

JK Flip Flop: A JK Flip Flop is a refinement of the RS Flip Flop in that the indeterminate

state of the RS type is defined in the JK type. Inputs J and K behave like S and R to set and

clear the flip-flops respectively. When both inputs J and K are equal to 1, the flip-flop

switches to its complement state that is the flip-flop toggles its output.

T Flip Flop: The T flip flop is a single input version of the JK flip-flop. The T flip-flop is

obtained from the JK flip-flop when both inputs are together. The designation T comes

from the ability of the flip-flop to toggle its state.

D Flip Flop: One way to eliminate the undesirable condition of the indeterminate state in

the RS flip flop is to ensure that inputs S and R are never equal to 1 at the same time. This

is done in D flip flop. The D input has only two inputs D and clk. If D=1 and clk=1 output

goes to 1 and if D=0 and clk =1 then output goes to 0.

Procedure:

1. Connect the circuit as shown in logic connections for JK, D and T Flip Flops.

2. Verify the truth table of all the Flip Flops.

Result:

Thus the characteristics of RS, JK, D and T flip flops using IC’s were studied.

Truth Table:

Pin details:

Logic connections:

4. ADDERS AND SUBTRACTORS

Aim:

To construct an adder and subtractor circuit using logic gates and to verify its truth

tables.


Digital Trainer kit

IC 7408 – AND IC

IC 7432 –OR IC

IC 7486 – EXOR IC

IC 7404 – NOT IC

Theory:

HALF ADDER:

A combinational circuit that performs the addition of two bits is called half adder. A

half adder circuit needs two binary inputs and binary outputs. The input variable designate

the augend and the addend bits. The output variables produce the sum and the carry.

The carry output is 0 unless both inputs are 1.The S output represents the least

significant bit of the sum.

The simplified Boolean functions for the two outputs can be obtained directly fro

the truth table.

S=X’Y+XY’

C=XY

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of three input

bis. It consists of three inputs and two outputs. The two outputs are designated by the

symbols S for sum and C for carry.

The binary variable S gives the value of the least significant bits of the sum. Binary

variable C gives the output carry.

When all inputs are 0,the output is 0.The S output is equal to 1 when only one input

is equal to 1.The c output has a carry of 1 if two or three inputs are equal to 1.

The simplified Boolean functions for the two outputs can be obtained directly from

the truth table.

S=X’YC’+X’YZ’+XY’Z’+XYZ

C=XY+XZ+YZ

HALF SUBTRACTOR:

A half subtractor is a combinational circuit that subtracts two bits and produces

their differences. A half subtractor needs two binary inputs and two binary outputs. The

input variable designate minuend and subtrahend bits. The output variables produce the

difference and borrow.

The simplified Boolean functions for the two outputs can be easily obtained directly

from the truth table.

D=X’Y+XY’

B=X’Y

FULL SUBTRACTOR:

A full subtractor is a combinational circuit that performs a subtraction between

three bits, 1 may have been borrowed by a lower significant bit. This circuit has three

inputs and 2 outputs. The three inputs a, b and c denote the minuend subtrahend and

previous borrow. The two outputs D and B represents the difference and output borrow.

The simplified Boolean functions for the two outputs can be obtained directly from the

truth table.

D= X’Y’Z+X’YZ’+XY’Z’+XYZ

B=X’Y+X’Z+YZ

Procedure:

1. The connections are given as per the circuit diagram

2. Verify the truth table

Result:

Thus an adder and subtractor circuit using logic gates were constructed and its truth

tables were verified.

CIRCUIT DIAGRAM:

HALF ADDER

FULL ADDER

HALF SUBTRACTOR

INPUT OUTPUT

X Y S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

INPUT OUTPUT

X Y Z S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1INPUT OUTPUT

X Y B D

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

S

C

X

Y

X

Y

Z X

Y

B

D

FULL SUBTRACTOR

INPUT OUTPUT

X Y Z B D

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

6. DESIGN AND IMPLEMENTATION OF CODE CONVERTERS USING LOGIC

GATES

Aim:

To design and implement a combinational circuit with four inputs and four outputs

that converts

1. a four bit binary number to a gray code number and vice versa.

2. a BCD to excess -3 and vice versa

X

Y

Z

B

D


Digital Trainer kit

IC 7486 - XOR IC

Theory:

Gray code belongs to a class of codes called minimum change codes in which only

one bit in the code group changes when going from one step to the next. It is also called

Mirror reflecting code. Gray code is a special purpose code and these codes are applied for

error detection and error correction. The conversion of gray code to binary code can be

electronically achieved by using EXOR gates

Excess3 code is the modified form of BCD number. The excess3 code can be

derived from the natural BCD code by adding 3 to each coded number. For hexadecimal 12

can e represented in BCD as 0001 0010.Now, adding decimal 3 represented in BCD as

0011 to each digit we get excess 3 code as 0100 0101(12 in decimal). With this

information, the truth table for BCD to excess 3 code converter can be determined as

shown in the tabulation.

Procedure:

1. Connect the circuit and verify the truth table.

Result:

Thus a combinational circuit with four inputs and four outputs was designed and

implemented that converts

1. a four bit binary number to a gray code number and vice versa.

2. a BCD to excess -3 and vice versa

TRUTH TABLE:

Conversion of gray code to binary

Decimal Gray

code

Binary

Code

ABCD WXYZ

0 0000 0000

1 0001 0001

2 0011 0010

3 0010 0011

4 0110 0100

5 0111 0101

6 0101 0110

7 0100 0111

8 1100 1000

9 1101 1001

10 1111 1010

11 1110 1011

12 1010 1100

13 1011 1101

14 1001 1110

15 1000 1111

Conversion of BCD to Excess 3

Decimal BCD EXCESS3

ABCD WXYZ

0 0000 0011

1 0001 0100

2 0010 0101

3 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 1010

8 1000 1011

9 1001 1100

CIRCUIT DIAGRAM:

BINARY TO GRAY

W X Y Z

A=W

B=WX’+W’X

C=XY’+X’Y

D=YZ’+Y’Z

GRAY TO BINARY

W=A

X=AB’+A’B

Y=XC’+C’X

Z=YD’+DY’

BCD TO EXCESS3

DCBA

A B C D

W X Y Z

A B C D

Z=D’

Y=CD+C’D’

X=B’C+B’D+BC’D’

W=A+BC+BD

y

z

x

w

EXCESS3 TO BCD

A=Z’

B=YZ+Y’Z’

C=X’Y’+XYZ+WYZ’

D=WYZ+WX

7. 4-BIT BINARY ADDER / SUBTRACTOR AND BCD ADDER

W X Y Z

A

B

C

D

Aim:To design and implement a 4-bit binary Adder / Subtractor and 4 bit BCD adder

using IC7483


Digital Trainer Kit

IC 7483 IC 7486-XOR IC

Theory:IC 7483 is a 4-bit binary parallel adder. The two 4-bit input binary numbers are A1

through A4 and B1 through B4. The 4-bit sum is obtained from S1 through S4. C0 is the

input carry and C4 is the output carry.

The subtraction of two binary numbers can be done by taking the 2’s complement

of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by

taking the 1’s complement and adding 1. To perform A – B, we complement the four bits

of B, add them to the four bits of A, and add 1 through the input carry. Four EXOR gates

complement the bits of B when the mode select M = 1 (because x 1 = x’) and leave the

bits of B unchanged when M = 0 (because x 0 = x). Thus when the mode select M = 1,

the input carry C0 is equal to 1 and the sum output is A plus the 2’s complement of B.

When M is equal to 0, the input carry is equal to 0 and the sum generates A + B.

The Procedure for BCD addition is as given below:

1. Add two BCD numbers using ordinary Binary addition.

2. If 4 bit sum is equal to or less than 9, no correction is needed. The sum is in proper BCD

form.

3. If the 4 bit sum is greater than 9 or if a carry is generated from the fourth bit sum, the

sum is invalid.

4. To correct the invalid sum add 0110 to the fourth bit sum. If a carry results from this

addition, add it to the next higher order BCD digit.

Thus to implement BCD adder we require

Four bit binary adder for initial addition

Logic circuit to detect sum greater than 9 and

One more 4 bit adder to add 0110 in the sum if the sum is greater than 9 or carry is

1.

Inputs OutputsS3 S2 S1 S0 Y0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1

0 0 0 0

0 0 0 0

1 1 1 1

0 0 1 1

Y=s3s2+s3s1Procedure:

1. Test the 4-bit binary adder 7483 by connecting the power supply and ground terminals.

2. Then connect the four A inputs to a fixed binary number such as 1001 and the B inputs

and the input carry to the five toggle switches.

3. Set the mode = 0 for 4 bit binary addition.

4. The five outputs are applied to indicator lamps.

S3S2

S1S0

00 01 11 10

00

01

11

10

5. Perform the addition of a few binary numbers and check that the output carry gives

proper values.

6. Repeat the steps with mode =1 for binary subtraction.

7. Also show that when A B, the subtraction operation gives the correct answer, A – B,

and the output carry C4 is equal to 1. But when A < B, the subtraction gives the 2’s

complement of B – A and the output carry is equal to 0.

Result:Thus a 4-bit binary Adder / Subtractor and a 4 bit BCD adder were designed and

implemented using IC 7483.

Pin Diagram:

IC 7483 4-BIT BINARY ADDER.

4- Bit Binary Adder

4 bit BCD adder

`

8. COMPARATOR

B3 B2 B1 B0 A3 A2 A1 A0

16 4 7 11 1 3 8 10 5

Cin

Cout

1314

15 2 6 9

16 4 7 11 1 3 8 10

0

S3 S2 S1 S0

Cout Cin

Output carry

4 bit Binary Adder

4 bit Binary Adder

15 2 6 9

1314

Vcc

Gnd12

Vcc

5

Aim:

To construct two 2 bit numbers using logic gates and compare two 8 bit numbers

using IC 7485


Digital Trainer kit-1

IC 7486-XOR IC

IC 7404-NOT IC

IC 7408-AND IC

IC 7485

THEORY:

The comparison of two numbers is an operation that determines if one number is

greater than, less than or equal to the other number. A magnitude comparator is a

combinational circuit that compares two numbers, A and B and determines their relative

magnitudes. The outcome of the comparison is specified by three binary variables that

indicate whether A>B, A=B, A<B.

For comparing two four bit numbers

A=A3A2A1A0

B=B3B2B1B0

The circuits should be implemented by the following Boolean function

A>B: A1B1’+A0B0’(A1B1+A1’B1’)

A<B: B1A1’+B0A0’(B1A1+B1’A1’)

A=B: (A1 XNOR B1) . (A0 XNOR B0)

Description of IC 7485:

The four bit magnitude comparators perform comparison of straight binary and

straight BCD codes. A magnitude comparator compares the magnitude, i.e. unsigned

binary, of two numbers.

The magnitude comparator compares two numbers. There are three outputs to

display if one number is equal, greater or smaller compared to the other. The two inputs

can be 4 bits long. Vcc has to be used to generate a logic one and ground to generate a logic

zero. The outputs are verified using LEDS. The comparator has to be used to test all the

three cases.

Procedure:

1. The connections are given as per the circuit diagram.

2. Verify the output.

3. Now give two 8 bit numbers as input to the two comparator ICs and verify the

output.

Result:

Thus two 2 bit numbers were compared using logic gates and two 8 bit numbers were

compared using IC 7485 .

.

CIRCUIT DIAGRAM:

TRUTH TABLE:

A>B

A<B

A=B

A1 A0 B1 B0 A>B A<B A=B

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 0 1 0

0 0 1 1 0 1 0

0 1 0 0 1 0 0

0 1 0 1 0 0 1

0 1 1 0 0 1 0

0 1 1 1 0 1 0

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 0 1

PIN DIAGRAM OF IC 7485:

FUNCTION TABLE OF IC7485:

Comparing

inputs

Cascading Inputs

I(A>B) I(A=B) I)\(A<B)

Outputs

A>B A=B A<B

A>B X X X 1 0 0

A=B 1 0 0 1 0 0

X 1 X 0 1 0

0 0 1 0 0 1

0 0 0 1 0 1

1 0 1 0 0 0

A<B X X X 0 0 1

8 BIT COMPARATOR USING 7485

IC7485

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

Vcc A3 B2 A2 A1 B1 A0 B0

B3 A<Bin A=Bin A>Bin A>Bout A=Bout A<Bout Gnd

MSB MSB LSB LSB

Input A Input B Input A InputB

Vcc Gnd Vcc Gnd

15 13 12 10 1 14 11 9 15 13 12 10 1 14 11 9

5 A>B

6 A=B

7 A<B

I(A>B) 2

I(A=B) 3

I(A<B) 4

I(A>B) 2

I(A=B) 3

I(A<B) 4

IC 7485(1)IC 7485(2)

5 A>B

6 A=B

7 A<B

A7 A6 A5 A4 B7 B6 B5 B4 A3 A2 A1 A0 B3 B2 B1 B0

5V

16 8 16 8

9. 4 BIT ODD / EVEN PARITY GENERATOR / CHECKER USING LOGIC GATES AND MSI DEVICES

Aim:To design, construct and test a circuit that checks and generates an even parity bit

and odd parity bit from four message bits using EX-OR gates and IC 74180

Equipment Required:

Digital Trainer Kit,

IC 7486 EXOR

Theory:

EX-OR functions are very useful in systems requiring error detection and correction

codes. A parity bit is used for the purpose of detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to make the number

of 1’s either odd or even. The message, including the parity bit, is transmitted and then

checked at the receiving end for errors. An error is detected if the checked parity does not

correspond with the one transmitted. The circuit that generates the parity bit in the

transmitter is called a Parity Generator. The circuit that checks the parity in the receiver is

called a Parity Checker.

Procedure:

Parity checker:

1. Draw the circuit diagram using EX-OR gates

2. Connect the circuit to four switches and one LED and check for proper

operation.( Output=0 means Even parity, and Output=1 means odd parity)

Parity Generator:

1. Draw the circuit diagram using EX-OR gates.

2. Connect the circuit to three switches and one LED and note down the output as

even parity. (Add one more EX-OR gate to generate odd parity bit)

Result:

Thus a circuit that checks and generates an even parity bit and odd parity bit from

four message bits using EX-OR gates was designed, constructed and tested using logic

gates.

Truth Table: (Even parity Generator)

Message bitsParity

BitX Y Z P0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1

Design:

1 1

1 1

P=X Y Z

Circuit Diagram:

Parity Generator: (Even Parity)

X

yz00 01 11 10

0

1

P = X Y Z

Truth Table: (Parity Checker)

4 bits Message ReceivedParity error check

X Y Z P C0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 0

Design:

1 1

1 1

1 1

1 1

C=X Y Z P

XY

ZP

00 01 11 10

00

01

11

10

PARITY CHECKER:

C=XYZP

Truth Table: (Odd parity Generator)

Message bitsParity

BitX Y Z P0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0

Design:

1 11

1

X

yz00 01 11 10

0

1

P=X Y ZCircuit Diagram:

Parity Generator: (Odd Parity)

P = X Y Z

Truth Table: (Parity Checker)

4 bits Message ReceivedParity error check

X Y Z P C0 0 0 0 10 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 10 1 1 0 10 1 1 1 01 0 0 0 01 0 0 1 11 0 1 0 11 0 1 1 01 1 0 0 11 1 0 1 01 1 1 0 01 1 1 1 1

Design:

1 1

1 1

1 1

1 1

C=X Y Z P

Circuit diagram for odd parity checker:

XY

ZP

00 01 11 10

00

01

11

10

10. MULTIPLEXER AND DE-MULTIPLEXER

Aim:

To construct the multiplexer and demultiplexer using logic gates and to study IC

74150 and IC 74154


1. Digital trainer kit

2. IC 7404 – NOT IC

3. IC 7408 – AND IC

4. IC 7432 – OR IC

Theory:

Multiplexer and Demultiplexer:

Multiplexer is a combinational circuit that selects binary information from one of

many input lines and directs it to a single output line. A multiplexer is also called as data

selector. Normally there are 2n input lines and n selection lines whose bit combinations

determine which input is selected.

In a 4 to 1 line multiplexer, each of four input lines I0 to I3 is applied to one input of

an AND gate. Selection lines S1 and S0 are decoded to select a particular AND gate. The

function table lists the input to output path for each possible bit combination of selection

lines.

To demonstrate the circuit operation consider the case when S1S0=10. The AND

gate associated with input I2 has two of its inputs equal to 1 and third input connected to I2.

The other three AND gates have at least one input equal to 0, which makes their output

equal to 0. The OR gate have at least one output is now equal to the value of I2, thus

providing path from the selected input to the output.

Demultiplexer is a circuit that receives information on a single line and transmits

this information on one of a possible 2n output lines. The selection of a specific output line

is controlled by the bit values of n selection lines.

Procedure:

1. The connections are given as per the circuit diagram.

2. The function table is verified for multiplexer and demultiplexer.

3. Give the inputs to IC 74150 and IC 74147 as shown in the pin diagram and verify

the outputs.

Result:

Thus multiplexer and demultiplexer was constructed using logic gates and IC 74150

and IC 74154 were studied.

Circuit Diagram:

IC 74150 as MULTIPLEXER

INPUTS OUTPUTSA3 A2 A1 A0 En Q’X X X X 1 10 0 0 0 1 D0’0 0 0 1 0 D1’0 0 1 0 0 D2’0 0 1 1 0 D3’0 1 0 0 0 D4’0 1 0 1 0 D5’0 1 1 0 0 D6’0 1 1 1 0 D7’1 0 0 0 0 D8’1 0 0 1 0 D9’1 0 1 0 0 D10’1 0 1 1 0 D11’1 1 0 0 0 D12’1 1 0 1 0 D13’1 1 1 0 0 D14’1 1 1 1 0 D15’

IC 74154 as Demultiplexer

INPUTS OUTPUTSA3 A2 A1 A0 En1’ En2’ Q=0X X X X 1 X ------X X X 0 X 1 ------

0 0 0 0 0 0 Q00 0 0 1 0 0 Q10 0 1 0 0 0 Q20 0 1 1 0 0 Q30 1 0 0 0 0 Q40 1 0 1 0 0 Q50 1 1 0 0 0 Q60 1 1 1 0 0 Q71 0 0 0 0 0 Q81 0 0 1 0 0 Q91 0 1 0 0 0 Q101 0 1 1 0 0 Q111 1 0 0 0 0 Q121 1 0 1 0 0 Q131 1 1 0 0 0 Q141 1 1 1 0 0 Q15

11. DECIMAL TO BCD ENCODER & BCD TO DECIMAL DECODER

Aim:

To design and implement a Decimal to BCD Encoder and BCD to Decimal

Decoder using logic gates and to study IC 7445 and IC 74147 as Decoder and encoder

respectively.


Digital Trainer kit

IC 7404-NOT IC

IC 7420/7421-4 input NAND IC

IC 7432-OR IC

Theory:

ENCODER: An encoder provides binary coded outputs from an input selected from given

number of inputs. It has 2 power n in put lines and n output lines. Decimal to BCD encoder

is also known as keyboard encoder. Using this device the decimal digits can be converted

into equivalent BCD codes.

If two or more inputs are equal to one simultaneously, then the input having highest

priority will take precedence. This can be done using priority encoder. The encoder

provides BCD output, which will correspond to the highest order digit.

This type of encoders are typically used for translating a decimal keyboard

(calculator) into a binary or BCD codes.

DECODER:A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of 2n unique output lines. BCD to decimal decoder is also called

as 1 of 10 decoders, as only one of 10 output lines is high or low at a time.

Procedure:

1. Connections are given as shown in the diagram

2. Truth table is verified for all the input combinations of both Encoder and

Decoder.

3. Verify the truth tables for IC 7445 and 74147.

Result:

Thus Decimal to BCD Encoder and BCD to Decimal Decoder was constructed

using logic gates and the IC’s 7445 and 74147 were studied.

Pin diagram of IC 7420:

Truth table of IC7420:

INPUT OUTPUT

A B C D Q

0 0 0 0 1

0 1 1 1 1

1 0 1 1 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Circuit Diagram:

IC 7445 as BCD to DECIMAL Decoder:

IC 74147 as Decimal to BCD encoder

12. ASYNCHRONOUS COUNTERAim:

To design and implement an Asynchronous counter & to verify its truth table.


Digital Trainer kit

74LS76

Theory:

The external clock is connected to the clock input of the first flip-flop (FF0) only.

So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when

triggered by the falling edge of the Q output of FF0. Because of the inherent propagation

delay through a flip-flop, the transition of the input clock pulse and a transition of the Q

output of FF0 can never occur at exactly the same time. Therefore, the flip-flops cannot be

triggered simultaneously, producing an asynchronous operation.

Usually, all the CLEAR inputs are connected together, so that a single pulse can

clear all the flip-flops before counting starts. The clock pulse fed into FF0 is rippled

through the other counters after propagation delays, like a ripple on water, hence the name

Ripple Counter.

The 3-bit ripple counter circuit above has four different states, each one

corresponding to a count value. Similarly, a counter with n flip-flops can have 2n states.

The number of states in a counter is known as its mod (modulo) number. Thus a 2-bit

counter is a mod-8 counter.

A mod-n counter may also described as a divide-by-n counter. This is because the

most significant flip-flop (the farthest flip-flop from the original clock pulse) produces one

pulse for every n pulses at the clock input of the least significant flip-flop (the one triggers

by the clock pulse). Thus, the above counter is an example of a divide-by-8 counter.

Procedure:

1. Give the connections as per the circuit diagram

2. Verify the Truth Table.

Result:

Thus an asynchronous counter was designed and implemented & its truth table was

verified.

Pin Diagram:

Truth table for 4 bit ripple counter:

FF3 FF2 FF1 FF00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 11 1 1 1

Truth Table for MOD-10 counter:

FF3 FF2 FF1 FF00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1

Truth Table for MOD-12 counter:

FF3 FF2 FF1 FF00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 1

Circuit Diagram:

4 bit ripple counter

MOD-10 counter

MOD-12 Counter

13. SYNCHRONOUS UP/DOWN COUNTER

Aim:

To design and implement a synchronous counter for the given state diagram using

JK Flip Flop.


Digital trainer kit

IC 7476

Theory:

A sequential circuit that goes through a prescribed sequence of states upon the

application of input pulses is called a counter. A counter that follows the binary sequence is

called a binary counter. An n-bit binary counter consists of n flip-flops and can count in

binary from 0 to 2n - 1.

In synchronous counters, the clock inputs of all the flip-flops are connected together

and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously

(in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0

are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the

J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs

of FF0 and FF1.

The most important advantage of synchronous counters is that there is no

cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum

operating frequency for this counter will be significantly higher than for the corresponding

ripple counter.

Procedure:


2. Verify the truth table.

Result:

Thus a synchronous counter was designed and implemented for the given state

diagram using JK Flip Flop.

Pin diagram :

FLIP FLOP EXCITATION TABLE

Q(t) Q(t+1) J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

Excitation table for up counter :

Present State Next State Flip flop inputsQ2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K00 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 0 0 X 1 X X 10 1 0 0 1 1 0 X X 0 1 X0 1 1 1 0 0 1 X X 1 X 11 0 0 1 0 1 X 0 0 X 1 X1 0 1 1 1 0 X 0 1 X X 11 1 0 1 1 1 X 0 X 0 1 X1 1 1 0 0 0 X 1 X 1 X 1

K maps for up counter:

J2=Q1Q0

K2=Q1Q0

J1=Q0

K1=Q0

J0=1

K0=1

Excitation table for down counter :

0 0 1 0X X X X

X X X X0 0 1 0

0 1 X X0 1 X X

X X 1 0X X 1 0

1 X X 11 X X 1

X 1 1 XX 1 1 X

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Present State Next State Flip flop inputsQ2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K00 0 0 1 1 1 1 X 1 X 1 X0 0 1 0 0 0 0 X 0 X X 10 1 0 0 0 1 0 X X 1 1 X0 1 1 0 1 0 0 X X 0 X 11 0 0 0 1 1 X 1 1 X 1 X1 0 1 1 0 0 X 0 0 X X 11 1 0 1 0 1 X 0 X 1 1 X1 1 1 1 1 0 X 0 X 0 X 1

K MAPS for Down counter:

J2=Q1’Q0’

K2=Q1’Q0’

J1=Q0’

K1=Q0’

J0=1

K0=1

1 0 0 0X X X X

X X X X1 0 0 0

1 0 X X1 0 X X

X X 0 1X X 0 1

1 X X 11 X X 1

X 1 1 XX 1 1 X

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Circuit Diagram:

3 bit up down counter

14. SHIFT REGISTER

Aim:

To construct and verify the truth table of following shift register for 4 bit using D

Flip Flop

1. Serial In Serial Out

2. Serial In Parallel Out

3. Parallel In Parallel Out

4. Parallel In Serial Out.


Digital Trainer kit

IC 7474

Theory:

Shift registers are a type of sequential logic circuit, mainly for storage of digital

data. They are a group of flip-flops connected in a chain so that the output from one flip-

flop becomes the input of the next flip-flop. Most of the registers possess no characteristic

internal sequence of states. All the flip-flops are driven by a common clock, and all are set

or reset simultaneously.

Serial In - Serial Out Shift Registers

The register is first cleared, forcing all four outputs to zero. The input data is then

applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock

pulse, one bit is transmitted from left to right.

Serial In - Parallel Out Shift Registers

For this kind of register, data bits are entered serially in the same manner as

discussed in the last section. The difference is the way in which the data bits are taken out

of the register. Once the data are stored, each bit appears on its respective output line, and

all bits are available simultaneously

Parallel In - Serial Out Shift Registers

The circuit uses D flip-flops and NAND gates for entering data (ie writing) to the

register. D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and

D3 is the least significant bit. To write data in, the mode control line is taken to LOW and

the data is clocked in. The data can be shifted when the mode control line is HIGH as

SHIFT is active high.

Parallel In - Parallel Out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the parallel

outputs immediately following the simultaneous entry of the data bits. The D's are the

parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data

at the D inputs appear at the corresponding Q outputs simultaneously.

Procedure:

1. The connections are given as per the circuit diagram


Result:

Thus a shift register was constructed using D Flip Flop and its truth table was

verified.

Pin diagram: Dual D Flip Flop

Circuit Diagram:

Serial in - Serial Out Shift Registers:

Serial In - Parallel Out Shift Registers:

Parallel In - Serial Out Shift Registers:

Parallel in Parallel out Shift registers: - Parallel Out Shift Registers

Truth Table:

Serial In Serial Out S.No Control Inputs Input Output Conditions

Rd1 Rd2 Rd3 Sd1 Sd2 Sd3 CLK D1 D2 D3 Q3

1 0 0 0 1 1 1 ↑ × 0 clear

2

1 1 1 1 1 1 ↑ a1 0

After clear Input - Shift Left

1 1 1 1 1 1 ↑ a2 0

1 1 1 1 1 1 ↑ a3 a1

1 1 1 1 1 1 ↑ a4 a2

3 1 1 1 0 0 0 ↑ b1 b2 b3 0After clear Input -

Load

4

1 1 1 1 1 1 ↑ c1 b3

After Load - Shift Left

1 1 1 1 1 1 ↑ c2 b2

1 1 1 1 1 1 ↑ c3 b1

Serial In Parallel Out

S.No Control Inputs Input Output Conditions Rd1 Rd2 Rd3 Sd1 Sd2 Sd3 CLK D1 D2 D3 Q1 Q2 Q3

1 0 0 0 1 1 1 ↑ × × × 0 0 0 clear

2

1 1 1 1 1 1 ↑ a1 a1 0 0

After clear Input

1 1 1 1 1 1 ↑ a2 a2 a1 0

1 1 1 1 1 1 ↑ a3 a3 a2 a1

1 1 1 1 1 1 ↑ a4 a4 a3 a2

Parallel In Parallel Out

S.No Control Inputs Input Output Conditions Rd1 Rd2 Rd3 Sd1 Sd2 Sd3 CLK D1 D2 D3 Q1 Q2 Q3

1 0 0 0 1 1 1 ↑ × × × 0 0 0 clear

2 1 1 1 1 1 1 ↑ a1 a2 a3 a1 a2 a3 after clear input

3 1 1 1 0 0 0 ↑ b1 b2 b3 0 0 0after clear input

- Load

4 1 1 1 1 1 1 ↑ b1 b2 b3 after Load

Parallel In Serial Out

S.No Control Inputs Input Output Conditions

Rd1 Rd2 Rd3 Sd1 Sd2 Sd3

Write /

Shift CLK D1 D2 D3 Q3

1 0 0 0 1 1 1 ↑ × × × 0 clear

2 1 1 1 1 1 1 0 ↑ a1 a2 a3 × Write

3

1 1 1 0 0 0 1 ↑ a1 a1 a2 a3 after Write - shift1 1 1 1 1 1 1 ↑ a1 a1 a1 a2

15. NON-SEQUENTIAL COUNTERS

Aim:

To design asynchronous counter using JK flip flop to count the following sequence

7,4,3,1,5,0,7


Digital trainer kit

IC 7476

Theory:

A sequential circuit that goes through a prescribed sequence of states upon the

application of input pulses is called a counter. The counters either count up or down

continuously. Even in lessened modulus counters count is sequential but reset is enabled in

the middle of the sequence. But designing a counter which skips states in the middle is also

possible. Such a counter is called the non sequential counting.

Procedure:



Result:

Thus a synchronous counter with non sequential counting was designed and

implemented for the given state diagram using JK Flip Flop.

Pin diagram :

FLIP FLOP EXCITATION TABLE

Q(t) Q(t+1) J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

Excitation table of the non sequential counter:

Present State Next State Flip flop inputsQ2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K01 1 1 1 0 0 X 0 X 1 X 11 0 0 0 1 1 X 1 1 X 1 X0 1 1 0 0 1 0 X X 1 X 00 0 1 1 0 1 1 X 0 X X 01 0 1 0 0 0 X 1 0 X X 10 0 0 1 1 1 1 X 1 X 1 X

K maps for non-sequential counter:

J2=Q1’

K2=Q1’

J1=Q2’

K1=1

J0=1

K0=Q2

Circuit Diagram:

1 1 0 XX X X X

X X X X1 1 0 X

1 0 X X1 0 X X

X X 1 XX X 1 X

1 X X X1 X X X

X 0 0 XX 1 1 X

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’ Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q2’Q2

Q2’Q2

Q2’Q2

Q2’Q2

Q2’Q2

Q2’Q2

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

Q1’Q0’ Q1’Q0 Q1Q0 Q1Q0’

16. DESIGN AND IMPLEMENTATION OF BOOLEAN FUNCTION USING

MULTIPLEXER

Aim:

To design and implement the given Boolean function using multiplexer

1. F=C’B’A+C’BA+CB’A+CBA’

2.F=D’C’B’A+D’C’BA’+D’CB’A+D’CBA’+D’CBA+DC’B’A’+DC’

BA’+DCB’A’+ DCB’A+DCBA


Digital Trainer kit

IC 74151- Multiplexer IC

Theory:

A multiplexer is a combinational circuit that selects binary information from one of

many input lines and directs it to a single output line. For this reason it is also called a data

selector. The selection of particular input line and n selection lines whose bit combinations

determine which input is selected.

A 4-to-1 line multiplexer circuit has four data input lines, one output line, and 2

selection lines S. Each of the four inputs, Io through I3, is applied to one input of AND

gate. The output of AND gates are applied to a single OR gate that provides the one line

output. The function table lists the input that is passed to the output for each combination of

binary selection values. To demonstrate the circuit operation consider the case when S1So

=10. The AND gate associated with input I2 has two of its inputs equal 1 and the third input

connected to I2. The other three AND gates have at least one input equal to 0, which makes

their outputs equal to 0. The OR gate output is now equal to the value of I2, providing a path

from selected input to the output.

Procedure:

1. If there are n variables, connect n-1 variables to the selection line of multiplexer.

2. Construct the block diagram of multiplexer with 2n-1 inputs, n-1 selection lines and one

output.

3. Write the truth table for the function with n variables.

4. Construct an implementation table with possible combinations of the remaining single

variable as rows and the 2n-1 inputs as columns.

5. Fill up the min terms as shown in the table and choose, the min terms with 1 as output

and encircle them

6. a) If none of the min-terms in the column are chosen. The input is 0.

b) If both of the min-terms in the column are chosen. The input is 1.

c) If any one is chosen, the variable in the row is the input.

Result:

Thus the given Boolean function was designed and implemented using multiplexer

Pin diagram:

F=C’B’A+C’BA+CB’A+CBA’Truth table:

Circuit Diagram:

Input Output

C B A Y0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0

F=D’C’B’A+D’C’BA’+D’CB’A+D’CBA’+D’CBA+DC’B’A’+DC’BA’+DCB’A’+ DCB’A+DCBA

Truth table:

Implementation Table:

Input OutputD C B A Y0 0 0 0 00 0 0 1 10 0 1 0 10 0 1 1 00 1 0 0 00 1 0 1 10 1 1 0 10 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 11 1 0 1 11 1 1 0 01 1 1 1 1

Circuit diagram:

CONTENTS

S.No. Name of the Experiments Page No.

1 Verification of digital Logic gates

2 Verification of Boolean Theorems using Digital Logic Gates

3 Design and Implementation of Combinational Circuits using basic gates for arbitrary functions

4 Study of flip flops

5 Design and implementation of adders and subtractors using logic gates

6

Design and implementation of code converters using logic gates

1.BCD to excess-3 code and vice versa 2.binary to gray and vice versa

7 Design and implementation of 4 bit binary adder/subtractor and BCD adder using IC 7483

8Design and implementation of 2 bit magnitude comparator using logic gates 8 bit magnitude comparator using IC 7485

9 Design and implementation of 16 bit odd/even parity checker generator using IC 74180

10Design and implementation of multiplexer and

demultiplexer using logic gates and study of IC 74150 and IC 74154

11 Design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147

12 Construction and verification of 4 bit ripple counter and MOD -10/MOD-12 Ripple counters

13 Design and implementation of 3-bit synchronous up/down counter

14 Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops

15Design and implementation of a synchronous counter using JK flip flop to count the following sequence 7,4,3,1,5,0,7

16 To design and implement the given Boolean function using multiplexer

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