DIGITAL SIGNAL PROCESSING IVhome.mweb.co.za/rf/rfitch/eidsv4/DsvStGds.pdf · Learning Guide – Digital Signal Processing IV iv i) Module assessment: To successfully complete each

VUT Vaal University of Technology

DIGITAL SIGNAL PROCESSING IV

Learning Guide First Semester 2018

Module Code: EIDSV4A

Learning Guide – Digital Signal Processing IV ii

INDEX PART I Module Information 1. Word of welcome ……………..………………………….….……………… iii 2. Contact persons …………………………………………………………….. iii 3. Rationale for the module ……...……………………………………………. iii 4. Prerequisites ………………………………………………………………… iii 5. Learning material and reference textbooks .………………………………… iii 6. Assessment ……………………………………………………………...….. iii 7. Icons used in this study guide .…….………………………………...……... v PART II Learning Units

Unit 1

1. Chapter 1 – Discrete Systems and Signals .……………………….…….…… 1-1 2. Chapter 2 – Time Domain Analysis …………………...…………….…....…. 2-1 3. Chapter 3 – Z Transform ………………..…………………...…………....…. 3-1 Unit 2

4. Chapter 4 – Frequency Domain Analysis …...….…………...…………......... 4-1 5. Chapter 5 – Discrete Fourier Transform …...………...……...…………....…. 5-1 6. Chapter 6 – Digital Filters ……...……………………...……….………....…. 6-1 Unit 3

7. Project 7.1 Project outcome ……..……………...…………………….....…...…… 7-1 7.2 Project schedule ……….………………...….……………………...…. 7-1 7.3 Assessment …………...………..……………..……..………………… 7-10

Learning Guide – Digital Signal Processing IV iii

1. WORD OF WELCOME The Department of Process Control and Computer Systems welcomes you as a student to the Faculty of Engineering at the Vaal University of Technology. The department strives towards integration of existing knowledge with new knowledge and to afford the student the ability to think logically, gain knowledge of Electrical Engineering, and specifically Digital Signal Processing, in order to make a positive contribution to the field of Industrial Instrumentation and Electrical Engineering, once you have completed your studies.

2. CONTACT PERSONS

Title and Surname Office Telephone number and e-mail address Prof MO Ohanga (HOD) R007 016 950 9323 [email protected] Ms. R Mwale (Administrator) R007 016 950 9254 [email protected] Mr. TV Maloka (Lecturer) S113 016 950 9433 [email protected]

3. RATIONALE FOR THE MODULE On completion of this module you should be knowledgeable in the basic concepts underlying linear discrete-time systems, sampling of analogue signals, difference equations, convolution summation, z-transform, frequency response, digital Fourier transform techniques and digital filters.

4. PREREQUISITES The z transform as well as complex algebra, are used extensively in this course. It is therefore strongly recommended that students successfully complete the courses in Control Systems III (EIBEH III) and Mathematics II (AMISK II), before commencing with their studies in Digital Signal Processing IV.

5. LEARNING MATERIAL AND REFERENCE TEXTBOOKS This learning guide as well as the course material and previous evaluations, will be made available to students at the beginning of the semester. Additional reference textbooks: a) Lynn, P.A. and Fuerst, W., Introductory Digital Signal Processing

withComputer Applications. b) Mayhan, R.J., Discrete-Time and Continuous Linear Systems. c) Oppenheim A.V. and Schafer R.W., Digital Signal Processing. Additional information may be available from: http://home.mweb.co.za/rf/rfitch The lecturer will not respond to email from students.

6. ASSESSMENT Module assessment will take place on a continuous basis, and for this purpose the module is divided into three units.

Unit 1: Chapters 1 to 3 (weight = 40%) Unit 2: Chapters 4 to 6 (weight = 40%) Unit 3: Project (weight = 20%)

Learning Guide – Digital Signal Processing IV iv

i) Module assessment: To successfully complete each unit, students must receive a unit mark of at least 50%. To successfully complete the module, students must complete all the units. A student that successfully completes the module will receive a module mark according to the following summative assessment schedule:

Module% = 0.4Unit1% + 0.4unit2% + 0.2unit3%

The continuous assessment programme does not allow for supplementary or rewritten examinations. Students that fail to complete this module, must resume their studies by completing all units again during a subsequent semester.

ii) Unit 1 assessment (1½ hour session): Assessment of unit 1 is scheduled for

Thursday 1 March 2018 at 10h00. Students that fail to receive 50% for unit 1, will be offered a second and final opportunity to complete unit 1 on Thursday 10 May 2018 at 10h00. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 1. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 1. A student that fails to receive 50% for the final attempt to complete unit 1, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus.

iii) Unit 2 assessment (1½ hour session): Assessment of unit 2 is scheduled for

Thursday 29 March 2018 at 10h00. Students that fail to receive 50% for unit 2, will be offered a second and final opportunity to complete unit 2 on Thursday 10 May 2018 at 11h35. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 2. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 2. A student that fails to receive 50% for the final attempt to complete unit 2, fails the module. The assessment venue is lecture room S205 (main campus), and as arranged at the Secunda campus.

ivi) Unit 3 assessment: For the purpose of assessing unit 3 (project), each student

will prepare and demonstrate a Finite Impulse Response digital filter of length three, constructed according to the guidelines given in the learner guide for unit 3. A clear photograph showing the project with the student’s student card (or other clear identification), must also be available for assessment and moderation. Assessment of unit 3 is scheduled for Thursday 19 April 2018 at 10h00. Students that fail to receive 50% for unit 3, will be offered a second and final opportunity to complete unit 3 on Thursday 26 April 2018 at 10h00. Students who successfully complete the final assessment, will however receive a maximum mark of 50% for unit 3. Students who were unable to attend the first assessment session, will receive the full mark obtained for the final assessment of unit 3. A student that fails to receive 50% for the final attempt to complete unit 3, fails the module. The assessment venue is the lecture room, S205.

Learning Guide – Digital Signal Processing IV v

v) Module Portfolio: Students will not be required to assemble a module portfolio individually. The lecturer, however, will assemble a module portfolio that will include all question papers and memoranda, as well as the study guide, mark sheets and class registers. The examination office currently archives all examination scripts in order to be available as assessment evidence for unit 1 and unit 2. Lecturers should include each student’s project photograph in the module portfolio, as assessment evidence for unit 3. The module portfolio must be safeguarded for at least three years for moderation purposes.

7. ICONS USED IN THIS STUDY GUIDE

1

2

3

4

5

6

Estimated study time

Opening remarks and introduction

Outcomes Study the following passage thoroughly

Practical work

Exam questions and assessment

7.

Section still under construction

EIDSV4 Discrete Systems and signals Learning Guide Unit 1

1-1

1. LEARNING GUIDE - UNIT 1: DISCRETE SYSTEMS AND SIGNALS

The objective of this learning unit is to introduce students to the fundamental properties of discrete systems and signals.

You should spend approximately 10 hours on this learning unit.

LEARNING UNIT OUTCOME

After completion of this learning unit, students should be able to:

Define Shannon’s sampling theorem. Define the impulse and step function. Sketch and perform elementary algebraic operations with discrete

signals. Construct difference equations and block diagrams for discrete

systems. Determine the response of linear, time invariant system to various

inputs.

EIDSV4 Time Domain Analysis Learning Guide Unit 1

2-1

2. LEARNING GUIDE – UNIT 1: TIME DOMAIN ANALYSIS

The objective of this learning unit is to introduce students to the analysis of discrete systems in the time domain, using the principle of the convolution sum.




Describe digital signals in terms of impulse functions. Determine the impulse response of a discrete system. Use the convolution method to calculate the response of a discrete

system for typical input signals.

EIDSV4 Frequency Domain Analysis Learning Guide Unit 1

3-1

3. LEARNING GUIDE – UNIT 1: Z TRANSFORM

The objective of this learning unit is to introduce students to the powerful z transform method to analyze discrete systems in the frequency domain.




Define the z transform X(z). Verify the important properties of the z transform. Determine the z transform X(z) for time functions x(k). Use the method of long division and partial fractions to find the

inverse z transform of X(z).

EIDSV4 Frequency Domain Analysis Learning Guide Unit 2

4-1

4. LEARNING GUIDE – UNIT 2: FREQUENCY DOMAIN ANALYSIS

The objective of this learning unit is to introduce students to the response of discrete systems to sinusoidal input signals. You should spend approximately 10 hours on this learning unit.



Relate the transient response of a system to the roots of the denominator of the system function H(z).

Determine the frequency response of the system H(), from H(z).

EIDSV4 Discrete Fourier Transform Learning Guide Unit 2

5-1

5. LEARNING GUIDE – UNIT 2: DISCRETE FOURIER TRANSFORM

The objective of this learning unit is to introduce students to the discrete Fourier transform as an instrument for finding the frequency spectrum of discrete signals,




Determine the frequency spectrum of non periodic signals. Determine the frequency spectrum of periodic signals.

EIDSV4 Digital Filters Learning Guide Unit 2

6-1

6. LEARNING GUIDE – UNIT 2: DIGITAL FILTERS

The objective of this learning unit is to introduce students to some of the important techniques used when designing digital filters. You should spend approximately 20 hours on this learning unit.



Design finite impulse response filters. Design infinite impulse response filters.

EIDSV4 Project Learning Guide Unit 3

7-1

7. LEARNING GUIDE – UNIT 3: PROJECT – LOW PASS FIR FILTER

The objective of this learning unit is to give students the opportunity to design a Finite Impulse Response filter of length three, and to use the filter to recover the fundamental frequency from a rectangular input signal.


7.1 Project Outcome After completion of this project, students will be able to demonstrate the operation of a low pass FIR structure, filtering the fundamental frequency from a rectangular input signal.

7.2 Project Schedule To complete this project, students will be required to construct a FIR low pass filter of length three with cut off frequency c of 1 rad/sec. A pulse generator will provide the input signal of 1 rad/sec, and the filter must extract the fundamental harmonic from this input. Both the input signal and the output signal will be displayed by means of LED’s. A block diagram of the system is shown in Figure P1.

x(t) y(k)

Pulse generatorLow passFIR filter

LED display LED display

Figure P1


7-2

7.2.1 Filter design guide For simplicity, a filter of length N = 3 will be constructed. The impulse response of a low pass FIR filter is given by:

h(k) =

c

T sin(k - ) c T

(k - ) c T. Equation P1

We will use a sampling frequency s = 10 r/s and cut-off frequency c = 1 r/s. (which is also the frequency of the input square wave). Therefore c = 0.1s. With T = 2/s, N = 3, = (N-1)/2 = 1 and using Equation P1, we find for h(k):

h(k) = )]/)(21)(0-[(k

)]/)(21)(0-sin[(k)/(2s0

ss

sss

h(k) = )]1)(0.2-[(k

)]1)(0.2-sin[(k0.2

, for k = 0, 1 and 2. Equation P2

From Equation P2, h(0) = 0.1871, h(1) = 0.2 and h(2) = 0.1871. To simplify the electronics and to amplify the output signal somewhat, we will assume h(0) = h(1) = h(2) = 0,25. The final structure is shown in Figure P2. The transfer function of the filter is given by:

H(z) = 0.25 + 0.25z-1 + 0.25z-2. Equation P3

Because of the low order of the filter (N = 3), the cut-off characteristics of this filter is not very good. Nevertheless, using a sampling frequency s = 10 r/s (fs = 1.5915 Hz.) which is ten times the cut-off frequency c = 1 r/s (fc = 0.15915 Hz.), will result in the attenuation of the third harmonic (=3), fifth harmonic (=5) and seventh harmonic (=7) frequencies contained in the input signal. Given that the sampling period T = 1/fs = 1/1.5915 = 0.6283 sec, the frequency response of the filter, |H(ejT)|, may be calculated. From Equation P3: H(ejT) = 0.25 + 0.25e-jT + 0.25e-j2T H(ej0.6281) = 0.25 + 0.25e-j0.6281 + 0.25e-j1.256 = 0.25[1 + 1-0.6283 + 1-1.2566]

The values of H(ejT), also just denoted by H(), for = 0 to 10, are tabulated in Figure P3. A graph of the frequency response |H()| is also shown.

0.25

x(k)

y(k) x(k-1)

x(k-2)

z-1

z-1

0.25

0.25

+

Figure P2


7-3

The network shown in Figure P4 will be used to implement this filter.

x(t)

v

100k

100k

100k

100k

y(k)

x(k-2) x(k-1)x(k)

CP0

Start of next sampling period Start of sampling period

CP2CP1CP0CP2 CP1 CP0

-

+

-

+

-

+

C2 C1 C0

|H()|

(rad/sec.) H() |H()|

0 0.750 0.75 1 0.6545-0.6283 0.6545 2 0.4045-1.2566 0.4045 3 0.0955-1.8849 0.0955 4 0.15450.6284 0.1545 5 0.250 0.25 6 0.1545-0.6282 0.1545 7 0.09541.8851 0.0954 8 0.40441.2568 0.4044 9 0.65450.6284 0.6545 10 0.750 0.75

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 1 2 3 4 5

0.9

1Ideal

c s/2Figure P3

S0

CP2

S1

CP1

S2

CP0

Sampling period = 0.6283 sec Next sampling period

Figure P4

-

+

MAC

x(t)

The bucket brigade x(k) x(k-1) x(k-2)


7-4

Capacitor C0 is used to store the most recent sample x(k) obtained from the input signal. Capacitor C1 is used to store the previous value x(k-1) of the input signal while capacitor C2 stores the oldest sample x(k-2). At the start of each sampling interval, all the stored values are shifted one position to the right. First, clock pulse CP0 closes switch S2 and transfers the stored value on C1, to C2 (which is the value of x(k-2) during this sampling interval). Next clock pulse CP1 closes switch S1 and transfers the stored value on C0 to C1 (which is the value of x(k-1) during this sampling period). Finally clock pulse CP3 operates switch S0 and sample the current value x(k) of the input signal. The filter output y(k) is calculated by means of the MAC operational amplifier. From Figure P4, y(k) is equal to v, the voltage at the positive input of the MAC operational amplifier that is connected in voltage follower mode. Applying Kirchoff’s current law at the v node:

[x(k)-v]/100k + [x(k-1)-v]/100k + [x(k-2)-v]/100k = v/100k [x(k)-v] + [x(k-1)-v] + [x(k-2)-v] = v 4v = x(k) + x(k-1) + x(k-2) v = ¼x(k) + ¼x(k-1) + ¼x(k-2) But y(k) = v, y(k) = ¼x(k) + ¼x(k-1) + ¼x(k-2).

This is the required filter response for our low pass filter. Strictly speaking, we should sample the output value of the MAC operational amplifier only after x(k), x(k-1) and x(k-2) have been shifted into their correct positions (that is after clock pulse CP3). For our purposes however, the continuous output of the operational amplifier will be a good enough representation of y(k).

7.2.2 Clock generation

The CD4022 is a divide by 8 counter and will be used to generate the CP0, CP1 and CP2 clock pulses. A 555 timer generates the master clock to the CD4022 counter and after every eighth master clock pulse, a pulse (CP0) will appear on pin 2 of the CD4022 counter, as shown in Figure P5. One master clock pulse after this, a pulse (CP1) will appear on pin 3 of the CD4022 counter. After another master clock pulse, a pulse (CP2) will appear on pin 11 of the CD4022 counter. This process will repeat itself after 8 master clock pulses (the other five pulses available from the CD4022 are not used). The sampling period starts when clock pulse CP0 goes high and ends just before clock pulse CP0 goes high again (the sampling period is equal to 0.6283 sec which corresponds to the sampling frequency of 10 rad/sec).

The complete circuit to generate clock pulses CP0, CP1 and CP2, is shown in Figure P6.


7-5

A test probe consisting of a 1 k resistor in series with a LED, may be used to check whether the master clock and clock pulses CP0, CP1 and CP2 are present. The master clock frequency is a bit more than 10 Hz and the LED flickering can still be observed. The frequency of clock pulses CP0, CP1 and CP2 is low and can be easily monitored with the test probe. (Note: The master clock, CP0, CP1 and CP2 do not have to be displayed when demonstrating the final system.)

Clock pulse 0 (CP0) – pulse 0 on pin 2 of CD4022

Next sample period (8 master clock pulses)

inhibit reset

clock

9

8 7 6 5

+

10F

4 3 2 1

5 6 7 8

555

2.7 k

4.7 k

4 3 2 1

13 141516

CD4022

10 1112

9V battery

+

CP0

Master clock

CP1

CP2

Master clock (provided by 555 timer)

Duration of 8 pulses = 0.6283 sec.



Figure P5

Figure P6

1 k

LED Test probe


7-6

7.2.3 Filter circuit

The filter network outlined in Figure P4, will be realized with the circuit in Figure P7. Three of the four available switches on the CD4066 quad switch are used to sample x(t), x(k) and x(k-1). This circuit can only be tested if clock pulses CP0, CP1 and CP2 from the circuit in Figure P6, are connected to S2 enable (pin 6 of the CD4066), S1 enable (pin 5 of the CD4066) and S0 enable (pin 13 of the CD4066) respectively. If +9V from the battery is applied to the x(t) input (pin 1 of the CD4066), the y(k) output from the MAC operational amplifier must increase, which may be verified with the y(k) LED becoming progressively brighter. Zero volt (negative battery voltage) connected to the x(t) input, must result in the LED becoming progressively dimmer.

LED

x(k) 5

6

3

2

1

7

5

6

7

3

2

4

8

4

8

Input signal

100k

½LM358 (II-b)½LM358 (I-b)

½LM358 (II-a)

½LM358 (I-a)

y(k)

CP0

CP1

x(t)

C2

0.1F

x(k-2)

2

3

x(k-1)

C1

0.1F

C0

0.1F

x(k)

7

14

13

1

5

4

9

6

8

S1

S1 enable

S0 enable

S2 enable

CP2

CD4066

100k

100k

100k

Figure P7

1

x(k-1)

9V battery

+

1 k

MAC


7-7

7.2.4 Pulse generator

Another 555 timer will be used to generate the pulsed input signal x(t). This signal will be presented to the input of the filter with the aim that the filter will allow the fundamental harmonic to pass through while suppressing the higher harmonics. As we did not employ an anti-aliasing analog filter before the digital filter, harmonics near multiples of the sampling frequency, will pass through because of the characteristic repetitive behavior of digital systems. Fortunately the higher harmonics in a square wave, diminishes fairly rapidly.

The pulse generator must generate a frequency equal to the cut off frequency of the filter which is 1 rad/sec or 0.1592 Hz., which implies a period of 6.281 seconds.

The circuit for the pulse generator is given in Figure P8.

Again the correct operation of the pulse generator may be confirmed with a LED test probe.

7.2.5 Complete system

A block diagram of the complete system is shown in Figure P9.

Students must display the input signal x(t) and the output signal y(k) with LED’s when demonstrating their system.

LED

CP1

CP0

x(t)

Clock generator (Figure P6)

Input signal x(t) (Figure P8)

9V battery

+

CP2

Three tap FIR filter(Figure P7)

y(k)

LED Figure P9

x(t)

+

22 F

4 3 2 1

5 6 7 8

555

10 k

220 k

9V battery

+

Input signal todigital filter

T 6 sec

Figure P8

LED

1 k


7-8

7.2.6 LM385 Single Supply Operational Amplifier (Practical note)

The LM385 package contains two operational amplifiers with pin out configuration as shown in Figure P10. If it is suspected that the LM385 operational amplifier is faulty, a simple technique to check whether both amplifiers are working is to connect each one in voltage follower mode, shown in Figure P10. If the non-inverting input is connected to the positive supply (+9V), the output should be high (8V) while if connected to the negative rail, the output should be zero volt. If the non-inverting input is left open, the output should be high.

7.2.7 Additional information on 555 timer

Figure P11, shows the 555 timer connected as an astable multivibrator.

3, 5

2, 6

+

4 3 2 1

5 6 7 8

LM358

Top view

1, 7

8

4

9 V

Figure P10

+

C

4 3 2 1

5 6 7 8

555

RA

RB

Output +

TL TH

time Output

TL = 0.7RBC TH = 0.7(RA + RB)C Total period = T = 0.7(RA + 2RB)C

4 3 2 1

5 6 7 8

555 Top view

9V

Figure P11


7-9

7.2.8 Pin out details for CD4022 and CD4066

7.2.9 Parts List 2 × LM358 (dual operational amplifier) 1 × CD4022 (8 bit counter) 1 × CD4066 (quad switch) 2 × 555 (timer) 2 × 1 k (¼ watt resistor) 1 × 2.7 k (¼ watt resistor) 1 × 4.7 k (¼ watt resistor) 1 × 10 k (¼ watt resistor) 4 × 100 k (¼ watt resistor) 1 × 220 k (¼ watt resistor) 3 × 0.1 F (non electrolytic) 1 × 10 F (64 V electrolytic capacitor) 1 × 22 F (64 V electrolytic capacitor) 2 ×LED (red)

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

4022

1

0

2

5

6

NC

3

GND

Vcc

Reset

Clock

Inhibit

Carry out

4

7

NC

1

2

3

4

5

6

7 8

9

10

11

12

13

14

4066

1X

1Y

2Y

2X

2 Enable

Vcc

1 Enable

4 Enable

4X

4Y

3Y

3X

3 Enable

GND


7-10

7.3 Assessment

Students will prepare this project and demonstrate their work in class on the scheduled date and time. A very clear photograph (or print), showing the project together with the student’s student card (or other clear identification), will also be prepared as part of the demonstration and assessment. A student that demonstrates the successful filtering of the fundamental harmonic frequency from the rectangular input pulses,

will meet the required outcome for this unit, and will receive at least 50% for unit 3. Please note: 1. A project submitted without accompanying photo’s, will not be assessed, and a

photograph displayed on a camera or cell phone or sent via email, will not be acceptable, as a hard copy is needed for final assessment and moderation of the project. A well defined photo printed on a color printer (A4), is preferred.

2. The demonstration system must include the LED display of the input signal x(t) and the output signal y(k).

3. Students that demonstrate a system crudely constructed on a medium such as breadboard, but with the system operating perfectly, will receive 60 %. If, in addition, special attention is given to the construction (for example the circuit is assembled on veroboard), 10% will be added. If, in addition, a student displays exceptional initiative, for instance increasing the length and sampling frequency of the system, 75% or more will be awarded according to the judgment and discretion of the assessor. Construction on PC boards will not be allowed.

Documents

DIGITAL SIGNAL PROCESSING IVhome.mweb.co.za/rf/rfitch/eidsv4/DsvStGds.pdf · Learning Guide – Digital Signal Processing IV iv i) Module assessment: To successfully complete each