Digital System Design

Verilog® HDL

Maziar Goudarzi

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Today program

History of Verilog® HDLOverview of Digital Design with Verilog®

HDLHello World!Hierarchical Modeling Concepts

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History of Verilog® HDL

Beginning: 1983 “Gateway Design Automation” company Simulation environment

Comprising various levels of abstraction• Switch (transistors), gate, register-transfer, and higher

levels

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History of Verilog® HDL (cont’d)

Three factors to success of Verilog Programming Language Interface (PLI)

Extend and customize simulation environment Close attention to the needs of ASIC foundries

“Gateway Design Automation” partnership with Motorola, National, and UTMC in 1987-89

Verilog-based synthesis technology “Gateway Design Automation” licensed Verilog to

Synopsys Synopsys introduced synthesis from Verilog in 1987

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History of Verilog® HDL (cont’d)

VHDL VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language Developed under contract from DARPA IEEE standard Public domain Other EDA vendors adapted VHDL “Gateway” put Verilog in public domain

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History of Verilog® HDL (cont’d)

Today Market divided between Verilog & VHDL

VHDL mostly in Europe Verilog dominant in US

VHDL More general language Not all constructs are synthesizable

Verilog: Not as general as VHDL Most constructs are synthesizable

Verilog® HDL

Overview of Digital Design Using Verilog

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Overview of Digital Design Using Verilog

Evolution of Computer-Aided Digital DesignEmergence of HDLsTypical Design FlowImportance of HDLsPopularity of Verilog HDLTrends in HDLs

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Evolution of Computer-Aided Digital Design

SSI: Small scale integration A few gates on a chip

MSI: Medium scale integration Hundreds of gates on a chip

LSI: Large scale integration Thousands of gates on a chip CAD: Computer-Aided Design

CAD vs. CAE Logic and circuit simulators Prototyping on bread board Layout by hand (on paper or a computer terminal)

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Evolution of Computer-Aided Digital Design (cont’d)

VLSI: Very Large Scale Integration Hundred thousands of gates Not feasible anymore:

Bread boarding Manual layout design

Simulator programs Automatic place-and-route Bottom-Up design

Design small building blocks Combine them to develop bigger ones

More and more emphasis on logic simulation

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Emergence of HDLs

The need to a standardized language for hardware description Verilog® and VHDL

Simulators emerged Usage: functional verification Path to implementation: manual translation into gates

Logic synthesis technology Late 1980s Dramatic change in digital design

Design at Register-Transfer Level (RTL) using an HDL

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Typical Design Flow (in 1996)

1. Design specification2. Behavioral description3. RTL description4. Functional verification and testing5. Logic synthesis6. Gate-level netlist7. Logical verification and testing8. Floor planning, automatic place & route9. Physical layout10. Layout verification11. Implementation

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Typical Design Flow (cont’d)

Most design activity In 1996:

Manually optimizing the RTL design CAD tools take care of generating lower-level details Reducing design time to months from years

Today Still RTL is used in many cases But, synthesis from behavioral-level also possible Digital design now resembles high-level computer

programming

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Typical Design Flow (cont’d)

NOTE: CAD tools help, but the designer still has the

main role GIGO (Garbage-In Garbage-Out) concept To obtain an optimized design, the designer needs to

know about the synthesis technology• Compare to software programming and compilation

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Importance of HDLs

Retargeting to a new fabrication technology

Functional verification earlier in the design cycle

Textual concise representation of the design Similar to computer programs Easier to understand

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Popularity of Verilog HDL

Verilog HDL General-purpose Easy to learn, easy to use Similar in syntax to C Allows different levels of abstraction and mixing them Supported by most popular logic synthesis tools Post-logic-synthesis simulation libraries by all

fabrication vendors PLI to customize Verilog simulators to designers’ needs

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Trends in HDLs

Design at behavioral levelFormal verification techniquesVery high speed and time critical circuits

e.g. microprocessors Mixed gate-level and RTL designs

Hardware-Software Co-design System-level languages: SystemC, SpecC, …

Verilog® HDL

Hello World!

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Basics of Digital Design Using HDLs

Circuit Under Design(CUD)

84

Generatinginputs to CUD

Checkingoutputsof CUD

Test bench

Stimulus block

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ModelSim® Simulation Environment

You’ll see in the laboratory

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Verilog Basic Building Block

Module

module not_gate(in, out); // module name+ports // comments: declaring port type input in; output out;

// Defining circuit functionality assign out = ~in;

endmodule

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useless Verilog Example

module useless;

initial

$display(“Hello World!”);

endmodule

Note the message-display statement Compare to printf() in C

Verilog® HDL

Hierarchical Modeling Concepts

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Design Methodologies

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4-bit Ripple Carry Counter

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T-flipflop and the Hierarchy

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Modules

module <module_name>(<module_terminal_list>); ... <module internals> ...endmodule

Example:module T_ff(q, clock, reset); ... <functionality of T_flipflop> ...endmodule

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Modules (cont’d)

Verilog supported levels of abstraction Behavioral (algorithmic) level

Describe the algorithm used Very similar to C programming

Dataflow level Describe how data flows between registers and is processed

Gate level Interconnect logic gates

Switch level Interconnect transistors (MOS transistors)

Register-Transfer Level (RTL) Generally known as a combination of behavioral+dataflow that is

synthesizable by EDA tools

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Instances

module ripple_carry_counter(q, clk, reset);

output [3:0] q; input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset); TFF tff1(q[1],q[0], reset); TFF tff2(q[2],q[1], reset); TFF tff3(q[3],q[2], reset);

endmodule

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Instances (cont’d)

module TFF(q, clk, reset); output q; input clk, reset; wire d;

DFF dff0(q, d, clk, reset); not n1(d, q); // not is a Verilog provided primitive.

endmodule

// module DFF with asynchronous resetmodule DFF(q, d, clk, reset); output q; input d, clk, reset; reg q;

always @(posedge reset or negedge clk) if (reset)

q = 1'b0; else

q = d;

endmodule

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Instances (cont’d)

Illegal instantiation example: Nested module definition not allowed Note the difference between module definition and module instantiation

// Define the top level module called ripple carry// counter. It is illegal to define the module T_FF inside// this module.module ripple_carry_counter(q, clk, reset); output [3:0] q; input clk, reset;

module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING:<module T_FF internals>:endmodule // END OF ILLEGAL MODULE NESTING

endmodule

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Simulation- Test Bench Styles

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Example

Design block was shown before ripple_carry_counter, T_FF, and D_FF modules

Stimulus block

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Example (cont’d)

module stimulus; reg clk; reg reset; wire[3:0] q;

// instantiate the design block ripple_carry_counter r1(q, clk, reset);

// Control the clk signal that drives the design block. initial clk = 1'b0; always #5 clk = ~clk;

// Control the reset signal that drives the design block initial begin reset = 1'b1; #15 reset = 1'b0; #180 reset = 1'b1; #10 reset = 1'b0; #20 $stop; end

initial // Monitor the outputs $monitor($time, " Output q = %d", q);endmodule

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What we learned today

History of Verilog HDLPrinciples of digital design using HDLsOur first Verilog design example

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Other Notes

Course web-page http://ce.sharif.edu/courses

Exercise 1 Install and use ModelSim in the lab. to simulate ripple_carry_counter example

Chapter 2 exercises