Digitala integrerade kretsar - eit.lth.se · Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, Digitala integrerade kretsar: teknologi och metod

Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, www.eit.lth.se

Digitala integrerade kretsar: teknologi och metod

Viktor Öwall


Motivation

• Hur konstruera med transistorer?

• Hur påverkar teknologin prestanda, tex

klockfrekvens och effektförbrukning?

• Vart är vi på väg?

• Vilka alternativ har vi?


Vi tittar först på logiska grindar,

viss repetition och en del nytt.

Sen lite mer vart elektroniken är

på väg.


V DD

A B

B

GND

A

A B OUT

0

1

1

1 1

0

0

0 OUT

Truth Table

Vad är detta?


&

US

A B NAND

0

1

1

1 1 0

0

0 1

1

1 0

NAND + Inverter a AND

Europe

AND

0

0

0

1

Logisk grind, NAND

+ a


Varför börjar jag med NAND

och inte AND?

Grundblock och för att den är

enkel att implementera med

CMOS transistorer.


Digitalt arbetar vi i stort sätt

uteslutande med CMOS transistorer.

p- N-Channel

Gate Drain Source

n+ n+

Solid State Physics V DS [V]

I D

V GS

I d

Electrical Characteristics

gm

Vgs

go

Vgs

Vds

drain

source

gate Small Signal Model (amplifier design)

GND

VDD

Digital – transistor as a switch


Logic Gates,

AND

A

GND

B

AND

Vdd

Vdd

NAND

PMOS

NMOS

GND

Vdd

&

US

A B NAND

0

1

1

1 1 0

0

0 1

1

1 0

NAND + Inverter a AND

Europe

V DD

A B

B

NAND f

GND

AND f

A

AND

0

0

0

1


Two

Input

NAND/

AND

0.8 m

CMOS

Början av

90-talet. Vad

har vi idag?

NAND

Inverter


V DS [V]

I D

V GS

V GS

V GS

Linear

Saturation

Pinch-off TGSDS VVV

ID som funktion av VDS


NMOS transistorn som strömbrytare

V DS [V]

I D

V GS

V GS

V GS

vin

vin=“låg” a “öppen”

vin=“hög” a “kortslutning”

Ökande VGS

G

S

D


PMOS transistorn som strömbrytare

V DS [V]

I D

V GS

V GS

V GS

vin

VDD

G D

S

vin=“hög” a “öppen”

vin=“låg” a

“kortslutning”


GND

V DD

I D

CMOS inverteraren med

transistorn som strömbrytare

“hög” in a

NMOS “kortsluten”

PMOS “öppen”


CMOS Inverteraren

VOUT

VIN

Ideal

Vdd/2

Idealt slår transistorerna om

som strömbrytare vid VDD/2.

Men hur är det egentligen?


CMOS Inverteraren

VOUT

VIN

Ideal ”Verklig”

V OUT

N Off

P Lin

V IN

N Lin

P Off

N Sat

P Sat

N Sat

P Lin

N Lin

P Sat

Vdd/2

Inget

omedelbart

omslag

≈Vdd/2 Omslagspunkt

varierar


Omslagstid

”Verklig”

V OUT

N Off

P Lin

V IN

N Lin

P Off

N Sat

P Sat

N Sat

P Lin

N Lin

P Sat

Vad beror omslagstiden på?


Omslagstid

”Verklig”

V OUT

N Off

P Lin

V IN

N Lin

P Off

N Sat

P Sat

N Sat

P Lin

N Lin

P Sat


En kapacitans som

inkluderar såväl

interna som externa

bidrag, t.ex.

kapacitansen från

ingången till nästa

steg.


Omslagstid

”Verklig”

V OUT

N Off

P Lin

V IN

N Lin

P Off

N Sat

P Sat

N Sat

P Lin

N Lin

P Sat


En kapacitans som

inkluderar såväl

interna som externa

bidrag, t.ex.

kapacitansen från

ingången till nästa

steg.

Mer om hastigheten senare.


Hur konstruerar vi som ingenjörer

tex en inverterare?

Om alls så i datorn.

Ofta kommer dessa

grundkomponenter i ett

cellbibliotek, dvs att få

konstruktörer gör detta

själv.


P-Substrate

N-Well

N-Channel

P-Channel


p -

n + n +

Gate

Drain Source

substrat

Courtesy of Intel


Detta kallas:

Complementary Logic V

DD

A B

B

GND

A

OUT Properties:

+ rail to rail swing

, i.e.out = VDD or GND

+ ”no” static power, i.e.

either PUN or PDN off

- Many transistors

Pull up network

Pull down network


Pseudo-NMOS Gates

V DD

B

GND

A

OUT

Pull up network

Pull down network

Properties:

+ fewer transistors

+ in the early years there

was only NMOS

- Static power consumption

- Low input ”not 0”


Pseudo-NMOS Gates

V DD

B

GND

A

OUT

Properties:

+ fewer transistors

-Static power consumption


En ”resistans” där R

beror på transistorns

egenskaper.


Pseudo-NMOS Gates:

Static Power V

DD

B

GND

A

OUT Vad händer när A=B=1?


Pseudo-NMOS Gates:

Static Power V

DD

B

GND

A

OUT Vad händer när A=B=1?

Ström från VDD till GND

vars storlek beror på R.

R

Istatic

Statisk effektförbrukning!


Så med enbart NAND kan vi göra allt,

dvs i princip bygga en processor.

Men är det effektivt?


Så med enbart NAND kan vi göra allt,

dvs i princip bygga en processor.

Men är det effektivt?

Nej, alltför många transistorer,

alltför långsamt och

för hög effektförbrukning!


Komplexare funktioner: addition

i+1 b i+1 a i b i a

i cin

i+1 cout

msb b msb a

msb cin

msb cout

lsb =

least signifcant bit msb =

most signifcant bit

sumi sumi+1

Memory digit:

carry value

summsb

Overflow om

resultatet

”för stort”.


Komplexare funktioner: addition

i b i a

i cin

sumi

Hur implementerar jag denna med transistorer?


Från tidigare lektion


Heladderare med NAND

9 x NAND a 36 transistorer


Full Adder in CMOS, 1 bit

A and B: in

C: carra in

S: sum

Co: carryout

C

B A B

A

A

B B

C

C

C

C

A

A

A

B B

B

V DD

V DD

S C o

C A B

V DD

A

A B Cin Co S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

24 transistorer (36 med enbart NAND)



A and B: in

C: carra in

S: sum

Co: carryout

C

B A B

A

A

B B

C

C

C

C

A

A

A

B B

B

V DD

V DD

S = 1 C = 1 o

C A B

V DD

A

A B Cin Co S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1



A and B: in

C: carra in

S: sum

Co: carryout

C

B A B

A

A

B B

C

C

C

C

A

A

A

B B

B

V DD

V DD

S = 0 C = 0 o

C A B

V DD

A

A B Cin Co S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1



A and B: in

C: carra in

S: sum

Co: carryout

C

B A B

A

A

B B

C

C

C

C

A

A

A

B B

B

V DD

V DD

S = 1 C = 0 o

C A B

V DD

A

A B Cin Co S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1


En ”carry ripple adder”.

i+1 b i+1 a i b i a

i cin

msb b msb a

msb cin

msb cout sumi sumi+1 summsb

Vad är maximal fördröjning?

Max delay?

Max delay

Viktigt att optimera carry-kedjan.



C

B A B

A

A

B B

C

C

C

C

A

A

A

B B

B

V DD

V DD

S C o

C A B

V DD

A

• Hur stora skall transistorerna vara?

• Vilka ingångar skall placeras var?

• Är detta en bra lösning?

• Beror på, tex är det hastighet eller effektförbrukning.

Finns mänger med adderar strukturer.


Det var lite om funktionaliteten.

Nu till prestanda.


• Hastighet

• Effektförbrukning

L är kanallängden vilket refereras till som

processen, technology, technology node, …

Anges i meter.

Vad är den idag?


DrainSource Gate

CDB

n+n+

CG

CGD

CGS

CSB

Xd

tox

Kapacitanser: påverkar hastigheten

Bulk Cap.

Junction Cap.

Overlap Cap.


Hastighet: en enkel model

2

L

)( TDD

DDpd

VVk

VCT

Stor kapacitans ger långsamma kretsar:



Stor kapacitans ger långsamma kretsar:

2

L

)( TDD

DDpd

VVk

VCT

Uin Uut R

C RCteEtv

/1

Liten RC a snabbare

Stor R or C a långsammare

tid

V



mindre transistorer a lägre kapacitans a snabbare kretsar

2

L

)( TDD

DDpd

VVk

VCT

Så vad är problemet?



mindre transistorer a lägre kapacitans a snabbare kretsar

2

L

)( TDD

DDpd

VVk

VCT

Så vad är problemet?

VDD?



2

L

)( TDD

DDpd

VVk

VCT

fkV

CT

DD

Lpd

1

om TDD VV

Stor approximation idag!


Avståndet mellan VDD and VT

har minskat.

Shouri Chatterjee, Yannis Tsividis and Peter Kinget,

Analog Circuit Design Techniques at 0.5V

Olika VT ger olika

karakteristik



2

L

)( TDD

DDpd

VVk

VCT

fkV

CT

DD

Lpd

1

om TDD VV

Så hastigheten är proportionell mot VDD.

Varför inte öka den?



2

L

)( TDD

DDpd

VVk

VCT

fkV

CT

DD

Lpd

1

om TDD VV

Så hastigheten är proportionell mot VDD.

Varför inte öka den?

Effektförbrukningen ökar och

små transistorer tål inte stora spänningar!


Effektförbrukningen hos CMOS

staticdynamictotal PPP

Historiskt den viktigaste.

Ignorerades tidigare

men nu viktigt.


Dynamisk Effektförbrukning

Uppladdning

V DD

Urladdning

2

dynamic L DDP f C V

Pdynamic varierar med kvadraten på VDD

a vi vill minska den

a långsammare kretsar


Statisk effektförbrukning:

vad är strömmen när ingångarna ligger

fast på högt eller lågt?

Linear Saturation V DD


Statisk effektförbrukning

på grund av läckströmmar.

Ileakage increases with

decreasing VT

Pstat =Ileakage VDD

Drain Leakage

I leakage

Subthreshold

Current

V DD


VT skalning:

trade-off mellan VT och IOFF

Men vad var bra med låg VT?

Performance vs

Leakage:

VT a IOFF

High VT

VG

VTH

ln

( I D

S)

IOFFH

Low VT

VTL

IOFFL

När VT minskar ökar läckströmmarna!

Snabbare kretsar!


Trender inom effektförbrukning

From

OptimizationDSP Architecture Design Essentials

By Dejan Markovic (UCLA) and Robert W. Brodersen (UC Berkeley)


So what do we do?

High VDD needed for high speed a

High Power consumption!

– One possibility: parallel processing!

Low VT needed for high speed a

High leakage power!

– Two possibilities:

• Multiple VT

• Find ways to reduce leakage, e.g. power gating


The end of ”some” scaling!


Going Multicore, e.g. Intel SandyBridge!

• 32 nm – 64 bit

• 4 995 000 000 Transistors

• ~3.5 GHz

• 216 mm2 (10x Pentium 4)


Going sub-threshold: long pursued in research. - Intel September 2011!


2007-09-03 ESS010 - Konsumentelektronik:

Överblick

60

p -

n + n +

Gate Drain Source

Gate-oxid

(isolerande)

substrat

WAFER

MOS transistorn


Nya typer av

transitor…FinFET/TriGate

“Going from flat to three-dimensional in the conservative

microchip industry is a radical shift, but as Leo Mathew, a

research scientist at Freescale Semiconductor, says, the payoff

will be substantial.”

Finns i Intels senaste processorer!


…and new technologies!


You can learn more in

ETIN20 Digital IC-design.


Computational Platforms

What options do we have?

What are the trade-offs?


Software vs. Hardware

Algorithm

Dedicated

Hardware

Processor

• Programmable

• “Low” Design cost

CPUs, micro processors,

micro controllers, …

• Process chips

• High Performance

• Low Power

• High cost

Programmble

Hardware

• Reconfigurable hardware

• No processing

Programble Logic Devices

(PLD): PLA, PAL, FPGAs, Gate

array (include processing), …


Software or Hardware?

• Flexibility

• Performance Requirements

– Power Consumption

– Throughput

• Cost

– Volume

– Know how

– Time to Market


Dedicated Hardware Architecture, i.e. you design hardware that makes what you want!

Special Purpose

PLD, e.g. FPGA

PLDs:

PAL, Field Programmable

Gate Arrays,…

• Reconfigurable

• Fast Turn Around

• Prototyping

Gate Array

ASIC

Application/Algorithm

Specific Integrated Circuit

• High Calculation Capacity

• High Utilization

• Low Power

• Low Price at Volume


Energy efficiency (MOPS/mW)

0,01

0,1

1

10

100

1000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

En

erg

y a

nd

Are

a E

ffic

ien

cie

s

Chip Number (see next slide)

Microprocessors Dedicated

Designs

General

Purpose

DSP’s

Courtesy: Professor Bob Brodersen, UC Berkeley


1

10

100

1000

10000

100000

0 2 4 6 8 10 12

SNR (db)

Re

lati

ve

Co

mp

lexit

yThe Cost of Approaching Shannon’s Bound

Courtesy Engling Yeo, UCB

8/9 Turbo, =4, N=4k

2/3 Turbo, =4, N=64k 1,2, and 3 iterations

1/2 Turbo, =4, N=64k 1,2,

and 3 iterations

8/9 LDPC, N=4k 1,3, and 5 iterations

8/9 Conv. Code, =3, N=4k



8/9 Capacity Bound

2/3 Capacity Bound

1/2 Capacity Bound

1/2 LDPC, N=107, 1100 iterations

for BER of 10-5


1

10

100

1000

10000

100000

0 2 4 6 8 10 12

Re

lati

ve

Co

mp

lexit

y

SNR (db)

The Cost of Approaching Shannon’s Bound

Courtesy Engling Yeo, UCB

1/2 Turbo, =4, N=64k 1,2,

and 3 iterations


1/2 Capacity Bound

1/2 LDPC, N=107, 1100 iterations

for BER of 10-5

LDPC-codes were proposed by Gallager in 1963.

However, they were considered of limited practical

use due to the implementation complexity. Now

LDPC-codes are in standards.


Tx

Tx

Tx

Tx

Data

Rx

Rx

Rx

Rx

High complexity

receiver

Symbol

Detection

Channel

Estimation

Matrix

Inversion

r = Hs + n

H ^ H-1 ^

s = H-1r ^ ^

QR-factorisation

PE PE PE

PE PE

PE

PE

PE PE

PE PE

PE

PE

PE

PE

PE

PE

PE

PE

PE

Inversion of triangular sub-

matrix

S/P

Multiple Antenna Systems – e.g. MIMO

• Multi-antenna approach exploits multi-path by sending data along several channels

• Results in large theoretical improvements in bandwidth efficiency for fading channels

• But…computationally hungry


MIMO Hardware perspective

Rx

Rx

Rx

Rx

Symbol

Detection

Channel

Estimation

Matrix

Inversion

r = Hs + n

H ^ H-1 ^

s = H-1r ^ ^

Tx

Tx

Tx

Tx

Data S/P

WLAN 802.11n Example

Modulation 256QAM; 4 Tx antennas; 108 sub-channels, 4s per symbol

ML detection 1.159 x 1017 lattice points/sec

Current DSP technology is 1G inst/s 108 processors!

OR (“Moores Law” ..... processor capability doubles every 18 months)

MUST WAIT 40years!

Mike Faulkner 2005, Victoria Univ.


B

E

R Sub-optimal QPSK

(square-root) 0.35 μm

Sphere 16QAM 0.35 μm

+ Soft Output 0.13 μm

#mult/

symbol

Trading Complexity – 4x4 antennas

ML-detection


MIMO going Massive

World Unique testbed

• 300kg

• 5kW@start-up

• Lots of cables!

In cooperation with

National Instruments (NI)!


LuMaMi:

Lund Massive Mimo Testbed

50 NI USRP: 2 radio chains each

a 100 simultaneous antennas

Xilinx Kintex-7

That is where

the power is going!


FPGA: Virtex from Xilinx BANK 0 BANK 1

BANK 5 BANK 4

BA

NK

6

BA

NK

7

BA

NK

3

BA

NK

2

IOB

Block RAM

CLB

Timing

Routing


Example: Xilinx FPGAs

CLB CLB

CLBCLB

Horizontal

Routing

Channel

Vertical

Routing

Channel

Interconnect

point

Switching

matrix

Configurable Logic Block

R

Q 1 D

CE

R

Q 2 D

CE

F

G

F

G

F

G

R

D in

Clock

CE

F

G

A

B/Q 1 /Q 2

C/Q 1 /Q 2

D

A

B/Q 1 /Q 2

C/Q 1 /Q 2

D

E

Combinational logic Storage elements

Any function of up to

4 variables

Any function of up to

4 variables


Basic Spartan Architecture – Low end FPGA


Xilinx Virtex-II Pro – Heterogeneous Programmable Platforms

Courtesy Xilinx High-speed I/O

Embedded PowerPc

Embedded memories

Hardwired multipliers

FPGA Fabric


Examples of FPGA Development Boards e.g. from Digilent (http://www.digilentinc.com)

Nexys4 Board • US$320/179 full/academic (2014)

• Xilinx Artix -7 FPGA

• 128Mbit serial Flash

• Serial port, Ethernet, VGA port, 3-axis accelerometer,

PWM audio output, Temperature sensor, microphone,

USB for mice, keyboards and memory sticks

• etc

Virtex-V Board • US$2199/799 full/academic (2014)

• Virtex-5 FPGA

• 256MB DDR2 + 2 x 32MB Flash + more

• JTAG, Ethernet, Video input, Video (DVI/VGA) output,

Stereo AC97 codec with line in, line out, headphone,

microphone, and SPDIF digital audio

• etc


Some remarks on FPGAs

Fantastic development platforms.

Offers lots of processing resources.

However:

• They are not low power

• Hardware uilization is rather low

• Lots of resources in configuration and routing


Other Platforms

Arduino Arduino is a tool for making computers that can sense

and control more of the physical world than your

desktop computer.

It's an open-source physical computing platform

based on a simple microcontroller board, and a

development environment for writing software for the

board.

Raspberry Pi From www.raspberrypi.org

“The Raspberry Pi is a low cost, credit-card sized

computer that plugs into a computer monitor or TV,

and uses a standard keyboard and mouse. It is a

capable little device that enables people of all ages to

explore computing, and to learn how to program in

languages like Scratch and Python. “

http://www.raspberrypi.org/

http://upload.wikimedia.org/wikipedia/commons/4/45/Raspberry_Pi_-_Model_A.jpg


Memories are a crucial part of

most designs.


Cell-phone ASIC complexity and cost

Courtesy: Sven Mattisson, Ericsson


Market for Memories According to a new technical market research report, semiconductor Memory: Technologies and Global Markets, the value of the global semiconductor memory industry was nearly $46.2 billion in 2009, but is expected to increase to nearly $79 billion in 2014, for a 5-year compound annual growth rate (CAGR) of 11.3%.

The largest segment of the market, DRAM, or dynamic random access memory, is projected to increase at a CAGR of 10.4% to $41.5 billion in 2014, after being valued at nearly $25.2 billion in 2009.

NAND, or nonvolatile/NANO RAM, which is the second-largest segment of the market, is estimated at $12.8 billion in 2009, and is expected to increase at a 5-year CAGR of 15% to reach more than $25.7 billion in 2014.

Source: Semiconductor Memory: Technologies and Global Markets, April 2010

From http://www.electronics.ca/presscenter/articles/1272/1/Global-Market-For-Semiconductor-Memory-To-Be-Worth-79-Billion-In-2014/Page1.html

Report Price: Price:USD $4,850.00!!!

Motivation behind the quest for new memory technologies!


Example: FFT Design

8k points FFT for DVB (Digital Video Broadcasting)

1996-97 in 0.5m CMOS

Several embedded

memories who’s

properties and size

is crucial to the

implementation


Sequential Circuits & D flip-flop

From Lecture 3.

Properties:

• can be dynamic or static

• Latch or Register

• Latch - level sensitive

• Register - edge triggered

Flip-flop most often refer to an

edge triggered register.


We have registers, why memories?

Static D Flip-flop : 252µm2 SRAM Memory element :

30µm2

0.35µm CMOS technology process


Flip-flops vs. SRAM

0 500 1000 1500 2000 2500 3000 3500 4000 45000

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

memory elements

square

mm

Flip-flops

Dual port memory

Single port memory

Double width memory

Alcatel Microelectronics 0.35µm CMOS technology process

Process and library dependent.

Flip-flops

SRAM


A memory is more than the storage

elements, i.e. the memory cells.

Address decoders, sense amplifiers,

clock buffers, etc


The Complete Memory

An Overview of Logic Architectures Inside Flash Memory Devices

ANDREA SILVAGNI, GIUSEPPE FUSILLO, ROBERTO RAVASIO, MASSIMILIANO PICCA, AND STEFANO ZANARDI

PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003

Memory

array


Pseudo NMOS ROM

WL[0]

V DD

Pull Up

WL[2]

WL[3]

WL[1]

BL[3] BL[0] BL[1] BL[2]

The placements of transistors decide memory content.

Do we recognize this?


Pseudo-NMOS Gates

V DD

B

GND

A

OUT

Pull up network

= load device

Pull down network

Properties:

+ fewer transistors

-Static power consumption


Function?

A B OUT

0

1

1

1 1

0

0

0


Pseudo NMOS NAND ROM

All transistors ON

pulls down Bit Line

Non-selected WL =1

WL lines reversed

A B Q

0 0 1

0 1 1

1 0 1

1 1 0

Select WL[2] a WL[0,1,3]=1 and WL[2] = 0

1

1

0

1

on

on

on

off off

Transistor on selected line shuts off path to GND

WL[0]

V DD

Pull Up

WL[2]

WL[3]

WL[1]

BL[3] BL[0] BL[1] BL[2]


Pseudo NMOS NOR ROM

NMOS NOR ROM GND lines overhead

Area Reduced by Mirroring

One transistor ON

pulls down Bit Line

A B Q

0 0 1

0 1 0

1 0 0

1 1 0 No transitors

= always

pulled up

BL[0]

V DD

Pull Up

BL[1] BL[2] BL[3]

GND

GND

WL[2]

WL[3]

WL[1]

WL[0]


Pseudo NMOS NOR ROM

NMOS NOR ROM GND lines overhead

Area Reduced by Mirroring

One transistor ON

pulls down Bit Line

A B Q

0 0 1

0 1 0

1 0 0

1 1 0

Select WL[2] a WL[0,1,3]=0 and WL[2] = 1

0 0 1 1

V DD

Pull Up

GND

GND

WL[2]=1

WL[3]=0

WL[1]=0

WL[0]=0


ROM or PLA

AND

plane

A0/X0

OR

plane

f 0

f 1 A1/X1 A2/X2

But now we had NAND/NOR?


AND - OR

NAND - NAND

NOR - NOR


NOR or NAND?

• NOR is faster – no series transistors.

• NAND is smaller – no GND lines.

You can see this if you look at e.g. FLASH

memories


What is a Flash memory?

• ROM – Read Only Memory

• RAM – Random Access Memory

• FLASH


What is a Flash memory?

• ROM – Read Only Memory

– data doesn’t change

– data remain when powered down

• RAM – Random Access Memory

– data can be both read and stored

– data disappears when powered down

• FLASH

– data can be both read and stored

– data remain when powered down


Floating Gate Transistor (FAMOS) electrically programmable VTH

n + n +

Floating gate Control gate

• Control gate is connected to wordline

• Floating gate is left unconnected

– If charged heavily negative a High VTH a ”Never” a channel

– If charged removed a Low VTH a ”ordinary” operation

• EPROM, EEPROM and Flash has different ways of controlling

the charge of the floating gate

WL

BL


Flash EEPROM

Control gate

erasure

p- substrate

Floating gate

Thin tunneling oxide

n 1 source n 1 drain programming


FLASH stucture

V DD

Pull Up

GND

GND

word2

word3

word1

word0

Floating gate transistors everywhere!


FLASH write, e.g. trap charge V DD

Pull Up

GND

GND

word2

word3

word1

word0

= trapped charge. Transitor is always off a Same content as ROM.


Read-Write Memories (RAM)

• Static (SRAM)

– Data stored as long as supply is applied

– Large cells (6 transistors/cell)

– Fast

• Dynamic (DRAM)

– Periodic refresh required

– Small cells (1-3 transistors/bit)

– Slower


Dynamic or Static RAM

6-transistor SRAM Cell

WL

BL BL

M5 Q

M1 M3

M6

M4 M2

Q

V dd

M 1

C S

WL

BL

C BL

1-transistor DRAM

Compare dynamic latch/register


How do we design today?


Design Flow: a simplified view

HDL (VHDL/Verilog/...)

P&R

Cell library

Configuration Post-layout sim.

Simulation

Synthesis

Fabrication


To move to a higher abstraction levels.

Algorithms, like for LDPC and MIMO, is often

developed in MATLAB or C/C++.

How can we easier get from there to hardware?

Is High Level Synthesis the answer?

SystemC, CatapultC, Vivado, etc

It’s getting there!?

Trend towards

High Level Synthesis


You can learn more in:

ETIN20 Digital IC-design,

EITF35 Introduction to

Structured VLSI Design

and

ETIN35/40 IC project 1 & 2

Documents

Digitala integrerade kretsar - eit.lth.se · Viktor Öwall, Inst. för Elektro- och Informations Teknologi, Lunds Universitet, Digitala integrerade kretsar: teknologi och metod