1294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006

Direct Digital-Frequency Synthesis byAnalog Interpolation

Alistair McEwan, Member, IEEE, and Steve Collins, Member, IEEE

Abstract—A highly compact 9-bit CMOS direct digital synthe-sizer without read-only memory that consumes 8 W/MHz is de-scribed. The circuit is based upon a small nonlinear array of sixcurrent sources and six current switches. This array converts ananalog voltage that represents the signal phase to an output currentthat represents the corresponding amplitude. Measurement resultsshow that the resulting 3.3-V 0.35- m system is robust to mismatchand capable of generating a signal with a spurious free dynamicrange as good as 48 dBc with a circuit area of 0.0085 mm2. Thislevel of performance and the compactness of the analog circuitmake it an attractive starting point for the arrays of frequency syn-thesizers that will be needed in a range of instrumentation systems.

Index Terms—ROM-less direct digital-frequency synthesis(DDFS) instrumentation.

I. INTRODUCTION

ACONVENTIONAL direct digital-frequency synthesis(DDFS) architecture consists of a large overflowing accu-

mulator to generate an instantaneous digital phase. This digitalphase word then forms the input to a ROM look-up table,which converts the phase input to the corresponding amplitude.Finally, a digital-to-analog converter (DAC) converts the digitalamplitude word to an equivalent analog value [1]. The perfor-mance of this type of DDFS architecture, particularly its powerconsumption, is often limited by the ROM. Several techniquesthat employ additional digital circuitry to reduce the size ofthe ROM and hence, the power consumption, yet achieve aparticular maximum output frequency and spectral purity havetherefore been developed [2]–[5], and a good summary is givenby Vankka et al. [6] and Langlois and Al-Khalili [7]. Thetrend to reduce the size of the ROM has naturally led to thedevelopment of DDFS systems in which phase-to-amplitudeconversion is performed without resorting to a ROM. Oneapproach to designing a ROM-less DDFS system is to simplycalculate the digital amplitude corresponding to a digital phase[8]. Alternatively, the functions of the ROM and the DAC in theconventional architecture can be combined within a nonlinearDAC [9]–[11].

This brief describes a more compact DDFS architecture basedon the nonlinear interpolation previously presented in [9] and

Manuscript received March 3, 2006; revised May 10, 2006. This work wassupported by the EPSRC under Grant GR/N18048. This paper was recom-mended by Associate Editor S. Callegari.

A. McEwan was with the Department of Engineering Science, Universityof Oxford, Oxford OX1 3PJ, U.K. He is now with the Medical Physics andBioengineering, University College London, London WC1E BT, U.K. (e-mail:a.mcewan@ucl.ac.uk).

S. Collins is with the Department of Engineering Science, University of Ox-ford, Oxford OX1 3PJ, U.K. (e-mail: collins@robots.ox.ac.uk).

Digital Object Identifier 10.1109/TCSII.2006.882349

Fig. 1. New DDFS architecture showing the accumulator on the left. Theoutput from the accumulator forms the input to the digital circuits neededto exploit the half-wave symmetry of the output wave. The output from thiscircuit is converted to an analog voltage that represents the instantaneous phaseof the signal by a linear DAC. Finally, this analog signal forms the input to anonlinear interpolating circuit whose output current represents the amplitudecorresponding to the instantaneous phase.

[10]. The interpolation technique used here is similar to thatused in an interpolating or folding flash analog-to-digital con-verter (ADC). This architecture is based upon a simple analogcircuit that converts an input voltage that represents the phaseof the signal to an output current that represents the amplitudeof the signal. Simulation results indicate that the spurious-freedynamic range (SFDR) of the output signal from the new archi-tecture with only six current cells can be as good as 50 dBc.

Instrumentation systems commonly use frequency synthesisas a standard reproducible source that can be used to guaranteethe accuracy of a measurement. One of the advantages of DDFSin instrumentation is its good frequency resolution, which al-lows fine trimming or calibration to remove variations in thesynthesizer itself or in the rest of the measurement system. Thislevel of performance together with the simplicity and compact-ness of the analog circuit makes the new architecture attrac-tive for generating the stimulus for resonant micromechanicalsensors, which require an SFDR of better than 40 dB [12],and the electric fields needed for noncontact sorting of particlesusing dielectrophoresis, which require an SFDR of better than

30 dB [13], [14]. The electric field may also be used to iden-tify or image biological particles and tissues via their impedancespectra [15], [16] with sinusoidal signals with an SFDR of betterthan 40 dBc. In these instrumentation systems, the output fre-quency requirement spans from dc to 1 MHz.

II. PROPOSED ARCHITECTURE

A schematic diagram of the proposed new DDFS architectureis shown in Fig. 1. As in a conventional system, this architecturecontains an accumulator to calculate the digital word that rep-resents the instantaneous phase of the output signal. The most

1057-7130/$20.00 © 2006 IEEE

MCEWAN AND COLLINS: DIRECT DIGITAL-FREQUENCY SYNTHESIS 1295

Fig. 2. Simple three-transistor circuits, which form the basis of the interpo-lating circuit.

significant bits of the output from the accumulator are then usedto determine the phase of the output signal. The first stage in thisprocess is to use the most significant bit to exploit the half-wavesymmetry of the output to minimize the size of the circuits thatare needed to transform this digital word into its correspondinganalog amplitude. Unlike other architectures, the digital outputfrom this block then forms the input to a linear DAC, which isreferred to as the phase DAC. The output from this circuit is ananalog voltage that represents the phase of the signal. Finally,this voltage forms the input to the interpolating circuit that con-verts the input phase to the output amplitude. To understand theoperation of the interpolating circuit, consider the circuit shownin Fig. 2. This circuit consists of a MOSFET that actsas a constant-current source connected to a pair of MOSFETs

and , which act as a differential input. If the differentialinput devices in the circuit are well matched, all the transistorsare operating in saturation, and , then the output cur-rent from the circuit can be calculated using

(1)

However, if , then , or if ,then . This saturation of the output current from thecircuit in Fig. 2 to either 0 or can be exploited to convertan input phase voltage to the corresponding amplitude. In thecircuit in Fig. 3, this is achieved by connecting six circuits inparallel. Each circuit receives an input voltage that representsthe instantaneous phase of the output signal; however, each ofthe six circuits has a different reference voltage. These referencevoltages are chosen to have uniform spacing , and theinput voltage must range between and given by

(2)

(3)

This choice of reference voltages and input-voltage rangemeans that as the input voltage increases from to ,each pair of differential devices successively steers their associ-ated current toward the output node. Since the system exploits

Fig. 3. System used to convert an input phase voltage to an output current thatrepresents the corresponding amplitude.

the half-wave symmetry of a sinusoidal output, the interpolatingcircuit only needs to represent the output signal over the rangeof 0– . Thus, to ensure that the six current sources representhalf a period, the bias current of each current cell must be

(4)

(5)

(6)

(7)

(8)

(9)

where is the current that represents the amplitude of theoutput signal. The quarter-wave symmetry of the cosine wave(about ) means that , , and . Sincethe reference voltages are equally spaced over the range of inputvoltages, then to accommodate the different bias current values,the parameter for the input devices in each current cell mustbe chosen to ensure that is the same in each current cell.Then, the only undetermined parameter that can control the per-formance of the interpolating circuit is the total output current,which will determine the relationship between and thedifferential input voltage needed to saturate the output from eachcircuit.

III. CIRCUIT SIMULATIONS

The optimum total output current and the correspondingperformance of the interpolating circuit were determined bysimulating the circuit in Fig. 3 using the device parameters for

1296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006

an 0.35- m CMOS process. To determine the transistor sizesand reference voltages for this circuit, the following require-ments need to be considered: The voltage supply is limited to3.3 V. Within this voltage range, a saturated current source anddifferential input and output voltage swing must be allocated.With this in mind, the circuit was designed to operate with agate–source voltage of approximately 1 V for the MOSFETsused as current sources. Then, to ensure that these currentsources remain saturated, the minimum input voltage to thiscircuit should be approximately 1 V. The minimum differencebetween the reference voltages of adjacent devices was thenchosen to be 200 mV. Once the various voltage levels hadbeen determined, the next stage of the design was to use infor-mation provided by the circuit manufacturer to determine thedimensions of the devices in the interpolating circuit. A criticalcriterion throughout this design process was to try to achievea high yield of working circuits despite both the process andparameter variations that occur in any manufacturing process.

When MOSFETs are used to create constant-current sourceswith different output currents, it is good practice to use sev-eral “unit” MOSFET current sources acting in parallel withineach current to create a ratio of output currents that is robust toprocess variations. Simulations suggested that the SFDR of theoutput signal could be maintained if 4, 11, and 15 1- m-wideand 10- m-long MOSFETs are used as the unit current sourcesto create the three different bias currents that are needed in theinterpolating circuit. In addition, to scale the transconductanceparameter of the input transistors to be proportional to the biascurrent in each circuit, different sizes of the input transistor arerequired. All the input transistors were designed to be 3.5 mlong, and the three different widths of the devices used with thethree different bias currents were 4.05, 11.5, and 16 m.

The simulation results from the circuit with these device sizesand bias voltages are shown in Fig. 4. These results show thatwhen is too low, the output from each cell saturates beforeits neighboring cell starts to contribute to the output. The re-sulting ripples on the output amplitude reduce the SFDR of thesignal. In contrast, at high bias voltages, the input-voltage rangeis too small to saturate the output of any of the current sources.All six circuits are then effectively operating in a linear regime,and the output resembles a triangular wave. As shown in the cen-tral panel of Fig. 4, between these two extremes, there is a rangeof bias voltages between 0.85 and 0.9 V for this particular cir-cuit, which gives the best approximation to a sinusoidal output.In this bias range, the SFDR of the output is 52 dBc. Fur-thermore, this creditable performance has been achieved usinga simple circuit, which for the target 0.35- m process, occu-pies only 8400 m (Fig. 5), which is less than the area that isneeded for a bond pad. The output frequency may be changedby increasing either the frequency of the clock or the phase wordstored in the accumulator, i.e.,

PW(10)

where PW is the phase word stored in the accumulator andis the number of phase bits, 9 of which were used in this de-sign to ensure that the SFDR was not limited by phase resolu-tion. Mixed-signal simulations of the circuit with a phase ac-

Fig. 4. Simulation results showing the output waveform for three currentsource bias voltages.

cumulator and XOR gates implemented in Verilog and a phaseDAC with a settling time of 10 ns were used to simulate thechange of the output frequency. As the phase word is increased,the dominant harmonics of the clock alias spur began to con-structively interfere with the dominant harmonics of . Forexample, there was degradation in SFDR to 48 dBc when thephase word was increased to 51 with MHz

MHz , while at MHz and PWMHz , there was no degradation in SFDR. Therefore, in-

creasing by increasing the phase word degrades the SFDRmore than increasing by increasing the clock frequency.This is expected, as increases in the phase word cause largervoltage changes at the gates of the current switches as wellas faster changes, while increases in the clock rate only in-crease the frequency of changes and not the magnitude. With

MHz, the SFDR was maintained at 50 dBc up to1 MHz and degraded to 40 dBc by MHz.

IV. MEASUREMENT RESULTS

The simulated interpolating circuit has been manufacturedusing the AMS 0.35- m CSX process. To test the performanceof these circuits, an analog input voltage that represents thephase of the output signal was generated using one channel ofan Agilent 4155B semiconductor parameter analyzer. A secondchannel generated the gate bias voltage for all the unit currentsources, while another channel was used to measure the outputcurrent from the circuit. The various reference voltages weregenerated using a PowerDAQ PDIO-210 that was supplied byUnited Electronic Industries and controlled by the same AgilentVEE software used to control the Agilent 4155B. The outputdata for different current source bias voltages were transferredfrom the Agilent 4155B into a personal computer (PC). Matlabwas then used to calculate the spectrum of each response and todetermine the magnitude of the dominate spurs in the spectrum.Results from one circuit at different bias voltages (Fig. 6) shows

MCEWAN AND COLLINS: DIRECT DIGITAL-FREQUENCY SYNTHESIS 1297

Fig. 5. Microphotograph of the manufactured chip. To minimize bias-voltagedrop, the entire circuit was covered in the top metal layer, which obscures thetransistors from view; however, the photo compares the size of the circuit to atypical bond pad, illustrating the compactness of the circuit.

Fig. 6. Relative output power of several important harmonics of the output fre-quency at different current source bias voltages.

that at low bias voltages, the dominant spur is the fifth harmonic.As the bias voltage increases, the SFDR of the output improvesas the power in the fifth harmonic reduces. However, eventually,a different harmonic becomes dominant, and the SFDR of thesystem is maximum at an optimum bias voltage. For the partic-ular circuit whose results are shown in Fig. 6, the optimum biaspoint occurs at a voltage that is slightly less than 0.9 V, and atthis bias voltage, the SFDR of the output signal is better than

50 dBc.Results from all the sample circuits provided by the manu-

facturer are shown in Fig. 7. As expected, differences betweenthe effects of device mismatch in different circuits mean thateach circuit has a slightly different response. Despite these vari-ations, the trends in the dominant harmonic shown in Fig. 7 arequite similar for different circuits. The largest differences be-tween the circuits occur in the optimum bias-voltage range of0.8–1.0 V. In this range, a combination of process and parametervariations means that the dominant harmonic varies between cir-cuits. Most dramatically, the spectral purity of the output of two

Fig. 7. Relative power of the dominant spurious output of all the availablesample circuits at different current source bias voltages.

of the circuits is limited by a larger-than-expected second-har-monic component caused by parameter variations within thesecircuits. Although this suggests that further improvements to thedesign could be made, the overall conclusion from these resultsis that these circuits have an estimated yield of 70% for sys-tems with an SFDR of better than 50 dBc at a bias voltage of0.87 V and a yield of 100% for an SFDR of better than 45 dBc.The yield measurement results show that with careful design tomatch the transistors in the circuit, the conversion from phaseto amplitude is achieved to the accuracy needed for an SFDR ofbetter than 45 dBc.

To facilitate higher frequency measurements, an OPA655 am-plifier was used to amplify the output voltage so that its spec-trum could be measured using an HP8590L spectrum analyzer.The input to the interpolating circuit was generated using thememory in an Agilent 33250A function generator to create ananalog phase signal that emulates the output of the accumulatorand the phase DAC at high frequencies. Since it takes at least1 s to output all 65536 B of this memory, a high frequencycould only be emulated by storing more than one cycle of theoutput signal in this memory. Using this technique, the effec-tive clock frequency is limited to less than 100 MHz by the200 Msa/s output rate of the function generator. The amplituderesolution of the function generator was 8 bits, which limitsthe following measurements to 48 dBc due to phase trunca-tion. The results obtained using this equipment showed that witha signal equivalent to a clock frequency between 1 kHz and1 MHz, the spectral purity of the output signal was consistentat 48 dBc and hence is limited by the measuring equipment.However, when the function generator output represents clockfrequencies of 10 and 50 MHz, the SFDR of the output from theinterpolating circuit reduced to 40 and 36 dBc, respectively.

These results are worse than simulations, and the discrepancyis probably due to parasitic impedances not included in the sim-ulations, such as bond wires, the chip socket, PCB tracks, andcables. The settling time of the phase DAC is the same propor-tion of the clock period for MHz in the measure-ment and 50 MHz in the simulation. Hence, with theavailable equipment, the measurement was frequency limited to

MHz with an SFDR of 40 dBc. However, with an

1298 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006

TABLE ICOMPARISON WITH STATE-OF-THE-ART COMPACT DDFS

integrated 9-bit phase DAC, a 50 dBc SFDR at MHzis expected.

It is difficult to compare this system with state-of-the-artDDFS systems, as most previous systems target communi-cation applications at higher frequencies (Table I). However,the power and area savings from using the compact systempresented here are improvements on similar systems; hence,this system is particularly attractive for arrays of synthesizersfor use in integrated microsystems.

In the developed circuit, only the nonlinear interpolator isrealized. Phase accumulator, DAC, and reference and biasvoltages are not realized and are all emulated by using anexternal testing equipment. In an integrated system, the non-ideality of linear DAC will degrade spurious performances.Moreover, reference and bias voltages would be generatedby using on-chip circuitry with mismatch/nonuniformity, re-sulting in SFDR degradation. The silicon area and the powerdissipation in Table I do not include the required componentsfor the system shown in Fig. 1, which are a 9-bit accumulatorand an 8-bit linear phase DAC. As a first-order estimate, thesecomponents would add approximately 0.01 mW/MHz and 0.01mm [4], [21] and hence dominate the required silicon areaand power dissipation. Including these figures, the performancestill compares favorably with the state of the art in Table I, as[2], [4], and [20] do not include an output DAC.

V. CONCLUSION

A new ROM-less DDFS architecture has been proposed. Thecritical novel component of this architecture is a simple analogcircuit whose output current represents the amplitude that corre-sponds to a phase represented by an input voltage. Results thatshow that despite device and process variations, this simple verycompact circuit is capable of generating an output signal withan SFDR that is better than 40 dBc and as good as 50 dBcwith clock frequencies of up to 50 MHz have been presented.This level of performance makes the new architecture unsuit-able for use in wireless communications systems, which are thetarget application of previous DDFS systems. However, thereare other emerging applications, including resonant microme-chanical sensors and dielectrophoretic cell sorting and charac-terization systems, for which this system appears to be ideal.

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