DisplayPort Transmit Reference Designxilinx.eetrend.com/files-eetrend-xilinx/download/201401/...Creating and Executing the DisplayPort Source Design XAPP1178 (v1.0) September 13, 2013

XAPP1178 (v1.0) September 13, 2013 www.xilinx.com 1

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Summary This reference design demonstrates the implementation of a LogiCORE IP DisplayPort system that includes policy maker features and a DisplayPort controller. Audio and video pattern generators are used to generate the traffic for testing. The reference design is created and built using the Vivado™ Design Suite 2013.2. Instructions are included for building the hardware and testing the design on the board with the provided C source code. Complete Vivado Design Suite and Xilinx Software Development Kit (SDK) project files are provided with the reference design to allow you to examine and rebuild the design or to use it as a reference for starting a new design.

Introduction This application note describes how to implement a DisplayPort transmit system and how to bring up the source core through the initialization steps such as training the main link, setting up the source core registers and monitoring and taking appropriate action on HPD assertion. It showcases a system transporting video and audio data from the Xilinx DisplayPort transmit core to a DisplayPort capable monitor. A DisplayPort source policy maker is implemented on the KC705 Evaluation Board, which includes the MicroBlaze™ processor, and DisplayPort core, as well as video and audio pattern generators. The block diagram of the reference design is shown in Figure 1.

The source policy maker is implemented as an application running on the MicroBlaze processor. The reference design includes the following features:

• Designed with the VESA DisplayPort Specification v1.2

• Dynamic, switchable lane rates: 1.62, 2.7 or 5.4 Gbps

• Variable lanes: 1, 2 or 4 lanes

Application Note: Kintex-7 Family

XAPP1178 (v1.0) September 13, 2013

DisplayPort Transmit Reference DesignAuthor: Vamsi Krishna, Saambhavi Baskaran

X-Ref Target - Figure 1

Figure 1: Reference Design Block Diagram

http://www.xilinx.com

Hardware Implementation


• A wide range of resolutions

• Enable or disable secondary channel audio during runtime

• Change the bits-per-color dynamically when the lane is up

• One/two/four pixel-wide video interface option

• AUX operations logging for debugging purpose

Hardware Implementation

Figure 2 shows the hardware architecture of the reference design. The design uses the Vivado Design Suite IP integrator tool, a block-based design, and assembly tool. The Vivado IP Integrator (IPI) is used to integrate many of the key blocks of the design into a subsystem. The Vivado IPI subsystem consists of the MicroBlaze processor, AXI interconnect IP, MIG 7-series IP and other AXI4-Lite peripherals. The IPI sub-system is integrated in the top module along with DisplayPort IP and custom design sources for video pattern generator, audio pattern generator and video clock generator. The MicroBlaze processor changes the DisplayPort core configuration over the AXI4-Lite interface based on the user application.

Clocking The DisplayPort uses the following clock domains:

• The processor and the AXI domain operate at 50 MHz.

• Jitter Attenuated Clock source Si5326 on KC705 provides a 135 MHZ reference clock for the transceivers. A clock of frequency 135 MHz from the clocking wizard is given as input to Si5326 for jitter attenuation. The jitter attenuated clock is then routed as a reference clock to the transceivers in DisplayPort.

• Audio clock operates at 22.5792 MHz (512 * 44.1 KHz) sourced from the Programmable User clock source - Si570, programmed through AXI IIC interface.


Figure 2: Hardware Architecture


Pattern Generators


• Transmit video clock is generated using MMCM from the link clock. Its configuration is programmed using DRP ports for various video modes.

Pattern Generators

The video pattern generator has an APB bus interface that is connected to the AXI APB Bridge for processor communication. The registers available in the video pattern generator are listed in Table 7. The video timing information is programmed by writing into the registers. Eight standard pixel patterns can be generated by the module.

• Vesa LLC pattern

• Vesa pattern three bars

• Vesa color squares

• Flat red

• Flat blue

• Flat green

• Flat yellow

• Color bars

The audio pattern generator produces a 2 KHz sine wave at a sampling rate of 44.1 KHz with silence in between for a few seconds in two channels.

DisplayPort Transmit Core Customization

The MicroBlaze processor interfaces with the DisplayPort core through the AXI4-Lite interface, which is brought out as an external interface of the IPI design and connected to the DisplayPort core in the top-level RTL source file.

The S/PDIF controller generated with the DisplayPort is disabled and the audio streaming signals of the DisplayPort Source are connected to the audio pattern generator. The audio is disabled by default in the application and you are given the option in the User Console to enable/disable the audio transmission.

The DisplayPort PHY is customized to use the bi-directional AUX channel interface signals: aux_tx_io_p and aux_tx_io_n. The four transceivers for the four high-speed lanes are mapped to the four GTX transceivers in the FMC HPC (MGT_BANK_118) on the KC705 board. The software application gives you the option to select fewer numbers of lanes (1 or 2 lanes) to be used.

Software Implementation

The reference design includes a software application running on a MicroBlaze processor to initialize and maintain the DisplayPort link. This application provides an interactive UART console through which you can test the system at different modes of operation. You are given the flexibility to debug the application by reading/writing to the DisplayPort AUX registers.

Figure 3 shows the software flow of the standalone application.


Software Implementation


Initialization

In the first stage, the IIC and Timer peripherals are initialized. The IIC interface is used to initialize the clock sources: programmable oscillator Si570 and jitter attenuator Si5326 on the KC705 board.

The DisplayPort source core is set up and initialized in the following sequence.

1. Keep the physical layer (PHY) in reset

2. Disable transmitter

3. Set clock divider

4. Set DisplayPort clock speed

5. Bring the PHY out of reset

6. Wait for PHY to be ready

7. Enable transmitter

8. Enable the interrupt mask for HPD

HPD Event Handling

The software identifies the HPD event by reading the interrupt status register and interrupt signal state register of the source core. The HPD status is polled every 100 ms by the processor. On detecting a hot-plug event, the software initiates link training. When a hot-unplug event is detected, the main link is disabled and the software continues to poll the registers for any change in HPD status. On occurrence of the HPD interrupt, the link status is checked and retraining is performed, if required. Figure 4 is a flow diagram for HPD event handling.


Figure 3: Standalone Application Flow


Hardware and Software Requirements


Upon plugging the sink device or on HPD interrupt, the source core starts to read the sink receiver capabilities field for the maximum supported lane bandwidth and lane count. The source core sets this as the default configuration for link training. The video timing format is determined by checking the capability of the sink device through an EDID (Extended Display Identification Data) read. If the EDID is corrupted, the software falls back to a default video timing format of 640x480 at 60 Hz.

Link Training

See the LogiCORE IP DisplayPort Product Guide (PG064) [Ref 3] for the detailed steps of the training procedures and VESA DisplayPort Standard specification document [Ref 4]. Link training consists of two distinct sequential tasks: clock recovery (training procedure 1 in [Ref 4]) followed by channel equalization (training procedure 2 in [Ref 4]). When both the tasks are complete, the training is turned off and scrambling is enabled. If the training fails, the procedure is repeated for a maximum of five times. When the link is trained successfully, the main link is enabled.

Hardware and Software Requirements

This reference design requires the following hardware:

• Kintex-7 KC705 board and power supply

• Tokyo Electron Device Limited FMCH-DP module (Used for initial testing. Contact Tokyo Electron Device Limited for FMC updates)http://solutions.inrevium.com/products/pdf/pdf_TB-FMCH-DP_HWUserManual_2.01e.pdf

• Platform cable USB JTAG programmer

• DisplayPort cable


Figure 4: HDP Event Handling


http://solutions.inrevium.com/products/pdf/pdf_TB-FMCH-DP_HWUserManual_2.01e.pdf

Creating and Executing the DisplayPort Source Design


• Monitor

• USB cable with standard-A plug to host computer and mini-B plug to KC705 board for Serial Communication

• Xilinx Vivado Design Suite 2013.2

• Xilinx Software Development Kit 2013.2


This section describes how to build the reference design and run the design on the KC705 board.

Before beginning, unzip the reference design into a local folder (referred to as XAPP1178 in the rest of the steps).

Start a New Vivado Project

This section details the steps to start a new Vivado project.

1. Install the Vivado Design Suite 2013.2.

2. Open the Vivado Design Suite.

3. Select Create New Project.

4. Click Next in the Create a New Vivado Project window.

5. Enter the project name “dp_src_pm_v1_0” and select a directory for the project. The selected directory is referred to as <user_dir> in the rest of the steps.

6. Select RTL Project in the Project Type window.

7. Click Next in the Add Sources window to create an empty project.

8. Click Next in the Add Existing IP window to create an empty project.

9. Click Next in the Add Constraints window.


Figure 5: Add Sources to Create Empty Project




10. Select Boards in the Specify column in the Default Part window and select Kintex-7 KC705 Evaluation Platform.

11. View the Project Summary and select Finish.

Adding the DisplayPort Core to Design1. Select IP Catalog on the left side of the Flow Navigator to bring up the IP catalog.

2. From the IP catalog, select Standard Bus Interfaces > DisplayPort > DisplayPort (version 4.0). Right click and select Customize IP.

In the DisplayPort IDE, set the following:

• Protocol Selection: DisplayPort 1.2 Version

• Link Configuration Max Link Rate: 5.4

• Video Interface Configuration Max Bits per Color: 16

• Enable Audio Option: Checked

• Y Only Enable: Checked

The final configuration is shown in Figure 7. Select OK when the DisplayPort IP license is bought to generate the output products.


Figure 6: Default Part Selection




3. Click Generate in the Generate Output Products window. Do no select the Generate Synthesized Design Checkpoint option.

Creating a MicroBlaze Processor System in Vivado IP Integrator (IPI)1. After the output products are generated for the DisplayPort core, select Create block

design under IP Integrator in the Flow Navigator. Specify the design name as design_1 and click OK.

2. Add the IPs listed in Table 1 into the block design by right-clicking and selecting Add IP. The IPs can be customized by double-clicking on the instance. Some of the IPs in Table 1 are grouped into blocks (Processor Local Memory, AXI4-Lite peripherals, AXI4 Peripherals) for easier understanding.


Figure 7: Customize IP

Table 1: Adding IP Cores

Name of the IP (Instance Name) Configuration

Clocking Wizard (clk_wiz_1) • clk_out1 frequency: 200• Enable clk_out2 and set the frequency to 135• Enable clk_out3 and set the frequency to 50

MicroBlaze (microblaze_1) • Enable Use Instruction and Data Caches• Select Enable Barrel Shifter• Change Enable Integer Multiplier: MUL32• Select Enable Additional Machine Status

Register Instructions• Select Enable Pattern Comparator• Change Size of Instruction and Data Cache

feature: 16kB• Base Address: 0x80000000 • High Address: 0xFFFFFFFF• Select Enable Peripheral AXI Data

Interface




1. Connect the IPs listed in Table 1 as shown in Figure 8 through Figure 10. The IPs are grouped into hierarchies named local_memory, axi4_mm_peripherals and axi4_lite_peripherals and shown in Table 2, Table 3 and Table 4 respectively. The entire IPI design is shown in Figure 10. See Vivado Design Suite Tutorial (UG940) for a step-by-step tutorial for building a processor system in Vivado IP Integrator [Ref 2].

2. Figure 8 shows the block connections in the local_memory group. Connect the IPs as shown in Table 2.

Processor Local Memory (local_memory)

LMB BRAM Controller (lmb_bram_if_cntlr_1) Default

Local Memory Bus (lmb_v10_1) Default

Block Memory Generator (blk_mem_gen_1) Change Memory Type: True Dual Port RAM

LMB BRAM Controller (lmb_bram_if_cntlr_2) Default

Local Memory Bus (lmb_v10_2) Default

AXI4-Lite Peripherals (axi4_lite_peripherals)

AXI Interconnect (axi_interconnect_1) Change Number of Master Interfaces: 7

MicroBlaze Debug Module (mdm_1) Select Enable JTAG Uart

Proc Sys Reset (proc_sys_reset_1) Default

AXI Interrupt Controller (axi_intc_1) Default

Concat (xlconcat_1) Change Number of Ports: 5

AXI Uartlite (axi_uartlite_1) Default

AXI Timer 1 (axi_timer_1) Default

AXI IIC (axi_iic_1) Change General Purpose Output Width: 2

AXI APB Bridge (axi_apb_bridge_1) Change Number of Slaves: 1

AXI4 Peripherals (axi4_mm_peripherals)

AXI Interconnect (axi_interconnect_2) Change Number of Slave Interfaces: 2Change Number of Master Interfaces: 1

MIG 7 Series (mig_1) • In the customization IDE for MIG, review the Vivado Project Options and click Next.

• Select Verify Pin Changes and Update Design in the MIG Output Options tab and click Next.

• In the Load mig.prj and XDC File window, browse to the downloaded XAPP1178/DP_Tx_Xapp/mig_files/ and select the design_1_mig_1_0_mig_a.prj and dp_ipi_mig_1_0.xdc files and click Next. Click Validate in the window that appears next.

• Review the information in the following windows and generate the IP.

• As an alternative, see KC705 MIG Design Creation with Vivado (XTP196) to create a custom MIG instance [Ref 1].

Table 1: Adding IP Cores (Cont’d)

Name of the IP (Instance Name) Configuration




a. After the connections are complete, select the blocks (lmb_v10_1,2, lmb_bram_if_cntlr_1,2 and blk_mem_gen_1) and create a hierarchy and name it “local_memory”.

Note: Two or more IPs could be grouped into a hierarchy by selecting the IPs (ctrl + click) and right-clicking and selecting Create Hierarchy.

3. Connect the blocks for the AXI4 peripherals as detailed in Table 3.

Table 2: Local Memory Block Connections

Point A Point B

Instance name Interface /Block Pin Name Instance name Interface /

Block Pin Name

lmb_v10_1 LMB_SI_0 lmb_bram_if_cntlr_1 SLMB

lmb_v10_2 LMB_SI_0 lmb_bram_if_cntlr_2 SLMB

lmb_bram_if_cntlr_1 BRAM_PORT blk_mem_gen_1 BRAM_PORTA

lmb_bram_if_cntlr_2 BRAM_PORT blk_mem_gen_1 BRAM_PORTB

microblaze_1 DLMB lmb_v10_1 LMB_M

microblaze_1 ILMB lmb_v10_2 LMB_M

clk_wiz_1 clk_out3 lmb_v10_1 LMB_Clk

lmb_v10_2

lmb_bram_if_cntlr_1

lmb_bram_if_cntlr_2

proc_sys_reset_1 bus_struct_reset lmb_v10_1 SYS_Rst

lmb_v10_2

lmb_bram_if_cntlr_1 LMB_Rst

lmb_bram_if_cntlr_2


Figure 8: Local Memory Connections in IP Integrator




a. Create a group named "axi4_mm_peripheral" by selecting the mig_7series_1 instance, right-clicking and selecting Create hierarchy.

4. Table 4 details the connections of AXI4-Lite peripherals. Alternatively, after the connections are done, select the IPs (Proc Sys Reset, AXI Timer, Concat, AXI APB Bridge, AXI Interrupt Controller, AXI IIC, MDM and AXI UART Lite) and create a hierarchy named axi4_lite_peripherals. Figure 9 shows the connections inside the hierarchy.

Table 3: AXI4 Block Connections

Point A Point B

Instance name Interface /Block Pin Name Instance name Interface /

Block Pin Name

microblaze_1 M_AXI_DC axi_interconnect_2 S00_AXI

M_AXI_IC S01_AXI

axi_interconnect_2 M00_AXI mig_7series_1 S_AXI

External ports sys_clk_p sys_clk_p

sys_clk_n sys_clk_n

sys_rst sys_rst

DDR3 DDR3

proc_sys_reset_1 peripheral_aresetn mig_7series_1 aresetn

clk_wiz_1 clk_out3 axi_interconnect_2 S00_ACLK, S01_ACLK

mig_7series_1 ui_clk axi_interconnect_2 ACLK, M00_ACLK

clk_wiz_1 clk_in1

ui_clk_sync_rst proc_sys_reset_1 ext_reset_in

clk_wiz_1 reset

proc_sys_reset_1 interconnect_aresetn axi_interconnect_2 ARESETN

peripheral_aresetn S00,S01,M00_ARESETN

Table 4: AXI4-Lite Connections

Point A Point B

Instance Name Interface / Block Pin Name

Instance Name / External Port

Interface / Block Pin Name

proc_sys_reset_1

interconnect_aresetn

axi_interconnect_1

ARESETN

peripheral_aresetn

S00,M00,M01,M02,M03,M04,M05,M06_ARESETN

axi_intc_1 s_axi_aresetn

mdm_1 s_axi_aresetn

microblaze_1 s_axi_aresetn

axi_timer_1 s_axi_aresetn

axi_uartlite_1 s_axi_aresetn

axi_iic_1 s_axi_aresetn

axi_apb_bridge_1 s_axi_aresetn




clk_wiz_1 clk_out3

axi_interconnect_1 All Clk pins

axi_intc_1 s_axi_aclk, processor_clk

mdm_1 s_axi_aclk

microblaze_1 Clk

axi_timer_1 s_axi_aclk

axi_uartlite_1 s_axi_aclk

axi_iic_1 s_axi_aclk

proc_sys_reset_1 slowest_sync_clk

axi_apb_bridge_1 s_axi_aclk

proc_sys_reset_1 mb_resetaxi_intc_1 processor_rst

microblaze_1 Reset

clk_wiz_1 locked proc_sys_reset_1 dcm_locked

mdm_1 Debug_SYS_Rst proc_sys_reset_1 mb_debug_sys_rst

xlconcat

In0 axi_uartlite_1 interrupt

In1 external Port Dp_Int

In2 axi_timer_1 interrupt

In3 mdm_1 interrupt

In4 axi_iic_1 iic2inctc_irpt

dout axi_intc_1 intr

axi_interconnect_1

M00_AXI axi_intc_1 s_axi

M01_AXI axi_uartlite_1 s_axi

M02_AXI axi_apb_bridge_1 s_axi

M03_AXI axi_timer_1 s_axi

M04_AXI mdm_1 s_axi

M05_AXI external Port M05_AXI

M06_AXI axi_iic_1 s_axi

axi_intc_1 interrupt microblaze_1 INTERRUPT

mdm_1 MBDEBUG_0 microblaze_1 DEBUG

axi_apb_bridge_1 apb_m external Port apb_m

axi_uartlite_1 uart external Port uart

axi_iic_1iic external Port iic2inctc_irpt

gpo[1:0] external Port gpo[1:0]

Table 4: AXI4-Lite Connections (Cont’d)

Point A Point B

Instance Name Interface / Block Pin Name

Instance Name / External Port

Interface / Block Pin Name




The complete design is shown in Figure 10.

5. Save the current block design.


Figure 9: AXI4-Lite Connections in IP Integrator


Figure 10: All Block Connections in IP Integrator




6. In the address editor tab, change the base address and high address of the IPs as listed in Table 5.

7. Save the changes in the block design.

Importing Other HDL files to the Project1. Import all the HDL files from the directories patgen, vid_clk_drp and wrappers

available in XAPP1178/DP_Tx_Xapp/design_files/, by selecting Add Sources in the Flow Navigator window. Press Ctrl+Q to open the Flow Navigator window if it is not already visible.

2. The DisplayPort IP delivers some RTL files for customization. For this project, displayport_0.v, displayport_v4_0.v and displayport_v4_0_tx_phy.v need to be edited. You can replace these files with the files available in XAPP1178/DP_Tx_Xapp/design_files/displayport.

3. Once the DisplayPort source files are edited, right-click inside the Sources window and select Refresh Hierarchy.

XDC Constraints1. From the Flow Navigator, select Add Sources and point to the constraints file at

XAPP1178/DP_Tx_Xapp/ design_files /constraint/ dp_src_pm_v1_0.xdc.

2. Save the design.

Generating the Bitstream 1. From the Flow Navigator window, select Generate Bitstream.

2. Once the bitstream generation is complete, the hardware platform is exported to SDK.

a. In the sources window, identify the block design named design_1 and open it by double-clicking on it.

b. Right-click on the block design (design_1) and select Export Hardware for SDK. Provide a directory location (for example, <user_sdk_workspace>) for the SDK workspace in the Export Hardware for SDK window and select Launch SDK.

Table 5: Base and High Addresses

Instance Names in/microblaze_1 Offset Address Range High Address

Data

lmb_bram_if_cntlr_1 0x00000000 64K 0x0000FFFF

axi_intc_1 0x41200000 64K 0x4120FFFF

axi_timer_1 0x41C00000 64K 0x41C0FFFF

axi_uartlite_1 0x40600000 64K 0x4060FFFF

mdm_1 0x41400000 64K 0x4140FFFF

mig_1 0x80000000 1G 0xBFFFFFFF

axi_iic_1 0x40800000 64K 0x4080FFFF

M05_AXI 0x44A00000 64K 0x44A0FFFF

axi_apb_bridge_1 0x42000000 64K 0x4200FFFF

Instruction

lmb_bram_if_cntlr_2 0x00000000 64K 0x0000FFFF

mig_1 0x80000000 1G 0xBFFFFFFF




c. In SDK, create a new application project (File > New > Application project). Provide a project name, "dp_app", and click Next.

d. Finish by selecting Empty Application in the following window to create a new project.

e. Copy the source codes from the location XAPP1178/DP_Tx_Xapp/sdk_workspace/dp_app/src to <user_sdk_workspace>/dp_app/src and refresh the SDK application (File > Refresh).

f. Modify the linker script (Xilinx Tools > Generate linker script) to place the code, data and heap sections in mig_1 and modify the heap and stack size to 3.54 KB each.

g. After the linker script is generated, dp_app.elf is ready for download and can be located in the directory <user_sdk_workspace>/dp_app/Debug/dp_app.elf.

Hardware Setup:

1. Connect the Tokyo Electron Device Limited (TED) TB-FMCH-DP module to the HPC FMC connector on the KC705 board.

2. Connect a USB cable from the host PC to the USB UART port on the KC705 for serial communication.

3. Connect a DP cable from the TX port of the TED TB-FMCH-DP module to a monitor, as shown in Figure 11.

4. Connect the power supply cable and turn on the KC705 board.

5. Start a HyperTerminal program on the host PC with the following settings:

• Baud rate: 9600

• Data Bits: 8

• Parity: None

• Stop Bits: 1

• Flow Control: None


Figure 11: Hardware Setup


Display User Console


6. Connect the JTAG cable to the board.

7. In a command shell, change directories to<user_dir>/dp_src_pm_v1_0/dp_src_pm_v1_0.runs/impl_1 or XAPP1178/DP_Tx_Xapp/ready_for_download,where the bit file can be found.

8. Start the Xilinx Microprocessor Debugger (XMD) by typing xmd in the command prompt. Download the bitstream to the board.

%xmd%fpga -f dp_src_pm_v1_0.bitExit

9. Download and execute the software on board. The ELF file can be found in <user_sdk_workspace>/dp_app/Debug or XAPP1178/DP_Tx_Xapp/ready_for_download.

%cd <user_sdk_workspace>/dp_app/Debug%xmd%connect mb mdm%rst%stop%dow dp_app.elf%run

10. This starts the DisplayPort source policy maker software.


The hot-plug-detect and link training take place after the software is initialized/run. After the link is trained, the UART terminal input command processor is active. Press h to see the user console options. The functionality of each command in the console is described below.

• ; - Read the EDID from the DisplayPort Sink Device

This function displays the DisplayPort Configuration Data (DPCD) and Extended Display Identification Data (EDID) read from the sink device through the AUX channel and displays relevant information.

• b - Enable Logging of AUX Transactions

This command enables/disables the AUX log. When enabled, the policy maker software displays the AUX transaction on the console.

• c - Run Compliance Test Routines

This command provides options for compliance testing, including link training at various rates and lane counts, pattern type, and bits per colors. The command displays a sub-menu with the options described in Table 6.

Table 6: Console Commands

Keystroke Command

1 Trains link @ 1.62G 1 lane

2 Trains link @ 1.62G 2 lanes










• d - Display MSA for TX

This command displays the main stream attributes such as resolution, and user pixel width.

• g- Run standard adaptive training sequence

This command runs link training with the default configuration.

• h - Display Help Menu

This command displays the help menu.

• s - Display DPCD Status and Training Configuration

This command displays the training information and configuration data of the DisplayPort monitor connected to the source port.

• 1 - Adjust TX Voltage Swing

This command prompts you to change the voltage swing setting of the PHY module.

• 2 - Adjust TX Pre-emphasis

This command prompts you to change the required pre-emphasis setting of the PHY module.

• A - Read from SRC registers

Enables you to read from the registers of DisplayPort source core.

• B-Write to SRC registers

Enables you to write into the DisplayPort source core registers.

• C - Read from Video Pattern Generator Registers

This command is used to read from the register space of video pattern generator. The register space of the video pattern generator is shown in Table 7.

• D - Write to Video Pattern Generator registers


b Sets bits per color:• 0 - Sets 6 bits per color• 1 - Sets 8 bits per color• 2 - Sets 10 bits per color• 3 - Sets 12 bits per color• 4 - Sets 16 bits per color

m Sets video resolution. Displays a sub-menu with resolution options. Choose a resolution by pressing the corresponding 2 hexadecimal indices from the sub-menu.

p Sets video pattern:• 0 - Color Bars• 1 - Vesa LLC pattern• 2 - Vesa Pattern3 bars• 3 - Vesa Color square• 4 - Flat Red screen• 5 - Flat Green screen• 6 - Flat Blue screen• 7 - Flat Yellow screen

V Reads DPCD Register Space

X Prints Frame CRC Values

Table 6: Console Commands (Cont’d)

Keystroke Command




This command is used to read from the register space of video pattern generator. The register space of the video pattern generator is shown in Table 7.

• S - Enable Audio

With this command, you can reprogram the source audio registers.

• T - Disable Audio

This command disables the audio output.

• R - Read AUX Register

This command allows the user to read the sink's register space over the AUX channel. The input is the 16-bit address and is formatted as four hexadecimal characters.

• W - Write AUX Register

This command allows you to write to the sink's register space over the AUX channel. The input is the 16-bit address and is formatted as four hexadecimal characters.

• x - Exit the application

This function exits the application loop and returns to main. The processor remains in an infinite loop in main and does nothing more at this point.

• / - Clear the screen

Table 7: Pattern Generator Registers

Address Read/Write Description

0x000 R/W Bit 0 = Enable video output.

Bit 1 = SW reset of the pattern generator.

0x004 R/W Bit 0 = VSYNC polarity.

0x008 R/W Bit 0 = HSYNC polarity.

0x00C R/W Bit 0 = DE polarity.

0x010 R/W Bits 8:0 = VSYNC width.

0x014 R/W Bits 8:0 = Vertical back porch.

0x018 R/W Bits 8:0 = Vertical front porch.

0x01C R/W Bits 10:0 = Vertical resolution.

0x020 R/W Bits 8:0 = HSYNC width.

0x024 R/W Bits 8:0 = Horizontal back porch.

0x028 R/W Bits 8:0 = Horizontal front porch.

0x02C R/W Bits 10:0 = Horizontal resolution.

0x104 R/W Bits 7:0 = TX Video clock M value. Used for video clock synthesis. Video_clock = lnk_clk * M/D.

0x108 R/W Bits 7:0 = TX Video clock D value. Used for video clock synthesis. Video_clock = lnk_clk * M/D.

0x200 R Bits 11:0 = VSYNC counter current count.

0x204 R Bits 11:0 = HSYNC counter current count.

0x208 R Bits 11:0 = Data enable counter current count.


Directory Structure


Directory Structure

This section shows the directory structure of the design files provided along with the application note. All files are in the DP_Tx_Xapp folder.

• design_files

• constraint: XDC file needed for the project.

• displayport: Customized wrapper files for DisplayPort IP.

• patgen: Verilog files needed for the project.

• vid_clk_drp: Verilog files needed for the project.

• wrappers: Verilog files needed for the project.

• dp_src_pm_v1_0: Vivado project directory.

• ready_for_download: Contains BIT and ELF files to be downloaded on the board.

• sdk_workspace: Contains the source files for the policy maker software.

• mig_files: Contains the PRJ and XDC files needed to configure the MIG-7 series IP.

Troubleshooting This section provides debugging steps for issues in the policy maker software.

To know the current status of the link, read the DPCD status by typing s in the help menu. If the link is not trained, the log shows the individual status of the different training procedures. Values from the DisplayPort registers 0x0100-0x0107 and 0x0204 - 0x0207 are shown for advanced debugging purposes.

References 1. KC705 MIG Design Creation with Vivado (XTP196)

2. Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940)

3. LogiCORE IP DisplayPort Product Guide (PG064)

4. VESA DisplayPort Standard Specification

Revision History

The following table shows the revision history for this document.

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Date Version Description of Revisions

09/13/13 1.0 Initial Xilinx release.

http://www.xilinx.com/support/documentation/boards_and_kits/kc705/2013_2/kc705-mig-xtp196-2013.2-c.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug940-vivado-tutorial-embedded-design.pdf

http://www.xilinx.com/cgi-bin/docs/ipdoc?c=displayport;v=latest;d=pg064-displayport.pdf


http://www.displayport.org/

http://www.xilinx.com/warranty.htm

Notice of Disclaimer


fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability foruse of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.


http://www.xilinx.com/warranty.htm#critapps

Documents

DisplayPort Transmit Reference Designxilinx.eetrend.com/files-eetrend-xilinx/download/201401/...Creating and Executing the DisplayPort Source Design XAPP1178 (v1.0) September 13, 2013