Distributed Shared Memory CIS825 Project Presentation

04/22/2304/22/23 Distributed Shared MemoryDistributed Shared Memory 11

Distributed Shared MemoryDistributed Shared Memory

CIS825 Project PresentationCIS825 Project Presentation

Sathish R. YennaSathish R. Yenna Avinash PonugotiAvinash PonugotiRajaravi KollarapuRajaravi Kollarapu Yogesh BharadwajYogesh BharadwajSethuraman SubramanianSethuraman Subramanian Nagarjuna NagulapatiNagarjuna NagulapatiManmohan UttarwarManmohan Uttarwar


Distributed Shared MemoryDistributed Shared Memory

1.1. IntroductionIntroduction2.2. Consistency modelsConsistency models3.3. Sequential consistencySequential consistency4.4. PRAM consistencyPRAM consistency5.5. Release consistencyRelease consistency6.6. Final SystemFinal System7.7. Performance EvaluationPerformance Evaluation


IntroductionIntroduction

What is shared memory?What is shared memory?

- Memory location or object accessed by two or more - Memory location or object accessed by two or more different processes running on same machinedifferent processes running on same machine

- A mechanism is to be defined for the access of the shared - A mechanism is to be defined for the access of the shared location, otherwise unpredicted states will resultlocation, otherwise unpredicted states will result

- Many operating systems provide various mechanisms to - Many operating systems provide various mechanisms to avoid simultaneous access of the shared memoryavoid simultaneous access of the shared memory

For example: semaphores, monitors etc..For example: semaphores, monitors etc..


Ex: Consider the Reader/Writer Problem:Ex: Consider the Reader/Writer Problem:We have a shared buffer into which writer writes and reader We have a shared buffer into which writer writes and reader reads form the values from the same.reads form the values from the same.

For avoiding writing on existing value and reading the same For avoiding writing on existing value and reading the same twice, we need to have a mechanism.twice, we need to have a mechanism.

We have semaphore/monitors provided by OS to avoid We have semaphore/monitors provided by OS to avoid simultaneous access.simultaneous access.

What if writer is writing from one machine and reader is reading What if writer is writing from one machine and reader is reading from another machine???from another machine???

MemoryWriter Reader


What is Distributed shared memory?What is Distributed shared memory?

- Memory accessed by two or more processes running on - Memory accessed by two or more processes running on different machines connected via a communication networkdifferent machines connected via a communication network

Formal Definition:Formal Definition:

A Distributed Shared Memory System is a pair (P,M) A Distributed Shared Memory System is a pair (P,M) where P is a set of N processors { Pwhere P is a set of N processors { P11, P, P22, P, P33, . . . P, . . . Pn n } and M is } and M is a shared memory.a shared memory.

Each process PEach process Pii sequentially executes read and write sequentially executes read and write operations on data items in M in the order defined by the operations on data items in M in the order defined by the program running on it.program running on it.


- DSM improves the performance of the whole systemDSM improves the performance of the whole system

- An abstraction like DSM simplifies the application programmingAn abstraction like DSM simplifies the application programming BUTBUT

- - The main problem is how to keep the memory consistentThe main problem is how to keep the memory consistent

- We don’t have traditional semaphores or monitors to control the We don’t have traditional semaphores or monitors to control the accesses in DSMaccesses in DSM

- We can implement by keeping the memory at a central location and We can implement by keeping the memory at a central location and allowing processes at different machines to accessallowing processes at different machines to access

- We can only use the message transmission as an aid to control the We can only use the message transmission as an aid to control the accessesaccesses


- But networks are slow, so for performance improvement, we have But networks are slow, so for performance improvement, we have to keep various copies of the same variable at various machinesto keep various copies of the same variable at various machines

- Maintaining perfect consistency (i.e., Any read to a variable x Maintaining perfect consistency (i.e., Any read to a variable x returns the value stored by the most recent write operation to x) returns the value stored by the most recent write operation to x) of all the copies is hard and results in low performance as the of all the copies is hard and results in low performance as the processes are on different machines communicating over a slow processes are on different machines communicating over a slow networknetwork

- The solution is to accept less than perfect consistency as the The solution is to accept less than perfect consistency as the price for better performanceprice for better performance

- Moreover many application programs don’t require strict Moreover many application programs don’t require strict consistencyconsistency

Because of all these reasons many consistency models were Because of all these reasons many consistency models were defineddefined


Consistency ModelsConsistency Models

A consistency model is essentially a contract A consistency model is essentially a contract between the software and the memory. If the between the software and the memory. If the software agrees to obey certain rules, the software agrees to obey certain rules, the memory promises to work correctly.memory promises to work correctly.

In our project we are implementing three of In our project we are implementing three of them:them:

- Sequential consistency- Sequential consistency- PRAM consistency- PRAM consistency- Release consistency- Release consistency


Sequential ConsistencySequential Consistency

A system is sequentially consistent if the result of the A system is sequentially consistent if the result of the any execution is the same as if any execution is the same as if

- the operations of all the processors were - the operations of all the processors were executed executed in some sequential order, and in some sequential order, and

- the operations of each individual processor - the operations of each individual processor appear appear in this sequence in the order specified by in this sequence in the order specified by its its program. program.


-- When processes run in parallel on different machines, any When processes run in parallel on different machines, any valid interleaving is acceptable behavior, valid interleaving is acceptable behavior, but all processes but all processes must see the same sequence of memory referencesmust see the same sequence of memory references..

-- Note that nothing is said about time; that is no reference to Note that nothing is said about time; that is no reference to the “most recent” store.the “most recent” store.

-- It merely guarantees that all processes see all memory It merely guarantees that all processes see all memory references in the same order.references in the same order.

-- Two possible results of the same programTwo possible results of the same program

P1:P1: W(x)1W(x)1 P1:P1: W(x)1W(x)1--------------------------------- --------------------------------------------------------------------- ------------------------------------P2:P2: R(x)0R(x)0 R(x)1R(x)1 P2:P2: R(x)1R(x)1R(x)1R(x)1


ImplementationImplementation

Brown’s Algorithm:Brown’s Algorithm:

Each Process has a queue INEach Process has a queue INii of invalidation requests of invalidation requests

W( x) v: Perform all invalidations in IN queue. W( x) v: Perform all invalidations in IN queue. Update the main memory and cache. Update the main memory and cache. Place invalidation requests in IN queue of each Place invalidation requests in IN queue of each process. process.

R( x): If x is in cache then read it from cacheR( x): If x is in cache then read it from cache ElseElse

Perform all invalidations in INPerform all invalidations in INii Read from the main memoryRead from the main memory


Problems with Brown’s ImplementationProblems with Brown’s Implementation

- All the three operations in W( x) v i.e., updating cache, All the three operations in W( x) v i.e., updating cache, main memory and broadcasting invalid message should main memory and broadcasting invalid message should be done atomically.be done atomically.

- For ensuring the above atomicity, we will have to use For ensuring the above atomicity, we will have to use robust mechanism involving an agreement by all the robust mechanism involving an agreement by all the processes. There is lot of communication overhead processes. There is lot of communication overhead involved in ensuring this atomicity.involved in ensuring this atomicity.

- For a single write, we have N invalid messages being For a single write, we have N invalid messages being transmitted, where ‘N’ is the number of processes.transmitted, where ‘N’ is the number of processes.


Sequentially Consistent DSM ProtocolSequentially Consistent DSM Protocol- J. Zhou, M. Mizuno, and G. Singh- J. Zhou, M. Mizuno, and G. Singh

DSM System consists shared memory module (SMem DSM System consists shared memory module (SMem Manager) and local manager (Processor Manager) at Manager) and local manager (Processor Manager) at each machine. each machine.

Each Processor manager:Each Processor manager:- handles requests to read or write objects from - handles requests to read or write objects from

the the user processesuser processes- communicates with SMem manager. - communicates with SMem manager.

SMem manager:SMem manager:- processes request messages from processor- processes request messages from processor

managers to read or write objects. managers to read or write objects.


Protocol DescriptionProtocol Description SMem manages the following data structures: SMem manages the following data structures:

- Object memory : M[Object Range] - Object memory : M[Object Range]

- Two dimensional binary array : - Two dimensional binary array : Hold_Last_Write[Processor Range, Object Range] Hold_Last_Write[Processor Range, Object Range]

At any time T , At any time T , - Hold_Last_Write[i; x]=1 : object x in the cache at - Hold_Last_Write[i; x]=1 : object x in the cache at processor i holds a value written by the last- processor i holds a value written by the last- write write with respect to T , with respect to T ,

- Hold_Last_Write[i; x]=0 : object x in the cache at - Hold_Last_Write[i; x]=0 : object x in the cache at processor i does not hold a value written by processor i does not hold a value written by the the last-write with respect to T. last-write with respect to T.

Each element of Hold_Last_Write is initialized to 0. Each element of Hold_Last_Write is initialized to 0. Let us say ‘n’ processors and ‘m’ objects.Let us say ‘n’ processors and ‘m’ objects.


Each processor i maintains the following data structures: Each processor i maintains the following data structures:

One dimensional binary array : ValidOne dimensional binary array : Validii [Object Range] : [Object Range] : -- Valid-- Validii [x] = 1 : object x in the cache is valid [x] = 1 : object x in the cache is valid -- Valid-- Validii [x] = 0 : object x in the cache is not valid [x] = 0 : object x in the cache is not valid

Each element of ValidEach element of Validii is initialized to 0. is initialized to 0.

For each object x such that ValidFor each object x such that Validii [x] = 1, C [x] = 1, Cii [x] (C [x] (Cii [x] is [x] is cache memory to hold value of object x) cache memory to hold value of object x)


Operations at processor i Operations at processor i

Write(x; v):: Write(x; v):: send[write,x; v] to SMem; send[write,x; v] to SMem; receive[Invalid_array[1..m]] message from SMem; receive[Invalid_array[1..m]] message from SMem; ValidValidii [1..m] := Invalid_array[1..m]; //element wise [1..m] := Invalid_array[1..m]; //element wise // //assignmentsassignments CCii [x] := v; [x] := v;

Read(x):: Read(x):: if Validif Validii [x] = 0 then [x] = 0 then send[read,x] message to SMem; send[read,x] message to SMem; receive [v, Invalid_array[1..m]] from SMem; receive [v, Invalid_array[1..m]] from SMem; ValidValidii [1..m] := Invalid_array[1..m]; [1..m] := Invalid_array[1..m]; CCii [x] := v; [x] := v; endif endif return Creturn Cii [x]; [x];


Operations at SMem: Operations at SMem:

Process [write,x; v] message from processor i:: Process [write,x; v] message from processor i:: M [x] := v; M [x] := v; Hold_Last_Write[1..n; x] := 0; Hold_Last_Write[1..n; x] := 0; Hold_Last_Write[i; x] := 1;Hold_Last_Write[i; x] := 1;send [Hold_Last_Write[i; 1..m]] to processor i; send [Hold_Last_Write[i; 1..m]] to processor i; /*send processor i's row of Hold_Last_Write to i. /*send processor i's row of Hold_Last_Write to i. Processor i receives the row in Invalid array */Processor i receives the row in Invalid array */

Process [read,x] message from processor i:: Process [read,x] message from processor i:: Hold_Last_Write[i; x] := 1; Hold_Last_Write[i; x] := 1; send [M [x], Hold_Last_Write[i; 1..m]] to processor i; send [M [x], Hold_Last_Write[i; 1..m]] to processor i;

Each procedure is executed atomically. Each procedure is executed atomically.


Advantages of the SC-DSM Protocol Advantages of the SC-DSM Protocol byby J. Zhou, M. Mizuno, and G. SinghJ. Zhou, M. Mizuno, and G. Singh

The number of messages to be exchanged for read and write The number of messages to be exchanged for read and write operations is the same and requires considerably less.operations is the same and requires considerably less.

- A write operation requires one round of message - A write operation requires one round of message exchange between the processor and the shared exchange between the processor and the shared memory. memory.

- A read operation at a processor also requires one - A read operation at a processor also requires one round round of message exchange between the processor and of message exchange between the processor and the the shared memory if the object is not found in its local shared memory if the object is not found in its local

cache. cache.

The protocol does not require an atomic broadcast.The protocol does not require an atomic broadcast.

The protocol does not require any broadcast of messages.The protocol does not require any broadcast of messages.


Release ConsistencyRelease Consistency

Sequential and PRAM consistencies are Sequential and PRAM consistencies are restrictive. restrictive.

For the case when a process is reading or For the case when a process is reading or writing some variables inside a CS.writing some variables inside a CS.

Drawback:Drawback: No way for memory to differentiate between entering No way for memory to differentiate between entering

or leaving a CS.or leaving a CS. So, release consistency is introduced.So, release consistency is introduced.


Release ConsistencyRelease Consistency

Three classes of variables:Three classes of variables: Ordinary variablesOrdinary variables Shared data variables Shared data variables Synchronization variables: Acquire and Release (CS)Synchronization variables: Acquire and Release (CS)

DSM has to guarantee the consistency of the sharedDSM has to guarantee the consistency of the shareddata variables. If a shared variable is read withoutdata variables. If a shared variable is read withoutacquire memory has no obligation to return the currentacquire memory has no obligation to return the currentvalue.value.


Protected VariablesProtected Variables

Acquire and release do not have to apply to all of the Acquire and release do not have to apply to all of the memory.memory.

Only specific shared variables may be guarded, in which Only specific shared variables may be guarded, in which case these variables are kept consistent and called case these variables are kept consistent and called protected variables.protected variables.

On acquire, the memory makes sure that all the local On acquire, the memory makes sure that all the local copies of protected variables are made consistent and copies of protected variables are made consistent and changes are propagated to other machines on release. changes are propagated to other machines on release.


P1: Acq(L) W(x)1 W(x)2 Rel(L)

P2: Acq(L) R(x)2 Rel(L)

P3: R(x)1

Fig: Valid event sequence for release consistency.


Rules for release consistencyRules for release consistency

Before an ordinary access to a shared variable is Before an ordinary access to a shared variable is performed, all previous acquires done by the process performed, all previous acquires done by the process must have completed successfully.must have completed successfully.

Before a release is allowed to be performed, all previous Before a release is allowed to be performed, all previous reads and writes done by the process must have reads and writes done by the process must have completed.completed.

The acquire and release accesses must be processor The acquire and release accesses must be processor consistent (sequential consistency is not required).consistent (sequential consistency is not required).


Implementation of Release ConsistencyImplementation of Release Consistency

Two types of implementation:Two types of implementation: Eager release consistency:Eager release consistency: Broadcast of modified data to all other processors is Broadcast of modified data to all other processors is

done at the time of release. done at the time of release.

Lazy release consistency:Lazy release consistency: A process gets the most recent values of the variables A process gets the most recent values of the variables

when it tries to acquire them.when it tries to acquire them.


Our ImplementationOur Implementation

Eager release consistencyEager release consistency

All the operations are done locally by the process and All the operations are done locally by the process and then sent to the DSM, which then broadcasts the then sent to the DSM, which then broadcasts the updated values to all the other processes.updated values to all the other processes.


Each process Pi maintains the following data structures:Cache array cache[1…..n]] // cache memoryArray valid[1…..n] // whether the value in the cache is valid or not (0/1)Array locked[1…..n] // whether the variable is locked or not (0/1)Array request[1…..m] // which variables it wants to lock

Distributed Shared Memory (DSM) maintains the following data structures:Memory array M[1…..n] // central memoryArray lock[1…..n] // to keep track of which variables are locked (0/1)Array whom[1…..n] // locked by which processorArray pending[1…..m] // processes who are yet to be repliedArray invalidate[1…..m] // values processes need to invalidate

Data StructuresData Structures


Operations at Processor PiOperations at Processor Pi

lock(list of variables):send(Pid, ACQUIRE, no_of_variables, request[1…..m]);receive(ACK and received_values[]); for i = 1 to m

locked[i] = 1;

read(i):if locked[i]

return cache[i];else if valid[i]

return cache[i];else

send(Pid, READ, i);receive(x);cache[i] = x;valid[i] = 1;


Operations at Processor PiOperations at Processor Pi write(i, x):

if locked[i] {cache[i] = x;valid[i] = 1;

} else {

send(Pid, WRITE, i, x);cache[i] = x;valid[i] = 1;

}

unlock(list of variables):send(Pid, RELEASE, locked[1…..m],

cache[1…..m]); receive[ACK]; for i = 1 to n

locked[i] = 0;


Operations at DSMOperations at DSM

receive() {switch(message) {

case READ: send(M[i]);break;

case WRITE:M[i] = x;break;


case ACQUIRE:/* for all the variable indices in request[1…..m], check in lock[] if they are free */for i = 0 to no_of_variables {

if (lock[request[i]] = = 0) {lock[request[i]] = 1;whom[request[i]] = Pid;requested_variable_values[i] = M[request[i]];continue;

}else {

for i = 0 to no_of_variables {lock[request[i]] = 0; whom[request[i]] = 0;/* add request[i] to pending[] */pending[Pid, i] = request[i];

}break;

}send(requested_variable_values[]);

}break;


case RELEASE:/* has received arrays locked[] and cache[] */

for i = 0 to no_of_variables {M[locked[i]] = cache[i];invalidate[i] = locked[i];

}broadcast(invalidate[]);receive(ACK);for i = 0 to no_of_variables {

lock[locked[i]] = 0;whom[locked[i]] = 0;

}send(Pid, ACK);check(pending[]);check() {

for i = 0 to n {/* if all pending[i] = = 1, send(ACK, Pid) */

}}break;


P1 DSM P2

(ACQUIRE, request[])

Enter CS

Write (a) Read (b) Write (c) Write (b)

(RELEASE, locked[], cache[]

RELEASE_ACK

Leave CS

BROADCAST

(ACK, values[])

Code for P1: Lock (a, b ,c);

Write (a);

Read (b);

Write (c);

Write (c);

Unlock (a, b, c);

Sample Execution

Exit CS

ACK


Performance IssuesPerformance Issues

Knowing the Execution HistoryKnowing the Execution History Broadcast overhead can be reducedBroadcast overhead can be reduced

No potential deadlocksNo potential deadlocks Operations inside the critical section are atomicOperations inside the critical section are atomic


PRAM ConsistencyPRAM Consistency

The total ordering of requests leads to The total ordering of requests leads to inefficiency due to more data movement inefficiency due to more data movement and synchronization requirements than and synchronization requirements than what a program may really call for.what a program may really call for.

A more relaxed version than Sequential A more relaxed version than Sequential

consistency is PRAM.consistency is PRAM.


PRAM(contd)PRAM(contd)

PRAM stands forPRAM stands for Pipelined RAM, thus, Pipelined RAM, thus, pipelined random accesspipelined random access

“ “ Writes done by a single process are Writes done by a single process are received by all the processes in the order received by all the processes in the order in which they were issued but writes from in which they were issued but writes from different processes may be seen in a different processes may be seen in a different order by different processes.” different order by different processes.”


ExampleExample

P1: W(x)1P1: W(x)1

P2P2 R(x)1 W(x)2R(x)1 W(x)2

P3:P3: R(x)1 R(x)2 R(x)1 R(x)2

P4:P4: R(x)2 R(x)1 R(x)2 R(x)1

Fig: Valid sequence of events for the PRAM Fig: Valid sequence of events for the PRAM consistency.consistency.


Weak RestrictionsWeak Restrictions

Only write operations performed by a single Only write operations performed by a single process are required to be viewed by other process are required to be viewed by other processes in the order that they were performed. processes in the order that they were performed.

In other terms, all writes generated by different In other terms, all writes generated by different processes are concurrent.processes are concurrent.

Only the write order from same process needs to Only the write order from same process needs to be consistent, thus the name be consistent, thus the name pipelinedpipelined. .

This is a weaker model than the causal model. This is a weaker model than the causal model.


Cache Cache Cache Cache

MiddleWare (Java Groups)

Central Memory

System ArchitectureSystem Architecture

DSM System


ImplementationImplementation

The operations by the processes are carried as The operations by the processes are carried as shown below:shown below:

Write(x) : Write(x) : Update the local cache value.Update the local cache value. Send the updated value to all the processes.Send the updated value to all the processes.

Read(x) :Read(x) : If present in the cache, read it from cache. If present in the cache, read it from cache. else goto main memory for the variable.else goto main memory for the variable.


continued…continued…

Whenever a write is carried, the value is Whenever a write is carried, the value is pushed to all the processes, thus writes pushed to all the processes, thus writes done by a process are always seen in the done by a process are always seen in the order in which they are written in the order in which they are written in the program as each is broadcasted after its program as each is broadcasted after its occurrence occurrence


Data StructuresData Structures

Central Memory (CM):Central Memory (CM):- An array CM[] of shared variables var1..var2.- An array CM[] of shared variables var1..var2.- We can do read operations and write operations on - We can do read operations and write operations on

this array.this array.- Array implemented using a Vector- Array implemented using a Vector

Local Cache : Local Cache : - An array C[] of type int of size equal to that of Central - An array C[] of type int of size equal to that of Central memory’s. memory’s.- A boolean one-dimensional array V[ ] for validity of the i- A boolean one-dimensional array V[ ] for validity of the ithth variable. variable.- We can do read operations and write operations on cache.- We can do read operations and write operations on cache.- Arrays implemented using a Vector- Arrays implemented using a Vector


Pseudo CodePseudo Code

At ProcessAt Processnn::

Read ( iRead ( inn)) - If (valid(i- If (valid(inn))))

fetch the element ifetch the element in n from the cache vector Vc from the cache vector Vc elseelse - send read(i- send read(inn,n) to CM,n) to CM - receive value(i- receive value(inn,n) from CM,n) from CM - update element i- update element in n in cache in cache - set valid(i- set valid(inn) = true) = true - return value(i- return value(inn););


Continued…Continued…

write( iwrite( inn, val, valnn))

- - write value valwrite value valnn into element i into element inn of cache vector of cache vector

- send write- send write( i( inn, val, valnn)) to CM to CM

Receive Receive ( i( inn, val, valnn))

- - write value valwrite value valnn into element i into element inn of cache vector of cache vector


At Central memoryAt Central memory Write (index iWrite (index inn, value v, value vnn))

- write value v- write value vnn into element i into element inn of vector. of vector.

- send i- send inn, v, vn n to all the n processes.to all the n processes.

Read Read (process(processnn, index i, index in n ))

- fetch the element i- fetch the element in n from the vector. from the vector.

- send value(i- send value(inn) to the process) to the processnn. .


IssuesIssues

Easy to implementEasy to implement- No guarantee about the order in which different - No guarantee about the order in which different processes see writes. processes see writes.- Except, that writes issued by a particular - Except, that writes issued by a particular

process process must arrive in pipeline must arrive in pipeline

Processor does not have to stall waiting for each one to Processor does not have to stall waiting for each one to complete before starting the next one.complete before starting the next one.


Final SystemFinal System

We are using Java Groups as MiddlewareWe are using Java Groups as Middleware

We have only a single group containing all the processes We have only a single group containing all the processes and the central DSM.and the central DSM.

We are using the Reliable, FIFO JChannel for the We are using the Reliable, FIFO JChannel for the communication between the processes and the DSM.communication between the processes and the DSM.

We have only two types of communications unicast and We have only two types of communications unicast and broadcast which are efficiently provided by Jchannel.broadcast which are efficiently provided by Jchannel.


DSM Initialization:DSM Initialization:

DSM will be given an argument saying which DSM will be given an argument saying which consistency level it should provide for the processes.consistency level it should provide for the processes.

Process Initialization:Process Initialization:

When a process starts execution, it:When a process starts execution, it:- sends a message to DSM inquiring about the - sends a message to DSM inquiring about the consistency level provided by the DSM. consistency level provided by the DSM.- waits for the response- waits for the response- Initializes the variables related to the - Initializes the variables related to the

consistency consistency level so as to use the corresponding level so as to use the corresponding library for library for communicating with the DSM. communicating with the DSM.


In order to connect to the system each process In order to connect to the system each process should know:should know: Group Address/Group NameGroup Address/Group Name Central DSM AddressCentral DSM Address

ScalableScalable

Easy to connect, with just one round of messagesEasy to connect, with just one round of messages

Less load on the network.Less load on the network.


Performance EvaluationPerformance Evaluation

Planning to test the performance of each Planning to test the performance of each consistency level with large number of consistency level with large number of processes accessing the shared memoryprocesses accessing the shared memory

Calculating the write cycle time and read cycle Calculating the write cycle time and read cycle time for each consistency level at the application time for each consistency level at the application levellevel

Comparing our implementation of each Comparing our implementation of each consistency level with the above criteria consistency level with the above criteria


ReferencesReferences

Brown, G. Asynchronous multicaches. Brown, G. Asynchronous multicaches. Distributed Computing,Distributed Computing, 4:31-36, 1990.4:31-36, 1990.

Mizuno, M., Raynal, M., and Zhou J.Z. Sequential consistency Mizuno, M., Raynal, M., and Zhou J.Z. Sequential consistency in distributed systems.in distributed systems.

A Sequentially Consistent Distributed Shared Memory, J. A Sequentially Consistent Distributed Shared Memory, J. Zhou, M. Mizuno, and G. Singh.Zhou, M. Mizuno, and G. Singh.

Distributed Operating Systems, Andrew S. Tanenbaum.Distributed Operating Systems, Andrew S. Tanenbaum. www.javagroups.comwww.javagroups.com www.cis.ksu.edu/~singhwww.cis.ksu.edu/~singh

http://www.javagroups.com/


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Distributed Shared Memory CIS825 Project Presentation