DLC 2 mark 28.12.2010

7/18/2019 DLC 2 mark 28.12.2010

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EE2255 DIGITAL LOGIC CIRCUITS 3 1 0 4

AIM

To introduce the fundamentals of Digital Circuits, combinational and sequential circuit.

OBJECTIVES

i. To study various number systems and to simplify the mathematical

expressions

using Boolean functions – simple problems.

ii. To study implementation of combinational circuits

iii. To study the design of various synchronous and asynchronous circuits.

iv. To expose the students to various memory devices.

v. To introduce digital simulation techniques for development of application

oriented logic circuit.

1. BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9

Boolean algebra: De!organ"s theorem, s#itching functions and simplification using

$maps % &uine !cClus'ey method, Design of adder, subtractor, comparators, code

converters, encoders, decoders, multiplexers and demultiplexers.

2. SYNCHRONOUS SEQUENTIAL CIRCUITS 9

(lip flops )*, D, +$ and T. nalysis of synchronous sequential circuits- design of

synchronous sequential circuits – Counters, state diagram- state reduction- state

assignment.

3. ASYNCHRONOUS SEQUENCTIAL CIRCUIT 9

nalysis of asynchronous sequential machines, state assignment, asynchronous

design problem.4. PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC AMILIES 9

!emories: *!, /*!, 0/*!, /1, /1D, (/2, digital logic families: TT1,0C1, C!).

5. VHDL 9

*T1 Design – combinational logic – Types – perators – /ac'ages – )equential

circuit – )ub programs – Test benches. 30xamples: adders, counters, flipflops, ()!,

!ultiplexers 4 Demltiplexers5.

L ! 45 T ! 15 T"#$% ! &0

TE'T BOO(S

6. *a7 $amal, 8 Digital systems/rinciples and Design", /earson education 9

nd

edition, 9;

9. !. !orris !ano, 8Digital Design", /earson 0ducation, 9<.

=. +ohn !.>arbrough, 8Digital 1ogic, pplication % Design", Thomson, 99.

REERENCES

6. Charles ?.*oth, 8(undamentals 1ogic Design", +aico /ublishing, @A edition, 99.

9. (loyd and +ain, 8Digital (undamentals", th edition, /earson 0ducation, 9=.

=.+ohn (.a'erly, 8Digital Design /rinciples and /ractice", =rd edition, /earson

0ducation, 99.

. Tocci, EDigital )ystems : /rinciples and aopplications,

th

0ditionF /earson 0ducation.UNIT ) I

7/18/2019 DLC 2 mark 28.12.2010


BOOLEAN ALGEBRA * COMBINATIONAL CIRCUITS

1. C"+-# #/- /-$-$% +6- &7BE #" 6+$8 $+ "#$% NOV 200:;

&7BE;H ! ;2 ! ;7

< B 0

↓ ↓ ↓ ↓

66 6 666 666 G 366666666659

66 6 6 666 66

↓ ↓ ↓ ↓ ↓

< 9 ; < G 3<9;<5

2. + #/- 1<= $+ 2<= ">%--+# "? 00000000 NOV 200:;

6"s complement of G66666666

9"s complement G6"sH6G66666666H6G6

3. E>-== #/- ?"%%"@+ =@#/+ # + 6+$8 %" +"#$#"+.NOV 200:;

4. S>%?8 ' 'Y. NOV 200:;

INPUT OUTPUT

A B C Y!AB;.C

6 6

6

6 6 6

6

6 6 6

6 6

6 6 6 6

' Y ' 'Y ''Y

6

6 6 6 6

6 6

6 6 6

I H I> G IH>

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5. /$# = #/- ??--+- 6-#@--+ /$%? $- $+ ?%% $- N" ) 200:;

H$%? A- %% A-

The logic circuit #hich performs

the arithmetic sum of t#o bits is

called a half adder.

The logic circuit #hich performs

the arithmetic sum of three bits is

called a full adder.

&. I>%--+# /$%? $- =+ $#-= N" 200:;

:. /$# = $ >- I>%$+# N" 2007;.fter grouping the cells, the sum terms #hich appear in the $map are called

/rime @mplicant.

7. G-+ #/$# 1&10 ! 1006 ?+ #/- $%- "? 6. NOV 2007;

6<

6

The value of b G .

9. I>%--+# #/- ?"%%"@+ =+ NAND $#-= "+%8. N" 2007;B H BG>

INPUT OUTPUT

A B S C$8

6 6

6 6

6 6 6

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10. G- $+ $>>%$#"+ -$/ ?" $ %#>%-- $+ $ D- %#>%--. NOV 2007;

!ultiplexer circuit are used for data selection and data routing.

De multiplexers are used in Binary to Decimal decoder and it is used in

DT transmission system #ith error detection.

11. S#$#- D-"$+<= #/-"-. J+- 2009;

6. B G H B. The complement of a product is equal to the sum of the

complement.

9. H B G . B. The complement of a sum is equal to the product of the

complement.

1. P""? AB ! A B

A B A . B A B A B

6 6 6 6

6 6 6 6

6 6 6 6

6 6

2. P""? AB ! A . B

A B AB A B A . B

6 6 6 6

6 6

6 6

6 6

12. B-?%8 ->%$+ #/- =#-$%+- -#/" "? "+-#+ 6+$8 #" -$% +6-

@#/ $+ -$>%-. J+- 2009;

0xample : 3666659 G 3 56

6 I 9 H 6 I 9= H I 99 H 6 I 96 H 6 I 9

6< H H H 9 H 6 G 39;56

13. G- #/- G$8 "- ?" #/- 6+$8 +6- 1111;2 J+- 2009;

3666659 G 36652ray

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14. S6#$# 01011011 F 00000101 J+- 2009;

66666

66

6666

15. /$# = >"#8 -+"-. J+- 2009;.

priority encoder is an encoder circuit that includes the priority function. @n

priority encoder, if 9 or more inputs are equal to 6 at the same time, the input having the

highest priority #ill ta'e precedence.

1&. S/"@ #/- ""+ $#/"- #8>- =--+ =--+# +$#" =>%$8;. N" 2009;.

D# A B C D $ 6 - ?

6 6 6 6 6 6

6 6 6 6

9 6 6 6 6 6 6

= 6 6 6 6 6 6 6

6 6 6 6 6

J 6 6 6 6 6 6 6 6

< 6 6 6 6 6 6 6 6

; 6 6 6 6 6 6

6 6 6 6 6 6 6 6

K 6 6 6 6 6 6 6 6

1:. C"+-# 1110011 +#" /-$-$%. J+- 2010;

666 66

↓ ↓

; = ns. G 3;=5?

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17. A 1A7;1& $+ &:B;1&. J+- 2010.

6

< ; B

9 =

ns. : 39=5?

19. E>-== #/- B""%-$+ ?+#"+ ! 'Y 'Y $= $ >"# "? $ #-. J+-

2010;

'.Y ' 'Y 'Y 'Y'Y

6 → !ax term

6 6 6 6

6 → !ax term

6

6

6 6

( G L!3,95

20. D??--+#$#- "6+$#"+$% $+ =--+#$% #= J+- 2010;

C"6+$#"+$% # S--+#$% C#

!emory unit is not required !emory unit is required

/arallel adder is a combinationalcircuit

)erial adder is a sequentialcircuit.

21. A A3;1& #" :C;H.

=

; C

66 (

ns.: 366(5?

22. /$# " 8" -$+ 68 %#-$%

D-$% H-$

6< 6

6; 666 69

6K 6=

9 6

D-$% H-$

6J (

6< 6

6; 66

6 69

6K 6=

9 6

96 6J

99 6<

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@n Boolean function, the total number of variables in complemented or

uncomplemented form are called literals.

0xample: ( 3,B,C,D5 G H BC H CD contains < literals.

23. N$- #@" 6$= ?"= "; #8>-= "? B""%-$+ ->-=="+.

1. )um of product (orm 3)/5 or !in term.

2. /roduct of sum form 3/)5 or !ax term.

24. // $#-= $- $%%- $= +-=$% $#-= $+ @/8 #/-8 $- =" $%%-

MMD and M* gates are called as universal gates. )ince MMD and M*

gates can be used alone to generate remaining gates such as MT, MD and *. ?ence

they are called as universal gates.

25. R->-=-+# 6+$8 +6- 1101.101 + >"@- "? 2 $+ ?+ #= -$%

-$%-+#.

M G 6 x 9= H 6 x 99 H x 96 H 6 x 9 H 6 x 96 H x 99 H 6 x 9=

G 36=.<9J56

2&. C"+-# &34;7 #" 6+$8.

< =

66 66 6

ns G 366 66 659

2:. C"+-# 9 B 2.1A;H #" #= -$% -$%-+#.

M G K x 6<9 H B3665 x 6<6 H 9 x 6< H 6 x 6<6 H 365 x 6<9

G 9= H 6;< H 9 H .<9J H .=K

G 399.66J56

27. /$# $- #/- ??--+# %$==?$#"+= "? 6+$8 "-=

• eighted codes

• Mon #eighted codes

•*eflective codes

• )equential codes

• lphanumeric codes

• 0rror Detecting and correcting codes.

29. C"+-# $8 "- 101011 +#" #= 6+$8 -$%-+#.

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30. A 1 0 1 0;2 $+ 0 0 1 1;2

31. + 2= ">%--+# "? 1 0 1 0 0 0 1 1; 2

32. /$# $- #/- $$+#$-= "? 1<= ">%--+# =6#$#"+

• The 6"s complement subtraction can be accomplished #ith an binary adder.

Therefore, this method is useful in arithmetic logic circuits.

• The 6"s complement of a number is easily obtained by inverting each bit in the

number.

33. /$# = -$+# 68 >$#8 6#

/arity bit is an extra bit included #ith a binary message to ma'e the number of 6"s either odd or even. The message, including the parity bit is transmitted and then

chec'ed at the receiving and for errors.

34. D-?+- D-"-.

decoder is a multiple input multiple output logic circuit #hich converts coded

inputs into coded outputs #here the input and output codes are different.

@n a binary decoder n input produces 9n outputs.

35. D-?+- E+"-.n encoder has 9n input lines and n output lines. @n encoder the output lines

generate the binary code corresponding to the input value.

3&. D-?+- %#>%-- * D-%#>%--.

!ultiplexer is a digital s#itch. @f allo#s digital information from several sourcesto be routed onto a single output line.

Demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 9n possible output lines.

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3:. D-=+ 17 -%#>%-- =+ #" 14 DEMU'.

37. /$# = $ %" $#-

The logic gate is an electronic circuit that has one or more input binary variables

but only one output. @t is called logic gate because of its ability to operate on a number

of binary inputs to perform a logical function, i.e. its output is a logical function of

inputs

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UNITF II

SYNCHRONOUS SEQUENTIAL CIRCUITS

1. /$# = -$+# 68 #-+ $+ @/$# = -- #-+ N" 200:;

Triggering of a flip flop means changing the state of the output of flip flop

3from to 6 for Hve logic and from 6 to for –ve logic 5 by giving a cloc' pulse and an

input.

nother type of flip flop that synchroniNes the state changes during a cloc' pulse

transition is edge triggered flip flop. @n this type of flip flop output transitioMoccur at a

specific level of the cloc' pulse.

2. /$# = $- "+#"+ N" 2007;

@n the +$ latch, the output is feedbac' to the input, and therefore change in the

output results change in the input. Due to this in the positive half of the cloc' pulse if +

and $ are both high then output toggles continuously. This condition is 'no#n as race

around condition.

3. D$@ #/- ##/ #$6%- ?" $ NOR $#- RS %> ?%">. J+- 200:;

S R Q+ Q+1 S#$#-

6

6 Mo change 3MC5

6

6

6

*eset

6

6

6

6

6)et

6

6

6

6

6

I

I@ntermediate

4. O6#$+ D %> %"> ?" J( %> %">. J+- 2009;

"

5. C"+-# J( %> ?%"> #" D %> ?%">. J+- 2010;

I+># P-=-+# =#$#- N-# =#$#- %>F?%"> +>#=

D Q+ Q + 1 J (

I

6 I 6

6 6 6 I

6 6 6 I

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&. D??--+#$#- S8+/"+"= C"+#- $+ A=8+/"+"= C"+#- J+- 2009;

:. D$@ $ "%" & "+#- J+- 2009;

9n OG<

MG<

nG=

therefore three flip flops are required to dra# the modulo < counter

7. A "+#- /$= 14 =#$6%- =#$#-= 0000 #/"/ 1101. I? #/- +># ?--+8 = 50

H. /$# @%% 6- #/- "#># ?--+8 J+- 2010;

J $?N G =.J; $?N

6

9. D-?+- =--+#$% # $+ @/$# $- #/- #8>-= "? =--+#$% #=

@n sequential circuits the output variables dependent not only on the present input

variables but they also depend up on the past history of these input variables.

• )ynchronous sequential circuits

•synchronous sequential circuits

10. D-?+- ?%>F?%">

(lip flop is a sequential device that normally samples its inputs and changes its

outputs only at times determined by cloc'ing signal.

11. L=# $"= #8>-= "? ?%>F?%">

• ).*. latch

• D latch

• Cloc'ed +.$. flipflop

• T flipflop

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12. D$@ #/- %" $$ ?" SR %$#/ =+ #@" NOR $#-=.

13. T/- ?"%%"@+ @$- ?"= $- $>>%- #" #/- +>#= "? SR %$#/.

D-#-+- #/- Q @$-?" A==- +#$%%8 Q ! 1

14. /$# = -$+# 68 $ %"- %> ?%">

(( #hose state changes 3according to the data i4p s 5 only #hen a cloc' pulse is

present.

15. E>%$+ #/- ?+#"+= "? K>-=-#< $+ K%-$< > = + ?%> ?%">=.

/reset input is used to set 3ma'e & G 6 5 the ((,#hereas the clear i4p is

used to clear or reset 3ma'e & G 5 the ((.

1&.E>%$+ #/- ">-$#"+ "? $ J( ?%> ?%">.

i5 hen + G $ G , the outputs are not affected by the cloc' pulse.

ii5 hen + G $ G 6,the outputs get complemented #hen a cloc' is

applied.

i5 + G 6, $ G sets the (( #hen the cloc' is applied.

ii5 + G , $G 6 clears the (( #hen the cloc' is applied.

1:. /$# = M$=#- S%$- ?%> ?%">

@t is a cascade of t#o flip flops in #hich the first one responds to the data inputs #hen

the cloc' is high, #hereas the second one responds to the outputs of the first one #hen

the cloc' is lo#. Thus the final o4p change only #hen the cloc' is lo# #hen the data

inputs are not effective. Thus the race around condition gets eliminated in this. The first

(( is 'no#n as the !)T0* and the second as the )1A0.

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17. /$# = $ L$#/ $+ @/$# = -$+# 68 $ T$+=>$-+# L$#/

1atch stores one bit of data. @t is a D type of flip flop.

@t is the output of the latch follo#s the input as long as the cloc' is present and

#hatever is the o4p at the falling edge of the cloc' gets latched, it is 'no#n as the

transparent latch. The #ord transparent signifies that the output is same as the i4p as long

as the cloc' is present.

19. /$# $- #/- $"= -#/"= =- ?" #-+ ?%> ?%">

i5 1evel Triggering.

ii5 !aster)lave or /ulse triggering.

iii5 /ositiveedge triggering.

iv5 Megativeedge triggering.

20. D??--+#$#- 6-#@--+ N-$#-F-- #-- $+ M$=#- =%$- ?%> ?%">.

@n Megativeedge triggered ((, only a negative 3 or falling 5 edge is required for

triggering #hereas in the case of master slave ((, both a positive and a negative edge are

required for triggering.

21. D??--+#$#- 6-#@--+ SFR $+ JF( ?%> ?%">.

hen both the i4ps are at logic 6,the o4p of a +$ (( gets complemented, #hereas

this i4p condition is prohibited in )* ((. (or all other i4p conditions the behavior of both is same.

22. /8 M$=#- ) S%$- "+?$#"+ = =- + $ J( ?%> ?%">

!aster – )lave configuration is used in a +$ (( to eliminate *ace – around

condition.

23. D-?+- =/?# R-=#-=

The binary information in a register can be moved from stage to stage #ithin the

register or into or out of the register upon application of cloc' pulses. This type of bit

movement or shifting is essential for certain arithmetic and logic operations used inmicroprocessors. This gives rise to a group of registers called shift registers.

24. /$# $- #/- #8>-= "? =/?# -=#-

• )erial in serial out shift register

• )erial in parallel out shift register

• /arallel in serial out shift register

• /arallel in parallel out shift register

• Bidirectional shift register

25. /$# $- #/- #8>-= "? "+#-

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• )ynchronous counter

• synchronous Counter

2&. D-?+- >">$$#"+ D-%$8

propagation delay is the time required to change the output after application of the input.

2:. /$# = -$+# 68 =-$% $#$

@n the serial form the data is arranged bit by bit. nly one #ire is required for serial

data.

27. /$# = -$+# 68 >$$%%-% $#$

@n the parallel form each data bit requires a separate #ire. (or example, #ires arerequired for processing or transmitting an bit data.

29. C">$- =-$% $#$ $+ >$$%%-% $#$ #$+==="+.

6. )erial data requires only one connecting #ire bet#een the source device and the

destination device, #hereas the parallel data requires a number of lines equal to the

number of bits in the data. Therefore, parallel transmission is expensive.

9. )erial data transmission requires more time than the parallel data transmission.

30. /$# = -$+# 68 "%= "? $ "+#-

@t represents the number of possible states of the counter.

31. H"@ @%% 8" =- $ =/?# -=#- #" %#>%8 " - $ 6+$8 +6- 68 2

The binary number is to be stored in the shift register and then shifted to#ards

right or left respectively by one bit position for multiplication or division by 9.

32. A- #/- + $+ #@=#- + "+#-= =8+/"+"= " $=8+/"+"= "+#-=

J=#?8

The ring and t#isted ring counters are synchronous because all the (1@/(lops

are cloc'ed simultaneously in three counters.

33. /$# = -$+# 68 #/- ?"%%"@+ #-=

3a5 )ynchronous preset 3b5 synchronous preset

3c5 )ynchronous clear 3d5 synchronous clear

3a5 /reset operation is performed in synchronism #ith the cloc'

3b5 /reset operation is independent of the cloc'

3c5 Clear operation is performed in synchronism #ith the cloc'.

3d5 Clear operation is independent of the cloc'

34. C$+ 8" =- $ :492 "+#- IC $= $ +$#$% 6+$8 "F12 "+#- J=#?8

8" $+=@-.

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@t is not possible. The divide by < circuit of this counter does not follo# natural

binary sequence.

35. H"@ @%% 8" =- #/- :490 IC #" -=+ $ =8-#$% - 68 10 ?--+8

-

The divide by J circuit follo#ed by divide by 9 circuit #ill give symmetrical

output.

3&. /$# = #/- $@6$ "? SR %> ?%"> $+ /"@ # = +- Dra#bac's

of )* (lip flop is that it has intermediate state #hen )* G 66 and problem can be

minimiNed by providing complemented input"s for ) % *.

3:. H"@ "-= $ J( %> ?%"> ??- ?" #/- SR %> %"> + #= 6$= ">-$#"+

@n +$ (lip flop #hen both the inputs are logic 6 the output is complement of

previous output. ?o#ever, in case of )* flip flop #hen both the input"s are 6, the output

is intermediate.

37. M-+#"+ #/- $>>%$#"+ "? "+#-.

Digital counter is useful and versatile device and it is found in many applications

such as digital cloc' and frequency counter.

39. H"@ $+8 %> ?%">= $- -- #" 6% $ 6+$8 "+#- #/$# "+#= ?" 0

#" 1023

Mumber of flip flops required:

9

n

O 69= H 69n O 69

M G 6

Therefore 6 flip flops are required to build a binary counter that counts from to

69=.

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UNITF III

ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. /$# = #/- ??--+- 6-#@--+ =-$% $+ >$$%%-% #$+=?- /$# #8>- "?

-=#- = =- + -$/ $=- N" 200:;

)hift register are used for storage and transfer of data in a digital system.

S-$% #$+=?- P$$%%-% T$+=?-

)erial shift right then out

)erial shift left then out

/arallel shift in

/arallel shift out

The register used for serial transfer is serial in serial out shift register.

The register used for parallel transfer is parallel in parallel out shift register.

2. D-?+- H$$. N" 2007;

The un#anted s#itching transients that appear at the output of a circuit are called

?aNards. The haNard cause the circuit to malfunction. The main cause of haNards is

the different propagation delays at different paths.

3. /$# = $ M-$%-8 $/+- G- $+ -$>%-. N" 2007;

hen the output of the sequential net#or' depends on both the present state of flipflop and on the inputs the sequential circuit is called as !ealey machine. @ts input

changes may affect the output of the circuit.

4. /$# = S$#$#"+ -%$8 #- E>%$+. J+- 2009;

TT1 logic family are based on the saturation mode. @n the saturation mode, the

transistor ta'es some time to come out of the saturation to s#itch to the cut off

mode. )ince the transistors do not go into saturation, these families do not have

saturation delay time for s#itching operation.

5. /$# = $ $- "+#"+ H"@ # $+ 6- -%+$#- J+- 2009;

@n a +$ latch #hen +% $ are both high, then the output toggles continuously and

this condition is called race condition.

This can be eliminated #hen an edge triggered or pulse triggered +$ flip flop is

used. @n this flip flop the output changes only at the positive edge or a negative

edge of the cloc'.

&. /$# = -==-+#$% /$$ G- $+ -$>%-. J+- 2009;

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0ssential haNards occurs in asynchronous sequential circuits. @t is caused by

unequal delays along t#o or more paths that originate from the same input. These

haNards can be eliminated by ad7usting the amount of delays in the affected path.

:. /$# = #/- ??--+- 6-#@--+ /$$ $+ $- J+- 2010;

The un#anted s#itching transients that appear at the output of a circuit are called

?aNards. The haNard cause the circuit to malfunction. The main cause of haNards is

the different propagation delays at different paths.

@n a +$ latch #hen +% $ are both high, then the output toggles continuously and

this condition is called race condition.

7. T/- +># ?--+8 "? $ 4 6# >>%- "+#- = 25& H. /$# = #/- "#>#

?--+8 J+- 2010;

– 6J that is 6< stable states are there for a bit ripple counter. 2iven input

frequency G 9J< ?N.

9J< ?N

G 6< ?N

6<

utput frequency G 6< ?N

9. D-?+- ">$#6%#8.

)tates )i and )7 said to be compatible states, if and only if for every inputsequence that affects the t#o states, the same output sequence, occurs #henever both

outputs are specified and regardless of #hether )i on )7 is the initial state.

10. D-?+- -- $>/.

The merger graph is defined as follo#s. @t contains the same number of vertices

as the state table contains states. 0ach compatible state pair is indicated by a line dra#n

bet#een the t#o state vertices. @f t#o states are incompatible no connecting line is

dra#n.

11. D-?+- +">$#6%#8.

The states are said to be incompatible if no line is dra#n in bet#een them. @f

implied states are incompatible, they are crossed % the corresponding line is ignored.

12. E>%$+ #/- >"-- ?" =#$#- +$#"+.

• /artition the states into subsets such that all states in the same subsets are 6

equivalent.

• /artition the states into subsets such that all states in the same subsets are 9 equivalent.

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• /artition the states into subsets such that all states in the same subsets are =

equivalent.

13. D-?+- =#$#- #$6%- $+ #"#$% =#$#-.

(or the design of sequential counters #e have to relate present states and nextstates. The table #hich represents the relationship bet#een present states and next states

is called state table.

The combination of level signals that appear at the inputs and the outputs of the

delays is called the total state of the circuit.

14. /$# $- #/- =#->= ?" #/- -=+ "? $=8+/"+"= =--+#$% #

• Construction of a primitive flo# table from the problem statement.

• /rimitive flo# table is reduced by eliminating redundant states by using

state reduction.• )tate assignment is made

• The primitive flo# table is realiNed using appropriate logic elements.

15. D-?+- >#- ?%"@ #$6%-.

@t is defined as a flo# table #hich has exactly one stable state for each ro# in the

table. The design process begins #ith the construction of primitive flo# table.

1&. G- #/- ">$="+ 6-#@--+ =#$#- A==+-+# S8+/"+"= #= $+ =#$#-

$==+-+# $=8+/"+"= #.

@n synchronous circuit, the state assignments are made #ith the ob7ective of circuit reduction. @n asynchronous circuits, the ob7ective of state assignment is to avoid

critical races.

1:. D-?+- #$% $- $+ +"+ #$% $-

@f the final stable state depends on the order in #hich the state variable changes,

the race condition is harmful and it is called a critical race.

@f the final stable state that the circuit reaches does not depend on the order in

#hich the state variable changes, the race condition is not harmful and it is called a non

critical race.

17. /$# = $ 8%-

cycle occurs #hen an asynchronous circuit ma'es a transition through a series

of unstable states. @f a cycle does not contain a stable state, the circuit #ill go from one

unstable to stable to another, until the inputs are changed.

19. L=# #/- ??--+# #-/+-= =- ?" =#$#- $==+-+#

• )hared ro# state assignment

• ne hot state assignment.

7/18/2019 DLC 2 mark 28.12.2010


20. #- $ =/"# +"#- "+ ?+$-+#$% "- $=8+/"+"= #.

(undamental mode circuit assumes that. The input variables change only #hen

the circuit is stable. nly one input variable can change at a given time and inputs are

levels and not pulses.

21. #- $ =/"# +"#- "+ >%=- "- #.

/ulse mode circuit assumes that the input variables are pulses instead of level.

The #idth of the pulses is long enough for the circuit to respond to the input and the

pulse #idth must not be so long that it is still present after the ne# state is reached.

22. D-?+- =-"+$8 $$6%-=.

The delay elements provide a short term memory for the sequential circuit. The

present state and next state variables in asynchronous sequential circuits are called

secondary variables.

23. /$# = #/- >>"=- "? =8+#/-== + $=8+/"+"= =--+#$% #

The purpose of synthesis is to develop systematic techniques for the design of

fundamental mode asynchronous sequential circuits. The approach to be follo#ed is to

construct a flo# table #hich describes the circuit performance, to simplify the table,

#henever possible, and finally to realiNe it by electronic or electromechanical devices.

24. #- =/"# +"#- "+ =/$- "@ =#$#- $==+-+#.

*aces can be avoided by ma'ing a proper binary assignment to the state

variables. ?ere, the state variables are assigned #ith binary numbers in such a #ay that

only one state variable can change at any one state variable can change at any one time#hen a state transition occurs. To accomplish this, it is necessary that states bet#een

#hich transitions occur be given ad7acent assignments. T#o binary are said to bead7acent if they differ in only one variable.

25. #- =/"# +"#- "+ "+- /"# =#$#- $==+-+#.

The one hot state assignment is another method for finding a race free state

assignment. @n this method, only one variable is active or hot for each ro# in the original

flo# table, ie, it requires one state variable for each ro# of the flo# table. dditional

ro# are introduced to provide single variable changes bet#een internal state transitions.

7/18/2019 DLC 2 mark 28.12.2010


UNIT ) IV

PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC AMILIES

1. /$# = $ V"%$#%- -"8 G- -$>%-. N" 200:;

Aolatile memory losses the content #hen the computer or hard#are device losses

po#er.

0xample : )*! % D*!

2. // = ?$=#- TTL " ECL // --= "- >"@- #" ">-$#- N"

200:;

TT1 logic is faster than 0C1, since it uses multi emitter transistors and every

emitter is a diode this logic eliminates the use of diodes. 0C1 requires more po#er

to operate.

3. D-?+- ?$+ + * ?$+ "#. N" 2007;

$+F+

@t is said to be the number of inputs in a digital logic gate.0xample: 9 input M* had fanin of 9.

$+F"#

@t is said to be the number of inputs in a digital logic gate.

0xample: 9 input M* has (anin of 9.

4. D-?+- N"=- $+. N" 2007;

The voltage difference bet#een the lo#est possible ?@2? output, A? 3min5 and the

minimum input voltage, A@? 3min5 required for a ?@2? input is called highstate

noise margin.

The voltage bet#een the largest possible lo# output, A1 3max5 and the maximum,

A@1 3max5 required for a 1 input is called lo#state noise margin.

The noise margin allo#s the digital circuit to function properly if noise voltages are

#ithin the noise margin.

7/18/2019 DLC 2 mark 28.12.2010


5. /$# = =$#$#"+ -%$8 #- E>%$+ J+- 2009;

TT1 logic families are based on the saturation mode. @n the saturation mode, the

transistor ta'es some time to come out of the saturation to s#itch to the cut off

mode. )ince the transistors do not go into saturation, these families do not havesaturation delay time for s#itching operation.

&. C">$- B>"%$ T$+==#"= @#/ MOS T$+==#"= J+- 2009;

B>"%$ T$+==#"= MOS T$+==#"=

6. Bipolar can #or' at higher

frequencies.

6. @t #or' at lo# frequency.

9. @t has good input and output

impedance matching at high frequency.

9. @nput and output impedance

matching is not possible at high

frequency.=. ?igh po#er dissipation =. 1o# state po#er dissipation.

. ?igh cost . 1o# cost.

:. C">$- "%$#%- $#$ =#"$- @#/ +"+ "%$#%- $#$ =#"$-. J+- 2009;

V"%$#%- D$#$ S#"$- N"+F"%$#%- D$#$ S#"$-

6. Aolatile data storage losses the stored

information #hen the po#er is turned

off.

0x: )*! % D*!

Mon – volatile data storage retains the

stored information even #hen the

po#er is turned off.

0x: *!, /*!, 0/*!, 00/*!

7. H"@ = "6+$#"+$% %" -+-$#- + PGA J+- 2009;.

The (/2 has three types of configurable elements. They are @4 bloc's, C1B"s

and resources for interconnection.

configuration program stored in internal static memory cells determines the logic

functions and the interconnection.

9. D-?+- P">$$#"+ -%$8. J+- 2010;

@t is a time interval bet#een application of an input pulse and occurance of the

resulting pulse.

The propagation delay is determined using t#o basic time intervals:

6. t/?1 : Delay Time measured #hen output is changing from logic 6 to logic

state.

9. t/1? : Delay Time measured #hen output is changing from logic to logic 6state.

7/18/2019 DLC 2 mark 28.12.2010


=. hen t/?1 and t/1? are not equal, the larger value is considered as propagation

delay.

. The shorter the propagation delay, the higher the speed of the circuit and vice

versa.

10. /$# = ">-+ "%%-#" "#># TTL /-- = # =- J+- 2010;

hen the collector terminal of a transistor is 'ept open #ithout any pull up

transistor the arrangement is called open collector output.

The output is ta'en directly from the open collector terminal of a transistor at the

output.

But, a gate #ith open collector #ill not #or' properly until an external resistor is

connected.

11. E>%$+ PGA. G- $+ -$>%- "? =/ --. J+- 2010;.

(ield programmable 2ate rrays 3(/25 provide the next generation in

the programmable logic devices. The #ord field in the name refers to the ability

of the gate arrays to be programmed for a specific function by the user instead of

by the manufacturer of the device. The #ord array is used to indicate a series of

columns and ro#s of gates that can be programmed by the end user.

s compared to standard gate arrays, the field programmable gate arrays

are larger devices. The basic cell structure for (/2 is some #hat complicated

than the basic cell structure of standard gate array. The programmable logic

bloc's of (/2s are called configurable logic bloc's 3C1Bs5.

0xample: I@1@MPI = % I@1@MPI

12. L=# 6$= #8>-= "? >"$$6%- %" --=.

• *ead only memory

• /rogrammable logic rray

• /rogrammable rray 1ogic

13. /$# $- #/- #8>-= "? ROM

• !as'ed *!.

• /rogrammable *ead only !emory

• 0rasable /rogrammable *ead only memory.

• 0lectrically 0rasable /rogrammable *ead only !emory.

14. /$# = $= F >"$$6%-

ith a mas' programmable /1, the user must submit a /1 program table to

the manufacturer.

7/18/2019 DLC 2 mark 28.12.2010


15. G- #/- ">$="+ 6-#@--+ PROM $+ PLA.

1&. D-?+- S>-- P"@- P"# $+ @/$# = #/- "#/- +$- ?" =>-- P"@->"#

The )peed /o#er /roduct is defined as the product of /ropagation delay and

average po#er dissipation. @ts unit is +oules 4 )econds

The other name for speed po#er product is (igure of merit.

1:. " $ -#$+ IC ?$%8, >">$$#"+ -%$8 = 10+= @#/ $-$- >"@-

==>$#"+

"? & . /$# = #/- =>-- >"@- >"#

)olution:

)// G propagation delay x average po#er dissipation.

G 6 ns x < m

G < pico 7oules 3p+5

17. G- #/- ">$="+ 6-#@--+ T"#- >"%- $+ O>-+ "%%-#" O#>#

"+?$#"+.

T"#- P"%- O>-+ C"%%-#"6. utput stage consists of pull up

transistor, diode resistor and pull do#n

transistor.

utput stage consists of only pull do#n

transistor

9. 0xternal pull up resistor is not

required.

0xternal pull up resistor is required for

proper operation of gate.

=. utput of t#o gates can not be tied

together.

utput of t#o gates can be tied together

using #ired MD technique.

. perating speed is high. perating speed is lo#.

19. /$# $- #/- #/-- #8>-= "? "#># "+?$#"+ + TTL ?$%8

7/18/2019 DLC 2 mark 28.12.2010


• pen Collector configuration

• Totem pole output configuration

• Tristate logic

20. D-?+- I+#-?$+ $+ @/$# = #/- ?+#"+ "? I+#-?$+

@nterfacing means connecting the output of one circuit or system to the input of

another circuit or system that may have different electrical characteristics.

@ts function is to ta'e the driver output signal and condition it so that it is

compatible #ith requirements of the load.

21. /$# $- ---+# @/%- +#-?$+ #@" #= " =8=#-=.

• The driver output must satisfy the voltage and current requirements of the

load circuit.• The driver and load circuit may require different po#er supplies. @n such

cases the output of both circuits must s#ing bet#een its specified voltage

ranges.

22. /$# = #/- %#$#"+ "? TTL ?$%8

The TT1 family uses transistors operating in the saturation mode. s a result,

their s#itching speed is limited by the storage delay time associated #ith a transistor that

is driven into saturation.

23. G- $+8 2 >"+#= "? ECL /$$#-=#=.

• @t is the fastest of logic families. The popular 6$ and 6$ 0C1 families

offer propagation delay as short as 6 ns.

• Transistors are not allo#ed to go into complete saturation and thus

eliminating storage delays.

24. D-?+- H/ %--% +># "%#$- $+ L"@ %--% +># "%#$-.

A@? 3min5 –?igh level input voltage: @t is the minimum voltage level required for

a logical 6 at an input. ny voltage belo# this level #ill not be accepted as a ?@2? by

the logic circuit.

A@1 3max5 – 1o# level input voltage: @t is the maximum voltage level required for

a logic at an input. ny voltage above this level #ill not be accepted as a 1 by the

logic circuit.

25. D-?+- H/ %--% "#># "%#$- $+ L"@ %--% "#># "%#$-.

@t is the minimum voltage level at a logic circuit output in the logical 6 state under defined load conditions.

7/18/2019 DLC 2 mark 28.12.2010


@t is the maximum voltage level at a logic circuit output in the logical state

under defined load conditions.

2&. D-?+- H/ %--% +># -+# $+ L"@ %--% +># -+#.

@t is the current that flo#s into an input #hen a specified highlevel voltage is

applied to that input.

@t is the current that flo#s into an input #hen a specified lo#level voltage is

applied to that input.

2:. D-?+- H/ %--% "#># -+# $+ %"@ %--% "#># -+#.

@t is the current that flo#s from an output in the logical 6 state under specified

load conditions.

@t is the current that flo#s from an output in the logical state under specified

load conditions.

27. L=# #/- /$$#-=#= "? #$% I=

i5 propagation delay

ii5 po#er dissipation

iii5 (aniniv5 (anout

v5 Moise margin

29. D-?+- %$=/ -"8 $+ @/$# = #/- "#/- +$- ?" ?%$=/ -"8

(lash memory is a type of constantly po#ered nonvolatile memory that can be

erased and reprogrammed in units of memory called bloc's.

The other name is (lash *!. But (lash memory is not useful as random access

memory because *! needs to be addressable at the byte level.

30. C">$- 6-#@--+ PROM, PLA $+ PAL.

PROM PLA PAL

6. MD array is fixed

and * array is

programmable.

Both MD and *

arrays are

programmable.

* array is fixed and

MD array is

programmable.

9. Cheaper and simple to

use.

Costliest and complex

than /1 and /*!s.

Cheaper and )impler.

=. ll minterms are

decoded.

MD array can be

programmed to getdesired minterms.

MD array can be

programmed to getdesired minterms.

7/18/2019 DLC 2 mark 28.12.2010


. nly Boolean

functions in standard

)/ form can be

implemented using

/*!.

ny Boolean functions

in )/ form can be

implemented using /1.

ny Boolean functions

in )/ form can be

implemented using

/1.

UNIT V

VHDL

1. D-?+- VHDL. J+- 2010;

A?D1 is a Aery ?igh )peed @ntegrated Circuit ?ard#are Description 1anguage.

This hard#are description language is used to describe the behaviour and structure of

digital system.

2. L=# #/- ">-$#"= =- + VHDL. J-+ 2010;.

Binary logical operators: MD, *, MMD, M*, I*, IM* *elational operators: G 4G Q QG O OG

)hift operators: sll srl sla sra rol ror

dding perators: H % 3Concatenation5

Pnary sign operators: H

!ultiplying operators: R 4 mod rem

!iscellaneous operators: not abs RR

3. /$# = -$+# 68 P$$-=

/ac'age is used to provide a convenient method to store and share declarations

that are common for many design units. @t is represented by:

• a pac'age declaration and

• a pac'age body

4. /$# = >$$- -%$$#"+ * >$$- 6"8

@t contains a set of declarations that may be shared by various design units.

@t defines items #hich are made visible to other design units.

pac'age body contains the hidden details of a pac'age. ie., @t contains

the behaviour of the subprograms and the values of the deferred constants #hichare declared in a pac'age declaration.

5. /$# $- #/- #8>-= "? $#$ #8>-=

There are four types of data types:

6. )calar type

9. Composite types

=. ccess types

. (ile types

&. N$- #@" =6>"$= $+ - #/- ??--+- 6-#@--+ #/-=- #@".

7/18/2019 DLC 2 mark 28.12.2010


6. (unction 9. /rocedure

nly one output is possible in function.

!any outputs possible using procedure.

:. #- #/- =8+#$ ?" ORGENERATE =#$#--+#.

2enerateSlabel: for identifier in range generate

beginU

concurrent statements-

end generategenerateSlabelU-

7. C">$- =+$% $+ $$6%-.

Aariables must be declared #ithin the process in #hich they are used and

are local to that process. )ignals must be declared outside of a process. )ignals

declared at the start of an architecture can be used any#here #ithin that

architecture.

9. L=# #/- =8+#$ "? AIT UNTIL =#$#--+# @#/ -$>%-.

ait until BooleanS expression -

ait until a G b-

10. D-?+- =-+=##8 %=# ?" >"-== =#$#--+#.

process have the form /rocess 3 sensitivity list5

Begin )equentialstatements

0nd process-

11. C">$- 6-/$"$% %--%, $#$ ?%"@ %--% $+ =##$% %--% "? -=6+ $

#$% =8=#- + VHDL

B-/$"$% %--% D$#$ ?%"@ %--% S##$% L--%

digital system in A?D1

is described in terms of its

function.

digital system in A?D1

is described by giving the

logic equations.

digital system in

A?D1 is described by

specifying the

interconnections of the

gates.

12. M"-% 4 #" 1 MU' =+ $ =-%-#- =+$% $==+-+# =#$#--#.

f QG i #hen selG

else i6 #hen sel G6 else i9 #hen sel G9

7/18/2019 DLC 2 mark 28.12.2010


else i=-

13. G- #/- >"$ =##- "? VHDL.

entity entityname is

declaring input ,output variables

end entityname-

architecture architecturename of entityname is

signal declaration

begin

end

architecturename-

14. /$# = "+-+# "-

Concurrent code are A?D1 signal assignment statements in #hich they are

not contained in A?D1 process or bloc'.

0g.,

C QG and B after J ns-

0 QG C or D after Jns-

15./$# = #/- =86"% !

The symbol QG is the signal assignment operator , #hich indicates the value

computed on the right side is assigned to the signal on the left side.

0g.,

C QG and B -

0 QG C or D -

1&.G- #/- VHDL "- ?" ?%% $-.

entity fulladder is port3 x,y cin : in bit-

entity

architecture

entity

architecture

module6

entity

architecture

moduleM

7/18/2019 DLC 2 mark 28.12.2010


cout,sum: out bit5-

end fulladder-

architecture equations of fulladder is

begin sumQGx xor y xor cin after 6 ns-

coutQG3x and y5 or 3x and cin5 or 3y and cin5 after 6 ns-

end equations-

1:. G- #/- "-%+ "? =--+#$% %" + VHDL >"-==.

process3sensitivitylist5

begin

sequentialstatements

end process-

17. /$# = =--+#$% "-

process3sensitivitylist5

begin

sequentialstatements

end process-

henever one of the signals in the sensitivity list changes, the

sequentialstatements in the process body are executed in sequence one time.

19. /$# = #/- =- "? VHDL ">%-

The A?D1 compiler also called an analyNer ,first chec's the A?D1 source

code to see that it conforms to the syntax and rules of A?D1.

20. /$# = -%$6"$#"+

The A?D1 intermediate code must be converted to a form that can be

used by the simulator. This is called elaboration.

21.G- #/- -+-$% ?" "? $$6%- -%$$#"+.

variable listofvariablenames:typeSname:GinitialSvalueU-

22. G- #/- -+-$% ?" "? =+$% -%$$#"+.

signal listofsignalnames:typeSname:GinitialSvalueU-

23. G- #/- -+-$% ?" "? "+=#$+# -%$$#"+.

7/18/2019 DLC 2 mark 28.12.2010


constant constantSname : typeSname:GconstantSvalue-

eg., constant delay6:time:G J ns-

24. G- #/- VHDL >"$ ?" D ?%> ?%">.

library ieee-

use ieee.stdSlogicS66<.all-

entity dfff6 is

port 3D,C1$,reset:in stdSlogic-

&:out stdSlogic5-

end dff6-

architecture archSdflipflop of dff6 is

begin

process3C1$5

begin

if3C1$"event and C1$G"6"5 then

if reset G"" then

&QG""-

else

&QGD-

endif- endif-

end process- end-

25. /$# = --+#

change in a signal is called an event. 0ach time an event occurs ,any

processes that have been #aiting on the event are executed in Nero time, and any

resulting signal changes are queued up to occur at some future time.

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DLC 2 mark 28.12.2010