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Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DDCharacterization and
Performance of Visible Light Photon Counters (VLPCs) for the Upgraded DØ Detector at
the Fermilab TevatronDon Lincoln
Fermi National Accelerator Laboratory
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPCs for DØ
VLPC: Visible Light Photon Counter Solid state photon detectors Detects single photons Operate at a few degrees Kelvin Can work in a high rate environment Quantum efficiency ~80% High gain ~40 000 electrons per
converted photon Low gain dispersion
The DØ detector uses VLPC readout for the following subsystems:
The scintillating fiber tracker: 76 800 VLPC pixels The central and forward preshower: 19 968 VLPC pixels
scintillating strips of triangular cross-section
Visible
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPC Operation
Based on the phenomenon of Impurity Band Conduction, occurring when a semiconductor is heavily doped with shallow donors or acceptors
Electrical transport occurs by charges hopping from impurity site to impurity site
In VLPC’s, the silicon is heavily doped with arsenic atoms
Impurity band 0.05 eV below the conduction band
Normal 1.12 eV valence band used to absorb photons
The 0.05 eV gap used to create an electron-D+
avalanche multiplication Small gap means low field needed
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD
D+ flow
E field
Undoped Silicon
Doped Silicon Layer
•+ •-
IntrinsicRegion
GainRegion
DriftRegion
Photon
•e •h
Spacer and
Substrate
VLPC Operation
Cross Section
Electric Field Distribution
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPC Fabrication
The VLPCs fabricated on a silicon wafer, highly doped with antimony that serves as a common cathode
Series of layers are grown by vapor-phase epitaxy
Active VLPC structure Silicon layer, heavily doped with
arsenic donor atoms and lightly doped with acceptor boron atoms
The arsenic atoms form an impurity band The boron atoms shape the electric field When a bias voltage is applied, doped silicon layer
divides – Gain Region: linear field region– Drift Region: constant field region
An undoped silicon layer tops the doped silicon layer
3”(7.6 cm)
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPC History
1987 published paper on SSPM Solid State Photo-Multipliers
sensitive into infra-red region
1989 HISTE Proposal Submitted High-Resolution Scintillating Fiber Tracker
Experiment Main goal: to suppress sensitivity in infrared
region
1991-1992 HISTE I, HISTE II, HISTE III 1993 HISTE IV
Visible QE ~60%, Cosmic Ray Test at Fermilab
1994 HISTE V High QE High Gain HISTE VI large scale production based on
HISTE V
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD HISTE-VI VLPC chip
1 mm pixels 2x4 array (HISTE-VI) To be assembled into 1024 pixel cassettes Excellent individual photoelectron resolution Actual performance dependent on many
parameters
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD In DØ, VLPCs Housed in 1024 Channel Cassettes
1024 VLPC pixels in one cassette Electronic readout:
custom SVXII chips
SVX Readout (ADC Counts) of Cassette A (T=8.2K, V=7V)
0
100
200
300
400
500
600
40 60 80 100 120 140 160 180 200
3’
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD The DØ Scintillating Fiber Tracker
8 nested cylinders r = 20 51 cm
On each cylinder scintillating fibers
2.5m or 1.7 m, long 835 um diameter
Fibers arranged into 1 axial doublet 1 stereo (u or v) Constant pitch
Total channel count >77K
Clear fiber, 7 - 11m long, brings signal to VLPCs
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DDVLPCs in the High
Background Environment at DØ
In Run II of the Fermilab Tevatron luminosity will reach 2x1032cm-2sec-1
The VLPCs that read out fibers closest to the beam will count photoelectrons at a rate of 10 MHz
The VLPCs attached to the outermost fibers will see a rate of about 2.5 MHz
The characterization of all chips was made at the background rate of 20 MHz
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Debiasing at High Rate
High rates: lower gain and QE
Degradation minimal if Bias set higher than
the bias at no background
Temperature of about 9K (7K typical for no background)
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Modeling of High Rates
Modeled by treating Drift Region as an internal resistor in series with an ideal VLPC
The additional current of D+
carriers (impurity-band holes) generated by background photons increases voltage drop in the Drift Region at the expense of the field in the Gain Region (integral of the field = the bias voltage)
External bias must be increased to restore the field in the Gain Region
D+ flow
E field
Undoped Silicon
Doped Silicon Layer
Gai
n Reg
ion
Drif
t Re
gion
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPCs at High Rate
By increasing the bias voltage on the VLPCs we recover the quantum efficiency and gain, however, at the expense of a higher rate of dark counts
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Characterization Procedure
The test cryostat houses 14 VLPCs under test and one reference VLPC
Temperature is 9 K Background LED pulses at 10
MHz, with 2 photoelectrons/pulse Signal LED pulses at 500 Hz,
with 2 photoelectrons/pulse10 60s2 ms s
VLPC biasCryostat
PreamplifierBoard
Preamppower
HP 8112APulse Generator
LED
VLPC
Delay
Gate
input
LeCroy2249A
Transformer
PC
ITC4
Background
SignalHP 8112APulse Generator
LED zz
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Analysis Technique: Summary
Set background photoelectron rate (20 MHz) Set signal rate (1.75 photoelectrons @ 500 Hz) Find threshold (0.5% noise rate, 100 ns gate [0.35% in
DØ])
Find gain (typically 40 000 (or 80 LeCroy 2249 ADC counts per photoelectron))
Find photoelectron yield Determine quantum efficiency (typically 80% @ 0
MHz)
Determine DØ single fiber trigger efficiency (assume 9 pe/mip)
Vary voltage to maximize triggering efficiency
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Analysis: Gain and Yield
Gain determined by separation between peaks
13 ADC counts per femtocoulomb
Typical Gain 40 000
Yield (pe.) NPE =
(Average -Pedestal)/Gain
same voltage)
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Analysis: Threshold
VLPCs at operating temperature (9 K)
VLPCs at operating voltage (6.2-8.0 V)
Pedestal run taken Large 0-pe peak,
much smaller 1-pe peak
Threshold set at 50kHz (Typically 1.2-1.6 pe)
99.5%
ADC Counts
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Analysis: Efficiency
NMIP,the number of photoelectrons expected from a minimum ionizing particle in the DØ fiber tracker: NMIP = NPEx9/2 9 photoelectrons observed in the prototype of
the DØ tracker in a cosmic ray test 2 is the number of photoelectrons in this
setup, in the reference VLPC chip
Efficiency is the probability that the signal, which is assumed to have Poisson distribution with mean, NMIP, is greater than the threshold
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Acceptance Criteria
Data taken at several values of the bias voltage in steps of 0.2 V
Operating bias: average of pixels’ efficiency is a maximum (not Quantum Efficiency)
Chip accepted if at the operating voltage The efficiency of each pixel greater than
0.99 The gains of all pixels similar
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD VLPCs for DØ
VLPC’s manufactured in two distinct cycles First 1/3 (higher gain) Then 2/3 (lower gain)
13 300 needed including 10% spares 17 845 tested at 20 MHz 15 541 accepted
Yield: 87% Attempted recovery of
failed chips underway.
0 MHz results 382 chips
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Efficiency, Bias Voltage
Efficiencymuch higher than
the required minimum 0.99
Operating Bias Voltageranges from 5.8 V to 8.0 V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0.994 0.995 0.996 0.997 0.998 0.999 1
Efficiency (Fraction)
Fre
qu
en
cy
0
500
1000
1500
2000
2500
3000
3500
5.6 6.1 6.6 7.1 7.6 8.1
Voltage (V)
Fre
qu
en
cy
V V
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50 60 70 80
Gain (in Thousands)
Fre
qu
en
cy
0
200
400
600
800
1000
1200
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gain RMS (%)
Fre
qu
en
cy
Gain
Gains (in thousands)Range from 20 000 to 60 000
Gain dispersion of the pixels within one chipAbout 1.5 %
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Threshold
Thresholds for 50 kHz dark count rateRange from 1.2 to 1.8 pe
RMS of threshold dispersion of the pixels within one chipAbout 0.03 pe
0
500
1000
1500
2000
2500
1 1.2 1.4 1.6 1.8 2
Threshold (pe)
Fre
qu
en
cy
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Threshold RMS (pe)
Fre
qu
en
cy
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Threshold
Thresholds in fCRange from 5 fC to 15 fC
0
500
1000
1500
2000
2500
3000
0 5 10 15 20 25
Threshold (fC)
Fre
qu
ency
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Quantum Efficiency and Threshold
Algorithm selects voltage where noise begins to grow, not at maximum Quantum Efficiency
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Qualitative Threshold
Noise grows very quickly, once a voltage threshold is exceeded.
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Gain Behavior
Gain poorly correlated with voltage, but relative gain extremely correlated.
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Temperature Behavior
Temperature affects response.
All plots normalized to signal at 9 K (nominal operating temperature).
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Linearity at 0 MHz Background
VLPC’s are linear to <10% for Equivalent PE ~600 (~750 photons)
Slight gain dependence, although gain is only tangentially related.
Deviation from Linearity of VLPC, Representative Chips
-100
-80
-60
-40
-20
0
20
40
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Equivalent Photoelectrons = QE(for one pe) * photons
Dev
iati
on (
%)
Response of High Gain VLPC
0.1
1
10
100
1000
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Equivalent Photoelectrons = QE(for one pe) * photons
Inte
gra
ted
Ch
arg
e (A
rbit
rary
Un
its)
measured
linear reference
Gain ~50 000
Gain ~30 000
Normalization Point
MeasurementArtifact
Don Lincoln, Fermi National Accelerator Laboratory, Instr’99, 15-19 November 1999
DD Summary
Test yield 87%, higher than anticipated Chips need to be sorted because of the spread
in the bias voltage and threshold One bias per 8 VLPC chips in DØ detector One threshold per 8 VLPC chips in the DØ trigger
electronics
All pixels belonging to one chip have nearly identical efficiencies, gains, and thresholds
Operating phase space complex Temperature, Voltage, Rate, Gain, Threshold,
Efficiency
We will make calibration runs to adjust operating voltage and thresholds to the actual background seen in the experiment