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Doping: Depositing impurities into Si in a controlled manner

Doping: Depositing impurities into Si in a controlled manner

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Page 1: Doping: Depositing impurities into Si in a controlled manner

Doping: Depositing impurities into Si in a controlled manner

Page 2: Doping: Depositing impurities into Si in a controlled manner

Overview Diffusion vs Implantation Mechanism,Models Steps Equipment

Page 3: Doping: Depositing impurities into Si in a controlled manner

Goal:Controlled Junction DepthControlled dopant concentration and profile

Wafer (Substrate): P Type

N “well”

Preferred location of maximum concentration need not be the surface

P+P+

Source

Drain

Page 4: Doping: Depositing impurities into Si in a controlled manner

Diffusion & Ion Implanatation

Ion Implantation

SOURCE

IonsElectricField Junction is where N

= PCan also be used when doping N in N

Bombardment of ions

OXIDE BLOCK

Wafer (Substrate)`

Page 5: Doping: Depositing impurities into Si in a controlled manner

Diffusion & Ion Implantation

Diffusion Solid-in-solid high temperatures (1000 C) Distances covered are in um or nm

OXIDE BLOCK

Wafer (Substrate)`

Diffusion

Page 6: Doping: Depositing impurities into Si in a controlled manner

Mechanism , Models Substitutional (10-12 cm2/s) Interstitial replacement (10-6 cm2/s) Interstitial movement Substitutional preferred (better control) Au, Cu diffuse by interstitial mechanism B, P etc by substitutional mechanism

Two ideal cases Constant source, limited source Using Fick’s First & second law

J = Flux D - Diffusivity of A in B N- Concentration x - distance

NJ D

x

2

2

N ND

t x

Page 7: Doping: Depositing impurities into Si in a controlled manner

Models

Constant Source Concentration at x=0 is No

Complementary Error Function

Total Dose Q

( , ) ( )2

o

xN x t N erfc

Dt

Limited source Dose Q = constant Approx by Delta Fn

0

0

( , ) 2Dt

Q N x t dx N

2

4( , ) ex

DtQN x t

Dt

(0, ) oN t N

( , ) 0N t

( ,0) 0N x 0,

0x t

N

x

( , ) 0N t

( ,0) 0N x

0

( , )N x t dx Q

Page 8: Doping: Depositing impurities into Si in a controlled manner

Models Constant Source

Concentration at x=0 is No

21

3

N0

Distance from Surface

Impu

rity

Con

cent

rati

on

Important Parameter : Dt

species, temp and time

Page 9: Doping: Depositing impurities into Si in a controlled manner

Models Limited Source

Dose Q

21 3

N0

Distance from Surface

Impu

rity

Con

cent

rati

on

Important Parameter : Dt

Area under the curve is constant

If you normalize, erfc drops faster than Gaussian

Page 10: Doping: Depositing impurities into Si in a controlled manner

Diffusivity Diffusivity

Follows Arrhenius behavior Wafer goes through heating cycles many times in the process Effective Diffusivity * time = sum (Diffusivity * time) Concept of thermal budget

0

E

kTD D e

1000T

D i itotali

Dt D t

Page 11: Doping: Depositing impurities into Si in a controlled manner

Diffusion Max absorption (at a given temp) Usually quite high Good for emitter and collector, but not for base Not all dopant can contribute to electron/hole near solubility limit

Solubility limit in the range of 10 20/cm3 at 1000o C

Diffusion into silicon Faster on grain boundaries 10 times in poly silicon Diffusivity in SiO2 usually very low (Segregation occurs)

Page 12: Doping: Depositing impurities into Si in a controlled manner

Junction Formation

N

P

Distance from surface

ImpurityConc

CarrierConc

Jn

Page 13: Doping: Depositing impurities into Si in a controlled manner

Diffusion: Drive In: Dopant re distribution

Deposited dopant must be pushed into SiRe-distribution of dopant Oxidation of exposed Si to protect

Dopant Diffusion

OXIDATION

*Dopant profile changes due to diffusion* Also due to preference for Oxide/Silicon: N-type piles up in Si, P-type depletes in Si

Page 14: Doping: Depositing impurities into Si in a controlled manner

Diffusion: Steps

OXIDE BLOCK

1.Pre CleanTo remove particlesThin oxide grows

2.HF EtchTo remove oxideNot too much!

3.Deposit (pre dep)Deposit enough to be higher than the solubility limit

4.Drive In High temp to enable diffusion inside SiAlso forms SiO2 (with high dopant concentration)2-STEP diffusion (usual)

5.Deglaze (HF Etch) Oxide may act as dopant source in future stepsRemoving highly doped oxide may be problem (for dry etch)

DepDiffusion

Page 15: Doping: Depositing impurities into Si in a controlled manner

Diffusion: Dep: schematic

Wafers are Horizontal

Vertical

Better UniformityLess wafers per batch

Poor UniformityMore wafers per batch (or can have smaller chamber)

Dummy wafers placed in the beginning & end

GasFlow

GasFlow

Page 16: Doping: Depositing impurities into Si in a controlled manner

Doping: Gas phase

Dopant can be in Gas/Liquid/Solid state, but is typically carried using N2 in gaseous form

Chamber

Reaction gas

Carrier Gas (N2) + Source

*Carrier gas may be bubbled through liquid source*Carrier gas may pass over heated solid source* inert gas can provide volume to maintain laminar flow

Page 17: Doping: Depositing impurities into Si in a controlled manner

Doping: Gas phase

2 5 22 5 4 5PO Si P SiO

3 2 2 5 24 3 2 6POCl O PO Cl

3 2 2 5 22 4 3PH O PO H O

Phosphorus oxy chloride

Phosphine

2 3 22 3 3 4As O Si SiO As Arsenic Oxide

Diborane 3002 6 2 2 3 23 3

oCB H O B O H O

2 6 2 2 3 26 3 6B H CO B O H O CO

2 3 22 3 4 3B O Si B SiO Boron Tribromide

3 2 2 3 24 3 2 6BBr O B O Br

Reaction/Diffusion Limited

Page 18: Doping: Depositing impurities into Si in a controlled manner

Solid phaseSolid Source

Slugs between wafersLower through putCleaning is issue (slugs can break)Safer to handle(no toxic vapor at room temp)

Spin coating (with solvents)Similar to photo resist coatingCost of extra spin/bake stepsthickness variations

Page 19: Doping: Depositing impurities into Si in a controlled manner

Doping: Solid phase

2 3 22 3 4 3B O Si B SiO

Boron Trioxide

Tri Methyl Borate (TMB)900

3 3 2 2 3 2 22( ) 9 6 9oCCH O B O B O CO H O

2 5 22 5 4 5PO Si P SiO Phosphorous pentoxide

2 3 22 3 3 4As O Si SiO As Arsenic Oxide

Antimony Tri Oxide2 3 22 3 3 4Sb O Si SiO Sb

Page 20: Doping: Depositing impurities into Si in a controlled manner

IssuesSide diffusion

Increases with temperature/timeLimits the space between devices

Maximum dopant concentration is near surface==> majority of current near surface(Surface tends to have max defects)==> less control

Dislocation generation (thermal drive in)Surface contamination (dep)Low dopant concentration and thin junction (small junction depth) are difficult

At 0.18 um , junction depth is ~ 40 nmAt 0.09 um, junction depth may be 20 nm

Page 21: Doping: Depositing impurities into Si in a controlled manner

Issues: Side diffusionSide diffusion (Lateral Diffusion)

OXIDE BLOCK

Wafer (Substrate)`Diffusion

BLOCK

Page 22: Doping: Depositing impurities into Si in a controlled manner

Example of Real systems :

*Hitachi-Zestone VII*2m x 3m x 3m*300 mm wafer*one wafer at a time* lower thermal budget, * better control, uniformity* low throughput

*Hitachi-Vertron V*1m x 3.5m x 3.3m*200 mm wafer*150 wafers at a time* higher thermal budget, * good control, uniformity* high throughput

Page 23: Doping: Depositing impurities into Si in a controlled manner

Example of Real systems : Protemp

Page 24: Doping: Depositing impurities into Si in a controlled manner

GetteringTo remove unwanted impurities

Try to get them to the back of wafer Defects

Ar implant Dep SiN/SiO2 (stress)

Oxygen during crystal growth (intrinsic) High Conc P on back of wafer

Page 25: Doping: Depositing impurities into Si in a controlled manner

Measurement Sheet Resistance (average)

Four point probe, VDP (Van der Pauw) Bevel

Interference Dye

SIMS

Page 26: Doping: Depositing impurities into Si in a controlled manner

Diffusion: Summary Diffusion Temp, Time, Thermal budget Doping (more important for older nodes) Relevant for all nodes 2 step (constant source, limited source) Solid/Liq/Gas

Page 27: Doping: Depositing impurities into Si in a controlled manner

Ion Implantation “Somewhat similar” to Sputtering Dopant goes inside the silicon

sputtering deposits on the surface Used for controlled doping

concentration profile (depth)

Equipment Mechanism Issues Summary

Page 28: Doping: Depositing impurities into Si in a controlled manner

EquipmentNeutral Beam Trap and Beam Gate

Beam Trap and Gate Plate

900 Analyzing Magnet

Focus

Acceleration Tube

Y-Axis Scanner

I onSource

w afer in w afer Process cham ber

© Peter van Zant

Page 29: Doping: Depositing impurities into Si in a controlled manner

1. Ion Source

Gas or solid source (no liquid source) Solid heated to obtain vapor (P2O5)

effectively gas source Mass flow meters (to control the flow better) Gas usually Fluorine based

5 3 3 3 5, , , ,AsF BF SbF PF PF Ionization chamber

low pressure (milli/ micro torr) to ionize and minimize contamination heated filament (thermionic emission) positively charged ions created

Page 30: Doping: Depositing impurities into Si in a controlled manner

2. Analyzing

Selection, analyzing, mass analyzing, ion separation Similar to Mass Spectroscope Usually the second stage (before acceleration) Magnetic field to control the path Charge to Mass Ratio

Some of the species from BF3 source

Selection of B+

B

BF

2BF

2, ,B BF BF

Page 31: Doping: Depositing impurities into Si in a controlled manner

3. Acceleration Acceleration needed for implantation Positive ions accelerated with ring anodes Energy range: 5 keV for low, 2 MeV for high

Medium current : 1 mA High current: 10 mA Current ~ Dose Beam Focus (magnetic/electric)

Accln Energy

Bea

m C

urre

nt

High Energy

Low Energy

Low Current

High Current

High Current Oxygen

keV MeV

1 mA

10 mA

100 mA

High energy ==> high throughput

few seconds per wafer

SOI

Page 32: Doping: Depositing impurities into Si in a controlled manner

4. Scanning Beam size ~ 1 sqr cm Wafer size 200 mm or 300 mm Issues:

neutral atoms need to be removed because... dose calculated by current integrator

Electrical (beam) scanning & Mechanical (wafer) scanningBeam Scan:(medium current)

beam moves outside the wafer for turn controlling XY plates may be destroyed by discharge Rotate wafer for uniformity

Wafer scan: (high current)

Beam shuttering: (electrical/mechanical) turn beam off when not on wafer

Page 33: Doping: Depositing impurities into Si in a controlled manner

5. Target chamber End chamber low particle, high vacuum Wafer held on

clamp (more particles) OR ESC (less particles) Anti-static devices on the chamber Integrate the current to measure dose

For 2+ ions, divide by 2 and so on... Wafer charging:

minimize by connecting wafer to ground (with a charge counter) dielectrics may get damaged use flood gun to provide electron (and count it in measurement)

Page 34: Doping: Depositing impurities into Si in a controlled manner

Mechanism

Inelastic collision:Electron (ionization)Nuclear (nuclear reactions)

Elastic collisionElectronNuclear (atom substitution)

Electrons attract the +vely charged ions Nuclei repel the +vely charged ions

At low energy Nuclear collisions predominant At high energy electronic collisions predominant

Variation in ‘stopping cross section’ Gaussian profile expected (projected range Rp)

Page 35: Doping: Depositing impurities into Si in a controlled manner

Implantation Mask with Photoresist or oxide

resist for medium and low energy, moderate dose high energy/high dose: increase in temp

Resist re-flow Cross link (for organics)

less soluble (stripping an issue) Faraday Cage

Retain secondary electron from wafer Otherwise, wafer under dosed -Ve Bias

e-

Page 36: Doping: Depositing impurities into Si in a controlled manner

Issue: Transverse Straggle

implant

Even in implantation, dopants present in lateral direction

OXIDE BLOCK

Transverse Straggle(Diffraction)

Gaussian

Page 37: Doping: Depositing impurities into Si in a controlled manner

Channeling

Some ions will move through“channels”without experiencingnuclearor electroncollision fora “long” time

==> No Gaussian Profile

Page 38: Doping: Depositing impurities into Si in a controlled manner

Channeling1. Hold the wafer at an angle (~ 8 degree)

BLOCK

Also causes “shadow”

==> increase transverse straggle(called undercut)

Shadow Undercut

==> Too much angle isalso a problem

Page 39: Doping: Depositing impurities into Si in a controlled manner

Channeling

OXIDE BLOCK

2. Dep amorphous material on the top

It has to be very thin and not stop ions

implant

3. Damage top of wafer and make it amorphous (eg high energy silicon implant)

Page 40: Doping: Depositing impurities into Si in a controlled manner

Channeling

4. Increase temperature==> reduce channel cross section

Channeling critical angle ~ (Z/E) 1/2

==> Low energy implants more likely to channel

Page 41: Doping: Depositing impurities into Si in a controlled manner

TED Transient Enhanced Diffusion Damage during implantation

==> point defects (vacancies) interstitial silicon atoms reduced during anneal

Channel dopant diffuse to surface==> VT modification

©Solid State Technology

Page 42: Doping: Depositing impurities into Si in a controlled manner

RTA Anneal to heal the damage Diffusion during anneal an issue

High temp repair is faster than anneal Repair energy barrier 5 eV, diffusion barrier 3 or 4 eV

1. Adiabatic (laser, heats surface , < micro sec) profile control difficult (not used)

2. Thermal flux ( micro to 1 sec) laser, ebeam, flash lamp surface+bulk heating rapid cooling ==> point defects

3. Iso thermal (W-Halogen lamp) 30 sec (1100 C)

Page 43: Doping: Depositing impurities into Si in a controlled manner

Diffusion vs Ion Implantation

Dep+Diffusion: depends on chemical nature and solubilityImplantation: on energy of ion beam

Expensive

Better Control of junction depth, dose, profileLess ‘transverse straggle’