DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

The 2004 ITRS

Assembly and Packaging Roadmap

Joe Adam TWG Co-Chair

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Key Packaging Chapter Contributors

Ryo Haruta – Renesas Dan Evans – Palomar TechEnboa Wu – ITRI/NTUShoji Uegaki – KyoceraKuniaki Takahashi – ToshibaHisao Kasuga – NECCoen Tak - PhilipsMark Bird - Amkor Bill Bottoms - 3MTSSteve Adamson - AsymtecChi Shih Chang – SMS Bill Chen – ASE

Mahadevan Iyer - IMEBernd Roemer - InfineonHenry Utsunomiya – ICT Jurgen Wolf – IZMJoe Adam – Skyworks Rainer Kyburtz - ESECJack Fisher - IPCGeorge Harman – NIST Chuck Woychik – PlexusSanjay Dandia – PhilipsKeith Newman – Sun

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Near Term Industry Challenges

• We need to close the gap between semiconductor interconnect density and next level substrate density– Both Organic and Ceramic substrate density is improving but not as

fast as silicon I/O density – Higher temperature capability to support lead free solder in high

density organic substrates– Low cost embedded passives

• The impact of BEOL and Cu/low K on packaging – Direct wirebond to Cu or improved barrier systems for bondable

pads– Improve interfacial adhesion of dielectrics – Integrated fab/packaging process development, reliability, and test

criteria to identify and resolve interaction problems early in the technology development cycle

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Near Term Industry Challenges

• Tools and methodologies to address chip and package co-design – More efficient mixed signal co-design and simulation for chip and

package within the same environment RF requirements– More accurate thermal and mechanical simulation of complex

package microstructures, including materials data

• Assembly equipment productivity is not improving fast enough to meet package cost improvement requirements

• Reliability degradation due to electromigration in lead free and other package metallurgies

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Long Term Industry Challenges

• Small high frequency, high power density, high pin count die– Very high chip I/O density which require reliable

bumpless connections to meet thermal and electrical performance requirements

• New devices and materials (organic, MEMS, nanostructures, optical, biological) which require new packaging technologies

• System level design capability to integrate semiconductor, passive, interconnect and new device technologies in 3 dimensions

• 450 mm wafer technical issues ( thinning, wafer level packaging, etc.)

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Subcontract Package Cost Trends

Package Type 2004 2005 2006 2007 2008 2009 2010

Low cost 0.3 - .56 .3 - .53 0.27 - .5 0.26 - .48 0.25 - .45 0.23 - .43 0.22 - .41

Cost Performance .75–1.30 .71–1.24 .67–1.17 .64–1.11 .61–1.05 .58–1.00 .55–.96

High Performance 1.98 1.88 1.78 1.69 1.61 1.52 1.45

High Reliability 0.36–3.20 0.32–2.88 0.29–2.60 0.26–2.33 0.23–2.11 0.21–2.00 0.20–1.90

Minimum Cents Per Pin for Subcontract Packages

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

System In Package Technology Requirements

Year of Production 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018

Digital networks- max I/O 2600 2900 3000 3200 3500 3500 3500 3500 3500 3500 3500 3500

RF products - max I/O 150 200 200 200 200 200 200 200 200 200 200 200

Memory products - max I/O

Max number of stack die 6 7 8 8 8 8 8 8 8 8 8 8

Max number die in Module 10 12 12 12 12 12 12 12 12 12 12 12

Minimum Component size in. 0201 0201 01005 01005 01005 01005 01005 01005 01005 01005 01005 01005

Die Pad pitch - wirebond 40 35 35 30 30 25 25 25 25 25 25 25

Die pad pitch - flipchip 150 130 130 120 110 100 90 90 80 80 70 70

Embedded Passives in Laminate L L CL CL CL CL CL CL CL CL CL CL

Embedded Passives in Ceramic R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C

MSL Level 2a 2 2 2 2 2 2 2 2 2 2 2

Mx Reflow temp C 260 260 260 260 260 260 260 260 260 260 260 260

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Package Materials Requirements

Materials Challenges IssuesWirebond Materials that enable 20 micron pitch without wire sweep, barrier

metals for Cu wirebond pads to reduce intermetalic Underfills Ability to support 100 pitch on large die, reduce stress on low-K and

compatibility with lead free reflowThermal Interfaces Increased thermal conduction, improved adhesion, higher modulas for

thin applications Materials Properties Methodology and characterization database for frequencies above 10

GHz, Molding Compound Low modulas materials that reduce stress on low- wafer structures

with low miosture absorption for high temperature lead free

applications

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Package Materials Requirements

Leadfree Solder Flip Chip

Materials

Solder and UBM the supports high current density and avoid

electromigrationDie attach solder for T j >200C No feasible solution seen

Rigid Organic substrates Lower loss dielectric, lower TCE, and higher Tg at low cost

Flexible Organic Substrates Lower TCE and improved metal adhesion

Embedded passives Improved high frequency performance of dielectrics with K

above 1000 High reliability, better stability resistor

materials. Ferromagnetics for sensor and MEMs applications LTCC Low shrink dielectric and lower dielectric constant for high

frequency application

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Die to Package Interconnect Requirements

Table 96 Chip-to-next-level Potential Solutions

Year of Production 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018

Technology Node hp90 hp65 hp45 hp32 hp22

WAS Wire bond—ball 35 30 25 25 20 20 20 20 20 20 20 20

IS 40 35 35 30 30 25 25 25 25 25 25 25

WAS Wire bond—wedge 25 20 20 20 20 20 20 20 20 20 20 20

IS 30 30 25 25 25 20 20 20 20 20 20 20

WAS TAB* 35 30 30 25 25 25 20 20 20 15 15 15

IS 35 30 30 25 25 25 20 20 20 15 15 15

WAS Flip chip area array* 150 130 130 120 110 100 90 80 70

Chip Interconnect Pitch (µm)

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

Crosscut issues

• BEOL and low K/Cu integration into packaging

• Wafer Level packaging impact on interconnect

• Thinned die issues (test, FEOL)

• New device types and structures impact on packaging

• Design and Simulation (SIP, RF, etc.)