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Innovations that fitby Siemens Semiconductors
2nd Edition 1997
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Published by Semiconductor Group
Siemens Aktiengesellschaft Ordering No. B165-H7072-G1-X-7600Printed in GermanyWS 07972. 21-873
Global PartnerChip for Systems on Silicon
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Internet-address:
http://www.siemens.de/Semiconductor
A Success Story
Over the past few years, Siemenshas established technical leadershipin the production of DRAMs.Siemens began its MEGA programin the 80s in order to accelerate itsproduction of 1 M and 4 M DRAMs.
Siemens is now the sole DRAMmanufacturer in Europe, providing itscustomers with both 16 M and 64 MDRAMs. 256 M and 1 G memorydevices will be available in 1998 and2000, respectively.
Based on these programs, majorinvestments in new factories inDresden, Germany and NorthTyneside, UK allowed us to increaseour production. To speed up theglobalization of our chip productionwe entered into joint ventures withMosel Vitelic (Taiwan) and Motorola(USA).
In addition to the standard DRAMproduct spectrum Siemens nowoffers embedded DRAM solutions tothe world market.
New requirements for higher datatransmission speed, low powerdissipation and higher integrationlead to technologies based onDRAM which allow the integrationof both DRAM and logic.
These newest technologies offer thecustomer significant advantagesconcerning• system cost• performance with focus on
bandwidth and reduced powerconsumption
• design flexibility
Siemens employs and continuouslyimproves the technologies requiredfor embedded DRAM solutions.
Embedded DRAM:
DRAM plus additional Metal
Layers
Embedded DRAM technology usesthe 64 MBit and the 256 MBit trenchcapacitor DRAM process, with one ortwo metal layers added. This bringsyou leading-edge DRAM qualitytogether with high-performancelogic.
This way, our embedded DRAMtechnology roadmap directly followsour advanced DRAM technologies.The know-how from standard DRAM production goes straight intoembedded DRAM product quality.
The advantages of a trench cell forembedded DRAM are compelling:The capacitor lies below the surfaceof the silicon, giving a much moreplanar die than with stackedcapacitors. Adding one or two metallayers allows us to efficientlyintegrate high-performance logicwith up to five interconnect layers,together with uncompromizeddynamic memory.
As the capacitor is buried in the die,while the metal layers lie on top, it is much less sensitive to spurious signals than a stacked capacitorwould be. As a result, more fastswitching logic functions may beintegrated with less effect onmemory operation.
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Embedded DRAM Technology Roadmap
The latest Technology
Dresden Fab building
North Tyneside Fab building
Trench based DRAM by Siemens
Conventional stack based DRAM
19970.35 µm
0.24 µm
0.20 µm
0.18 µm
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Siemens Semiconductor Group hasbeen working with embedded DRAMproducts since 1989 and is able toprovide the latest technologies (whichdirectly follow the DRAM technologies)and wafer capacity to produce chipswith embedded DRAM.
The first products were designed forconsumer TV applications. One exampleis the Quarter PIP (Picture in Picture)shown in the photo. It is used tocreate insert pictures on TV screens.The embedded DRAM of this deviceis 330 Kbit in size.
Another example is the VoiceEngine.This product, which is dedicated tovoice processing applications(recognition, storage, synthesis)contains 1Mbit embedded DRAM, a 16 bit fixpoint DSP and 15 k gatescustomized logic as well as ROMand SRAM. The chip photo is shownoverleaf. The VoiceEngine is pro-cessed in the Dresden fab on the0.35 micron embedded DRAMtechnology. Production ramp up willbegin in the 1st quarter 1998.
Upcoming products using this tech-nology are - among others - devicesfor HDD and graphics applicationswhich contain controller cores,ROM, customized logic and from1Mbit to 24 Mbit of embedded DRAM.
We are preparedFor your embedded DRAM solutions
QPIP VoiceEngine
DRAM cores customized logic DRAM cores
SRAM DSP ROM
5 6
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Typical applications include signalprocessing or graphics devices whichbenefit from the large bandwidth ofthe embedded DRAM. Unified memory architectures offerthe advantage that all data is avail-able for input, output and the processor.They benefit from the wide internalinterface because the total memorybandwidth is dynamically sharedamong the different tasks using ahigh-speed arbiter.
Devices with separate customizedmemory blocks for each functionallow independent memory accesswhich ensures simultaneous processoroperation and access to the input andoutput buffers. The flexible embeddedDRAM organization implements therequired memory block size for eachunit.
Figure it outFI
GU
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Cutting customized eDRAMs
Memory structure of a sample applicationwith unified memory block
line bufferfor X-Y-scaling
controldata
interface(PCI bus)
datainput
datainput
ECCinput buffer
outputbuffer
dataoutput
dataoutput
unified memory
512
local data for processor
Z-buffer
RAMDAC
frame buffer arbiter
frame buffer (front&back buffer)
analog output
video data input
interface(PCI bus)
control data
texture memory
bank 0
bank 7
off-screen buffer(fonts, display lists,etc.)
Memory structure of a DVD device with separated memory blocks
Memory structure of a 3D graphics application with separated memory blocks
VideoEngine
2D GraphicsAccelerator
3D GraphicsAccelerator
Processor
controldata
interface
hig
h-s
pee
d a
rbit
er
LogicLogicCD
– high bandwidth with wide on-chip buses
– parallel access to separated memory
blocks
– reduced power consumption
– customized DRAM size
– reduced chip count and board space
– simplified board layout and test
– less EMI problems
Processor
Logic
Logic
DRAM
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Three programmable pipeline
stages
The synchronous Modular embeddedDRAM interface provides fast pagemode access.
A special feature is the programmablepipeline depth of one, two or threestages. Different pipeline optionsoptimize the timing of the buildingblock. The timing with two pipelinestages and a clock frequency of100 MHz is optimized for randomaccess with 30 ns random accesstime and 20 ns precharge time.Operation with three pipeline stagesenables higher clock frequencies ofmore than 133 MHz and acceleratesthe page access, resulting in lessthan 7 ns column access time.
One building block with 7 ns cycle time achieves data rates of up to8.5 Gbit/s in page mode. Multipleblocks configurations enable largedata buses with up to 512 bit buswidth. This results in a maximumbus throughput rate of 8.5 Gbyte/s.
100 MHz clock
Command
Row address
Column address
Data out
READ0 READ1 READ2ACTIV PRECH ACTIV READ3
ADR X ADR Y
ADR 0 ADR 1 ADR 2 ADR 3
DAT 1 DAT 2
10 ns
DAT 0
READ1 READ2 ACTIV
ADR X
READ0
ADR 1 ADR 2 ADR 0
PRECH ACTIV
ADR X
ADR 3
READ3
7 ns
DAT 1 DAT 0 DAT 2
133 MHz clock
Command
Row address
Column address
Data out
Build it up
Modular embedded DRAM or
standard DRAM Cores
Siemens embedded DRAM is basedon two complementary approaches:
• Modular embedded DRAM providescustomized memory blocks from256 Kbit to 48 Mbit
• Standard DRAM cores such as EDO,SDRAM or SGRAM may be inte-grated straight away.
Standard DRAM cores such as the16 Mbit EDO-DRAM provide optimi-zed die size while Modular embeddedDRAM gives best possible designflexibility. A customized interface isavailable for both options. Modularembedded DRAM includes thefollowing features:
• 256 Kbit building block• Customized memory size up to
48 Mbit in 0.24 µm technology• Flexible memory organization accor-
ding to the application• 8.5 Gbyte/s maximum bandwith
with an up to 512 bits wide bus• Small chip area: 4.1 mm2 for
2Mbit with a 128 bit interface in the0.24 µm technology
• Low power: less than 1 mW/MHzper active building block
• High-speed operation: 7 ns pagemode cycle time
• Optional test controller for built-inself test.
On high-integration blocks
Modular embedded DRAM: 256 Kbit building block with interface
Different configurations of 2 Mbit memory using Modular embedded DRAM
Key features of embedded DRAM options
Modular embedded DRAM timing with two pipeline stages
Increased throughput using three pipeline stages
Modular embedded DRAM standard DRAM core
technology 0.35 µm 0.24 µm 0.24 µm
building block size 256 kbit 256 kbit/1 Mbit 8 Mbit …64 Mbit
max. memory block size 16 Mbit 48 Mbit
die area for 2 Mbit (mm2) 8.8 4.1 2.8
power consumption per building block (mW/MHz) 1.5 1 1
max. clock frequency (MHz) 83 >133 166
page mode cycle time (ns) 12 <7 6
max bandwith (Gbyte/s with 512 bit interface) 5.3 >8.5 10.6
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Design FlowD
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For fast time to market
Design and manufacturing
Siemens provides production capacityand technology together with a designand foundry service which can betailored precisely to customer's needs:
Design service:Siemens does the design of thecustomized embedded DRAM. Any kind of customer specific logiccan be added by the customer.Depending on the customer's needs,standard cells through DSP coresand µC cores can be provided.Different entry points to the designflow are supported as well as elec-trical and timing verification.
Foundry service:Siemens manufactures the embeddedDRAM product. Different steps offoundry service are offered to chosefrom. Packaging and testing can be provided as required.
Further information is available onrequest in our Acquisition Package.
