DS427 PLB Synchronous DRAM (SDRAM) Controller · 2021. 1. 18. · It is assumed that the reader is familiar with the OPB and MCH protocol. Features: ... To allow the user to create

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Multi-CHannel OPB External Memory Controller (MCH OPB EMC) (v1.00a)

DS 500 March 16, 2006 0 0 Product Specification

IntroductionThe Xilinx Multi-CHannel On-Chip Peripheral Bus External Memory Controller (MCH OPB EMC) provides the control interface for external synchronous, asynchronous SRAM and Flash memory devices through the MCH OPB interface. It is assumed that the reader is familiar with the OPB and MCH protocol.

FeaturesThe MCH OPB EMC is a soft IP core designed for Xilinx FPGAs and contains the following features:

• Parameterizable number of channel interfaces that can be configured with a Xilinx CacheLink (XCL) protocol (see "Reference Documents")

• Supports optional OPB interface

• Supports single-beat and burst transactions

• Supports target word of 1, 4, 8 and 16 words for first XCL cache line transactions

• Supports synchronous/asynchronous SRAMs and Flash memory devices

• Supports memory data widths of 32-bits, 16-bits and 8- bits

• Supports data width matching (memory data width must be less than or equal to the OPB or the MCH data width)

• Supports configurable cycle time for read and write operations

LogiCORE™ Facts

Core Specifics

Supported Device Family

Spartan™-3, Virtex™-II Pro, Virtex-4

Version of Core mch_opb_emc v1.00a

Resources Used

Min Max

Slices Please refer to Table 13, Table 14 and Table 15

LUTs

FFs

Block RAMs

Provided with Core

Documentation Product Specification

Design File Formats VHDL

Constraints File N/A

Verification N/A

Instantiation Template

N/A

Reference Designs None

Design Tool Requirements

Xilinx Implementation Tools

ISE 8.1i or later

Verification N/A

Simulation ModelSim SE/EE 6.0 or later

Synthesis XST 8.1i or later

Support

Support provided by Xilinx, Inc.

Discontinued IP

DS 500 March 16, 2006 www.xilinx.com 1Product Specification

© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties

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MCH OPB EMC Design ParametersTo allow the user to create a MCH OPB EMC that is uniquely tailored for the system, certain features are parameterizable in the MCH OPB EMC design. This allows the user to have a design that only utilizes the resources required by the system and runs at the best possible performance. The features that are parameterizable in the MCH OPB EMC are shown in Table 1.

Table 1: MCH OPB EMC Design Parameters

Generic Feature / Description Parameter Name Allowable ValuesDefault Value

VHDL Type

MCH OPB EMC Parameters

G1Target FPGA family C_FAMILY

spartan3, virtex2p, virtex4

virtex2pstring

G2 Number of memory banks

C_NUM_BANKS_MEM(1) 1-41

integer

G3 Arbitration mode between MCH and OPB

C_PRIORITY_MODE0 = Fixed priority mode

1 = Not supported

0integer

G4Include OPB slave interface

C_INCLUDE_OPB_IPIF0 = Don’t include OPB IPIF

1 = Include OPB IPIF

1integer

G5Includes support for OPB bursts

C_INCLUDE_OPB_BURST_ SUPPORT

0 = Don’t include the logic for OPB bursts

1 = Include the logic for OPB bursts

0

integer

G6 Data bus width for MCH and OPB

C_MCH_OPB_DWIDTH 3232

integer

G7 Address bus width for MCH and OPB

C_MCH_OPB_AWIDTH 3232

integer

G8

Input/output data and control signals using the falling edge of the clock

C_INCLUDE_NEGEDGE_ IOREGS(2)

0 = Don’t include negative edge IO registers (data and control signals are input/output on the rising edge of the clock)

1 = Include negative edge IO registers (data and control signals are input/output on the falling edge of the clock)

0

integer

G9 Width of memory bank x data bus

C_MEMx_WIDTH(1) 8, 16, 3232

integer

G10 Execute multiple memory access cycles to match memory bank x data width to MCH and OPB data width

C_INCLUDE_DATAWIDTH_ MATCHING_x(1,3)

0 = Don’t include data width matching

1 = Include data width matching

0

integer

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G11Memory type of memory bank x

C_SYNCH_MEM_x(1)

0 = Memory type is asynchronous

1 = Memory type is synchronous

0

integer

G12 Pipeline delay (in clock cycles) of memory bank x

C_SYNCH_PIPEDELAY_x(1) 1, 2 2

integer

Memory Bank Timing Parameters

G13 Read cycle chip enable low to data valid duration of memory bank x

C_TCEDV_PS_MEM_x(1,4,5)Integer number of picoseconds

15000(15)

integer

G14 Read cycle address valid to data valid duration of memory bank x

C_TAVDV_PS_MEM_x(1,4,6)Integer number of picoseconds

15000(15)

integer

G15 Read cycle chip enable high to data bus high impedance duration of memory bank x

C_THZCE_PS_MEM_x(1,7,8)Integer number of picoseconds

7000(15)

integer

G16 Read cycle output enable high to data bus high impedance duration of memory bank x

C_THZOE_PS_MEM_x(1,7,9)Integer number of picoseconds

7000(15)

integer

G17 Write cycle time of memory bank x

C_TWC_PS_MEM_x(1,10,11)Integer number of picoseconds

15000(15)integer

G18 Write enable minimum pulse width duration of memory bank x

C_TWP_PS_MEM_x(1,10,12)Integer number of picoseconds

12000(15)

integer

G19 Write cycle write enable high to data bus low impedance duration of memory bank x

C_TLZWE_PS_MEM_x(1,13,14)Integer number of picoseconds

0(15)

integer

Auto Calculated Parameter(16)

G20 Maximum data width of the memory devices in all banks

C_MAX_MEM_WIDTH(1) 8, 16, 3232

integer

Address Space Parameters

G21Base address of memory bank x

C_MEMx_BASEADDR(1) Valid address range(17)None(17) std_

logic_ vector

Table 1: MCH OPB EMC Design Parameters (Continued)


VHDL Type

Discontinued IP




Notes: 1. x = values for memory banks 0 to 3, but currently supports only one bank of memory.2. This parameter should only be set to 1 under the following conditions:

· Tfpga_outdelay + Tsetup_memory + Tboard_route_delay < Clock_period/2 · Tmemory_outdelay + Tfpga_setup + Tboard_route_delay < Clock_period/2

3. Always set this parameter to 1 when C_MEMx_WIDTH < C_MCH_OPB_DWIDTH4. Read cycle time is the maximum of C_TCEDV_PS_MEM and C_TAVDV_PS_MEM.

G22High address of memory bank x

C_MEMx_HIGHADDR(1) Valid address range(17)None(17) std_

logic_ vector

Simulation Only Parameter

G23MCH/OPB clock period C_MCH_OPB_CLK_PERIOD_PS

Integer number of picoseconds

10000integer

MCH Interface Parameters

G24 Number of MCH channels

C_NUM_CHANNELS 1-42

integer

G25 Interface protocol for channel x (x = 0 to 3)

C_MCHx_PROTOCOL(18) 0 = XCL protocol0

integer

G26 Depth of the access buffer for channel x (x = 0 to 3)

C_MCHx_ACCESSBUF_DEPTH 4, 8, 1616

integer

G27 Depth of the read data buffer for channel x (x = 0 to 3)

C_MCHx_RDDATABUF_ DEPTH(19)

0, 4, 8, 1616

integer

XCL Channel Parameters

G28 Size of the cacheline in number of 32-bit words for each channel x configured as an XCL channel

C_XCLx_LINESIZE(20) 1, 4, 8, 16

4

integer

G29Type of write transactions for each channel x configured as an XCL channel

C_XCLx_WRITEXFER(20,21)

0 = No write transfers

1 = Single transfers only

2 = Cacheline transfers only

1

integer

G30Include time out counter for MCH read transfers

C_INCLUDE_TIMEOUT_ CNTR(22)

0 = Don’t include an acknowledge time out counter

0

integer

G31 Number of clocks to wait for a transfer acknowledge from the MCH OPB EMC before issuing a time out error

C_TIMEOUT 1-512

16

integer

Table 1: MCH OPB EMC Design Parameters (Continued)


VHDL Type

Discontinued IP




5. Chip enable low to data valid, C_TCEDV_PS_MEM, is equivalent to tACE for asynchronous SRAM and tELQV for Flash in the respective memory device data sheets.

6. Address valid to data valid, C_TAVDV_PS_MEM, is equivalent to tAA for asynchronous SRAM and tAVQV for Flash in the respective memory device data sheets.

7. Read cycle recovery to write is the maximum of C_THZCE_PS_MEM and C_THZOE_PS_MEM.8. Chip enable high to data bus high impedance, C_THZCE_PS_MEM, is equivalent to tHZCE for asynchronous SRAM and tEHQZ for

Flash in the respective memory device data sheets.9. Output enable high to data bus high impedance, C_THZOE_PS_MEM, is equivalent to tHZOE for asynchronous SRAM and tGHQZ for

Flash in the respective memory device data sheets.10. Write enable low time is the maximum of C_TWC_PS_MEM and C_TWP_PS_MEM.11. Write cycle time, C_TWC_PS_MEM, is equivalent to tWC for asynchronous SRAM and tCW for Flash in the respective memory device

data sheets.12. Write cycle minimum pulse width, C_TWP_PS_MEM is equivalent to tWP for asynchronous SRAM and tPWE for Flash in the

respective memory device data sheets.13. Write enable high to data bus low impedance, C_TLZWE_PS_MEM, is equivalent to tLZWE for asynchronous SRAM and tWHGL for

Flash in the respective memory device data sheets.14. C_TLZWE_PS_MEM is the parameter set to meet write recovery to read time requirements.15. A value must be set for this parameter if the memory type in this bank is asynchronous. Refer to the memory device data sheet for the

correct value.16. This parameter is automatically calculated when using CoreGen, otherwise the user must set this parameter to the maximum value

of the C_MEMx_WIDTH generics.17. No default value will be specified for C_MEMx_BASEADDR and C_MEMx_HIGHADDR to insure that the actual value is set, i.e. if the

value is not set, a compiler error will be generated. The range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must be a power of 2.

18. Each channel can be configured to support a transfer protocol. Only the Xilinx CacheLink (XCL) protocol is supported at this time.19. If the channel is connected to a master which can consume data as soon as it is available (i.e., instruction side interfaces), set the

depth of the read data buffer to zero for that channel to save resources and latency.20. This design can accommodate up to 4 channels. The generics associated with the channels configured with a XCL protocol are

designated with a C_XCLx prefix where x = 0 to 3. If C_MCHx_PROTOCOL = XCL, then the generics with a C_XCLx prefix are used. If C_MCHx_PROTOCOL not equal to XCL, then the generics with a C_XCLx prefix are unused.

21. If an XCL channel is connected to a master that will only perform read transfers, then the entry in C_XCLx_WRITEXFER should be set to 0 indicating that no write transfers will be performed.

22. The timeout counter is not available in this release. The only allowed value for C_INCLUDE_TIMEOUT_CNTR is 0.

Allowable Parameter CombinationsNote that it is assumed all the external memory devices are accessible through MCH interface. They are also accessible through the OPB interface, if the design has been parameterized to include the OPB interface.

The OPB slave interface is only included in the design if C_INCLUDE_OPB_IPIF is set to 1. When C_INCLUDE_OPB_IPIF = 0, then the C_INCLUDE_OPB_BURST_SUPPORT is unused.

If C_SYNCH_MEMORY = 1, then C_SYNCH_PIPEDELAY specifies the pipeline delay of that synchronous memory type. All other timing parameters for that memory bank can remain at the default value of 0. If C_SYNCH_MEMORY = 0, C_SYNCH_PIPEDELAY is unused. All other timing parameters for that memory bank must be set to the value specified in the memory device data sheet.

C_INCLUDE_NEGEDGE_IOREGS provides no benefit when interfacing to asynchronous memories. Therefore, if there are no synchronous memories in the system, this parameter should be set to 0.

Optimal MCH Parameter SettingsThe only channel transfer protocol supported at this time is the Xilinx Cachelink (XCL) interface.

If an XCL channel is connected to a master that will only perform read transactions, then C_XCLx_WRITEXFER should be set to 0 indicating that no write transfers will be performed. This will reduce the channel logic to only contain logic for read transactions.

If an XCL channel is connected to a master that can consume data as soon as it is available, then C_MCHx_RDDATABUF_DEPTH for that channel can be set to 0. This will eliminate the read data buffer and eliminate the latency that would normally exist while reading data from this buffer. If the master cannot consume data as soon as it is available then, C_MCHx_RDDATABUF_DEPTH for that channel should be set to accommodate any latency the master has while reading data from the read data buffer.

Optimal performance will be achieved when the buffer depth of the access buffer is set greater than or equal to the line size of the channel (C_MCHx_ACCESSBUF_DEPTH ≥ C_XCLx_LINESIZE).

Discontinued IP




MCH OPB EMC I/O SignalsTable 2 provides a summary of all MCH OPB EMC input/output signals.

Table 2: MCH OPB EMC I/O Signals

Port Signal Name Interface I/O Initial State Description

System Signals

P1 MCH_OPB_CLK System I - MCH/OPB clock

P2 MCH_OPB_RST System I - MCH/OPB reset

External Memory Signals

P3MEM_DQ_I[0:C_MAX_MEM_WIDTH - 1]

External memory

I-

Memory input data bus

P4MEM_DQ_O[0:C_MAX_MEM_WIDTH - 1]

External memory

O0

Memory output data bus

P5MEM_DQ_T[0:C_MAX_MEM_WIDTH - 1]

External memory

O0 Memory output 3-state

signal

P6MEM_A[0:C_MCH_OPB_AWIDTH - 1]

External memory

O0

Memory address bus

P7MEM_RPN

External memory

O1

Memory reset/power down

P8MEM_CEN[0:C_NUM_BANKS_MEM - 1]

External memory

O1 Memory chip enables(1)

(active low)

P9MEM_OEN[0:C_NUM_BANKS_MEM - 1]

External memory

O1

Memory output enable

P10MEM_WEN

External memory

O1

Memory write enable

P11MEM_QWEN[0:(C_MAX_MEM_WIDTH/8) - 1]

External memory

O1 Memory qualified write

enables

P12MEM_BEN[0:(C_MAX_MEM_WIDTH/8) - 1]

External memory

O0

Memory byte enables

P13MEM_CE[0:C_NUM_BANKS_MEM - 1]

External memory

O0 Memory chip enables(1)

(active high)

P14MEM_ADV_LDN

External memory

O1 Memory advance burst

address/load new address

P15MEM_LBON

External memory

O1 Memory linear/interleaved

burst order

P16MEM_CKEN

External memory

O0

Memory clock enable

P17MEM_RNW

External memory

O1

Memory read not write

MCH Interface Signals

Discontinued IP




P18

MCH_Access_Control[0:C_NUM_CHANNELS - 1] MCH I

- Control signal to the access buffer of the MCH interface. This signal indicates the type of access to be performed (read or write) and the size of the access (byte, halfword or word)

P19 MCH_Access_Data[0:C_NUM_CHANNELS* C_MCH_OPB_DWIDTH - 1]

MCH I- Write data to the access

buffer of the MCH interface

P20MCH_Access_Write[0:C_NUM_CHANNELS - 1] MCH I

- Write signal to access buffer of the MCH interface

P21MCH_Access_Full[0:C_NUM_CHANNELS - 1] MCH O

0 Indicates that the access buffer of the MCH interface is full

P22

MCH_ReadData_Control[0:C_NUM_CHANNELS - 1]

MCH O

1 Control signal for the read data buffer of the MCH interface. These signals indicates if the data from the read data buffer is valid

P23MCH_ReadData_Data[0:C_MCH_OPB_DWIDTH* C_NUM_CHANNELS - 1]

MCH O0 Read data from the read

data buffer of the MCH interface

P24MCH_ReadData_Read[0:C_NUM_CHANNELS - 1] MCH I

- Read signal to the read data buffer of the MCH interface

P25MCH_ReadData_Exists[0:C_NUM_CHANNELS - 1] MCH O

0 Indicates that the read data buffer of the MCH interface is not empty

OPB Slave Signals(2)

P26 OPB_Select OPB I - OPB select

P27 OPB_RNW OPB I - OPB read not write

P28 OPB_ABus[0:C_MCH_OPB_AWIDTH-1] OPB I - OPB address bus

P29 OPB_DBus[0:C_MCH_OPB_DWIDTH-1] OPB I - OPB data bus

P30 OPB_BE[0:C_MCH_OPB_DWIDTH/8-1] OPB I - OPB byte enables

P31 OPB_seqAddr OPB I - OPB sequential address

P32Sl_xferAck OPB O 0

MCH OPB EMC transfer acknowledge

P33Sl_errAck OPB O 0

MCH OPB EMC error acknowledge

Table 2: MCH OPB EMC I/O Signals (Continued)


Discontinued IP




Notes: 1. Most asynchronous memory devices will only use MEM_CEN. Most synchronous memory devices will use both MEM_CEN and

MEM_CE. Refer to the device data sheet for correct connection of these signals.2. The signals in this section are unused if C_INCLUDE_OPB_IPIF = 0. The inputs are ignored and the outputs are driven to zero.

Parameter Port DependenciesThe dependencies between the MCH OPB EMC design parameters and I/O signals are shown in Table 3. When certain features are parameterized out of the design, the related logic will no longer be part of the design. The unused input signals and related output signals are set to a specified value.

P34Sl_toutSup OPB O 0

MCH OPB EMC timeout suppress

P35Sl_retry OPB O 0

MCH OPB EMC bus cycle retry

P36Sl_DBus[0:C_MCH_OPB_DWIDTH-1] OPB O 0

MCH OPB EMC output data bus

Table 3: Parameter Port Dependencies

Generic or Port Parameter Affects Depends Description

Design Parameters

G2C_NUM_BANKS_MEM P8, P9,

P13- Specifies the number of external

memory (SRAMs, Flash) banks

G4

C_INCLUDE_OPB_IPIF P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,

P36

- OPB input signals are unused and output signals are tied to 0 when

C_INCLUDE_OPB_IPIF = 0

G5C_INCLUDE_OPB_BURST_SUPPORT - G4 Unused when

C_INCLUDE_OPB_IPIF = 0

G6C_MCH_OPB_DWIDTH P19, P23,

P29, P30, P36

- Data bus width of MCH/OPB interface

G7C_MCH_OPB_AWIDTH P6, P28 - Address bus width of OPB interface

and MCH interface

G20C_MAX_MEM_WIDTH P3, P4,

P5, P11, P12

- Maximum data bus width of the external memory (SRAMs, Flash)

devices in all banks

G24

C_NUM_CHANNELS P18, P19, P20, P21, P22, P23, P24, P25

- The number of MCH interface channels

G25C_MCHx_PROTOCOL - G24 Unused when x is greater than

C_NUM_CHANNELS - 1

Table 2: MCH OPB EMC I/O Signals (Continued)


Discontinued IP




MCH OPB EMC Address Map DescriptionThe MCH OPB EMC currently supports only one bank of external memory. The address range of a bank of memory is restricted to be a power of 2. If the desired address range is represented by 2n, then the n least significant bits of the base address must be 0. For example, a memory bank with an addressable range of 16M (224) bytes could have a base address of 0xFF000000 and a high address of 0xFFFFFFFF.

A memory bank with an addressable range of 64K (216) bytes could have a base address of 0xABCD0000 and a high address of 0xABCDFFFF. The MCH OPB EMC core transactions must fall between the Bank 0 base address C_MEM0_BASEADDR and high address C_MEM0_HIGHADDR. The addresses for memory bank is shown in Table 4.

Table 4: MCH OPB EMC Memory Bank

Memory Base Address High Address Access

Bank 0 C_MEM0_BASEADDR C_MEM0_HIGHADDR Read/Write

G26C_MCHx_ACCESSBUF_DEPTH - G24 Unused when x is greater than

C_NUM_CHANNELS - 1

G27C_MCHx_RDDATABUF_DEPTH - G24 Unused when x is greater than

C_NUM_CHANNELS - 1

G28C_XCLx_LINESIZE - G24 Unused when x is greater than

C_NUM_CHANNELS - 1

G29C_XCLx_WRITEXFER - G24 Unused when x is greater than

C_NUM_CHANNELS - 1

I/O Signals

P3 MEM_DQ_I[0:C_MAX_MEM_WIDTH - 1]- G20 External memory (SRAMs, Flash)

input data bus

P4 MEM_DQ_O[0:C_MAX_MEM_WIDTH - 1]- G20 External memory (SRAMs, Flash)

output data bus

P5 MEM_DQ_T[0:C_MAX_MEM_WIDTH - 1]- G20 External memory (SRAMs, Flash)

output 3-state signal

P6 MEM_A[0:C_MCH_OPB_AWIDTH - 1]- G7 External memory (SRAMs, Flash)

address bus

P8 MEM_CEN[0:C_NUM_BANKS_MEM - 1]- G2 External memory (SRAMs, Flash)

active low chip enables

P9 MEM_OEN[0:C_NUM_BANKS_MEM - 1]- G2 External memory (SRAMs, Flash)

active low output enables

P11 MEM_QWEN[0:C_MAX_MEM_WIDTH/8 - 1]- G20 External memory (SRAMs, Flash)

qualified write enables

P12 MEM_BEN[0:C_MAX_MEM_WIDTH/8 - 1]- G20 External memory (SRAMs, Flash)

byte enables

P13MEM_CE[0:C_NUM_BANKS_MEM - 1] - G2 External memory (SRAMs, Flash)

active high chip enables

Table 3: Parameter Port Dependencies

Generic or Port Parameter Affects Depends Description

Discontinued IP




Memory Data Types and OrganizationMemory can be accessed through the MCH OPB EMC as one of three types: byte (8 bits), halfword (2 bytes) or word (4 bytes). Data to and from the MCH and OPB is organized as big-endian. The bit and byte labeling for the big-endian data types is shown below in Figure 1.

Figure 1: Memory Data Types

n n+1 n+2 n+3

0 1 2 3

MSByte LSByte

0 31

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n n+1

0 1

MSByte LSByte

0 15

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n

0

MSByte

0 7

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Byte

Halfword

Word

Discontinued IP




MCH OPB EMC Block diagram

MCH OPB EMC Top level block diagramFigure 2 illustrates the top level block diagram of MCH OPB EMC.

MCH 0

MCH 1

MCH 2

MCH 3

MCH

OPB

IPIF

IPIC

Interface

OP

B

Counters

Select Parameters

Mem State Machine

IO

Registers

Mem Steer

MEM_DQ_I

MEM_DQ_O

MEM_DQ_T

MEM_A

MEM_RPN

MEM_CEN

MEM_OEN

MEM_WEN

MEM_QWEN

MEM_BEN

MEM_CE

MEM_ADV_LDN

MEM_LBON

MEM_CKEN

MEM_RNW

Address Counter Mux

EMC CORE

MCH OPB EMC

Figure 2: MCH OPB EMC Top Level Block Diagram

The MCH OPB EMC consists of the MCH OPB IPIF module, Select Parameters module, Mem State Machine module, Mem Steer module, Address Counter Mux module, Counters module, I/O Registers module and IPIC Interface module.

MCH OPB IPIFThe MCH OPB IPIF provides an interface to the MCH interface and optional interface to the OPB. The MCH OPB IPIF consists of an optional OPB slave interface, a parameterizable number of channel interfaces and arbitration logic to select between the MCH interfaces and the OPB interface. The appropriate multiplexors/de-multiplexors connect the selected channel or OPB transaction to the EMC core.

Discontinued IP




Select ParametersThe Select Parameters module provides necessary pipeline delays or timing delays based on the type of memory. It also indicates the type of memory connected to the core.

Mem State MachineThe state diagram of Mem State Machine is shown in Figure 3.

Figure 3: Memory State Machine State Diagram

IDLE

READ WRITE

WAIT_RDDATA_ACK

DASEERT_WEN

WAIT_WRITE_ACK

Bus2IP_RNW * Bus2Mem_CS * Bus2IP_RdReq * Tlz_end

Bus2IP_RNW * Bus2Mem_CS * Bus2IP_WrReq * Thz_end

Trd_end * Cycle_End * ( Bus2IP_Rdreq +

Bus2Ip_Burst )

Read_complete

Twr_end * Sync_mem

Cycle_End + (Cycle_End * Bus2Ip_WrReq * Burst_continue)

Twr_end * Sync_mem * Cycle_End * ( Bus2Ip_WrReq + Burst_continue )

Cycle_End * ( Bus2Ip_WrReq +

Burst_continue )

The Mem State Machine controls read and write transactions for the memory. It handles both single and burst conditions and provides necessary control signals to the Counters, Mem Steer and Address Counter Mux modules.

Mem SteerThe Mem Steer module contains the logic to provide the steering of read data, write data and memory control signals. It generates the acknowledge signals for the MCH OPB IPIF. This module contains data width matching logic when the data bus width of the memory is less than the MCH/OPB data bus width.

Address Counter MuxThe Address Counter Mux module provides the address count to the Mem Steer module and provides the address suffix to generate the memory address. It also handles the cycle end logic which is directed to the Mem State Machine.

CountersThis module contains the counters for counting the read cycle time and write cycle time.

I/O RegistersRegisters are used on all signals to and from the memory bank to provide consistent timing on the memory interface. The I/O Registers module present in the design depends upon the setting of the C_INCLUDE_NEGEDGE_IOREGS. All signals output to the memory bank are registered on the rising edge of the system clock. If C_INCLUDE_NEGEDGE_IOREGS = 1,

Discontinued IP




the signals are registered again on the falling edge of the system clock, as shown in Figure 4, and can be used at lower clock frequency to provide adequate setup and hold times to synchronous memories.

Figure 4: MCH OPB EMC Output Registers When C_INCLUDE_NEGEDGE_IOREGS = 1

Clk

D Q

Clk

D Q

Internal

Clk Clk

Memory Data/Control

Memory Data/Control

IPIC InterfaceThe IPIC Interface module connects the EMC core to the MCH OPB IPIF.

Connecting to Memory

Clocking Synchronous MemoryThe MCH OPB EMC does not provide a clock output to any synchronous memory. The MCH/OPB clock should be routed through an output buffer to provide the clock to the synchronous memory.

To synchronize the synchronous memory clock to the internal FPGA clock, the FPGA system design should include a DCM external to the MCH OPB EMC core that uses the synchronous memory clock input as the feedback clock as shown in Figure 5. This means that the synchronous clock output from the FPGA must be routed back to the FPGA on a clock pin with a connection to a DCM clock feedback input.

Discontinued IP




Figure 5: Synchronous Memory Bank Clocked By FPGA Output With Feedback

External Clk

Synchronous Memory Bank

BUFG OBUF

FPGASyncmem_Clk

CLKIN

CLKFB

DCM

Sync

mem

_Clk

_fb

CLK

MCH OPB EMCMC

H_O

PB

_Clk

CLK0

If the synchronous memory is clocked by the same external clock as the FPGA, or if the clock feedback is not available, the DCM shown in Figure 6 should be included in the FPGA external to the MCH OPB EMC core.

Note: If DLLs are used, the designer must reference XAPP132 v2.4, "Using the Virtex Delay-Locked Loop" for the correct DLL implementation.

Discontinued IP




Figure 6: Synchronous Memory Bank Clocked By External Clock

CLKIN

CLKFB

CLK0

DCM

Synchronous Memory BankCLK

BUFG

FPGA

External Clk

MC

H_O

PB_C

lk

MCH OPB EMC

Address Bus, Data Bus and Control Signal ConnectionsThe three primary considerations for connecting the controller to memory devices are the width of the MCH/OPB data bus, the width of the memory subsystem and the number of memory devices used.

The width of the memory subsystem is simply the maximum width of data that can be read from or written to the memory subsystem. The memory width must be less than or equal to the MCH/OPB data bus width.

The data and address signals at the memory controller are labeled with big-endian bit labeling (for example: D(0:31), D(0) is the MSB), whereas most memory devices are either endian agnostic (they can be connected either way) or little-endian D(31:0) with D(31) as the MSB.

Care must be taken when connecting the chip enable signals. Most asynchronous memory devices will only use MEM_CEN, while most synchronous memory devices will use both MEM_CEN and MEM_CE. MEM_CEN is a function of the address decode while MEM_CE is a function of the state machine logic.

Caution must be exercised with the connections to the external memory devices to avoid incorrect data and address connections. The following tables show the correct mapping of memory controller pins to memory device pins.

Table 5 shows variables used in defining memory subsystem and Table 6 shows interconnection of MCH OPB EMC signals to memory interface signals.

Table 5: Variables Used In Defining Memory Subsystem

Variable Allowed Range Definition

BN 0 to 3 Memory bank number

DN 0 to 31 Memory device number within a bank. The memory device attached to the most significant bit in the memory subsystem is 0; device numbers increase toward the least significant bit.

MW 8 to 32 Width in bits of memory subsystem

DW 1 to 32 Width in bits of data bus for memory device

MAW 1 to 32 Width in bits of address bus for memory device

Discontinued IP




Notes: 1. The value of X depends on variables MW, AU and DW.

Table 6: MCH OPB EMC To Memory Interconnect

Description MCH OPB EMC Signals (MSB:LSB) Memory Device Signals (MSB:LSB)

Data bus MEM_DQ(DN*DW:((DN+1)*DW)-1) D(DW-1:0)

Address bus MEM_A(HAW-MAW-AS:HAW-AS-1) A(MAW-1:0)

Chip enable (active low) MEM_CEN(BN) CEN

Output enable (active low) MEM_OEN OEN

Write enable (active low) MEM_WEN WEN (for devices that have byte enables)

Qualified write enable (active low)

MEM_QWEN(DN*DW/8)WEN (for devices that do not have byte enables)

Byte enable (active low)MEM_BEN((DN*DW/8): (((DN+1)*DW/8)-1))

BEN(DW/8-1:0)

Example Memory Connections

Connecting to SRAM

Example 1: Connection to 32-bit memory using 2 IDT71V416S SRAM parts.

Table 7

Table 7: Variables For Simple SRAM Example

Variable Value Definition

BN 0 Memory bank number


MW 32 Width in bits of memory subsystem

DW 16 Width in bits of data bus for memory device

MAW 18 Width in bits of address bus for memory device

AU 16 Width in bits of smallest addressable data word on the memory device

AS 2 Address shift for address bus = log2((MW*AU/DW)/8)

HAW 32 Width in bits of host address bus (e.g. MCH/OPB)

shows variables for simple SRAM example.

AU 1 to 32 Width in bits of smallest addressable data word on the memory device

AS X(1) Address shift for address bus = log2((MW*AU/DW)/8)

HAW 1 to 32 Width in bits of MCH/OPB address bus

Table 5: Variables Used In Defining Memory Subsystem (Continued)

Variable Allowed Range Definition

Discontinued IP




Table 8: Connection To 32-bit Memory Using 2 IDT71V416S Parts

DN Description MCH OPB EMC Signals

(MSB:LSB)Memory Device Signals

(MSB:LSB)

0 Data bus MEM_DQ(0:15) I/O(15:0)

Address bus MEM_A(12:29) A(17:0)

Chip enable (active low) MEM_CEN(0) CS

Output enable (active low) MEM_OEN OE

Write enable (active low) MEM_WEN WE

Byte enable (active low) MEM_BEN(0:1) BHE:BLE

1 Data bus MEM_DQ(16:31) I/O(15:0)


Chip enable (active low) MEM_CEN(0) CS

Output enable (active low) MEM_OEN OE

Write enable (active low) MEM_WEN WE

Byte enable (active low) MEM_BEN(2:3) BHE:BLE

Table 8 shows connection to 32-bit memory using 2 IDT71V416S (256K X 16-Bit) parts.

Connecting to Intel StrataFlashStrataFlash parts contain an identifier register, a status register and a command interface, so the bit label ordering for these parts is critical in order to function properly. Table 9 shows example of how to connect the big-endian MCH OPB EMC bus to the little-endian StrataFlash parts.

The proper connection ordering is also indicated in a more general form in Table 6. StrataFlash parts have a x8 mode and a x16 mode, selectable with the BYTE# input pin. To calculate the proper address shift, the minimum addressable word is 8 bits for both x8 and x16 mode, since A0 always selects a byte.

Example 2: Connection to 32-bit memory using 2 StrataFlash parts in x16 mode.

Supports byte read, but no byte write; smallest data type that can be written is 16-bit data.

Table 9: Variables For StrataFlash (x16 mode) Example










Table 9 shows variables for StrataFlash (x16 mode) example.

Discontinued IP




Table 10: Connection To 32-bit Memory Using 2 StrataFlash Parts

DN Description MCH OPB EMC Signals (MSB:LSB) StrataFlash Signals (MSB:LSB)

0 Data bus MEM_DQ(0:15) DQ(15:0)


Chip enable (active low) GND,GND,MEM_CEN(0) CE(2:0)

Output enable (active low) MEM_OEN OE#

Write enable (active low) MEM_QWEN(0) WE#

Reset/Power down (active low) MEM_RPN RP#

Byte mode select (active low) N/A - tie to GND BYTE#

Program enable (active high) N/A - tie to VCC VPEN

1 Data bus MEM_DQ(16:31) DQ(15:0)


Chip enable (active low) GND, GND, MEM_CEN(0) CE(2:0)



Reset/Power down (active low) MEM_RPN RP#



Table 10 shows connection to 32-bit memory using 2 StrataFlash parts.

Example 3: Connection to 32-bit memory using 4 StrataFlash parts in x8 mode.

Supports byte reads and writes.

Table 11: Variables For StrataFlash (x8 mode) Example










Table 11 shows variables for StrataFlash (x8 mode) example.

Discontinued IP




Table 12 shows connection to 32-bit memory using 4 StrataFlash parts.

Table 12: Connection To 32-bit Memory Using 4 StrataFlash Parts


0 Data bus MEM_DQ(0:7) DQ(7:0)(1)





Reset/Power down (active low)

MEM_RPN RP#





Chip enable (active low) GND,GND, MEM_CEN(0) CE(2:0)




MEM_RPN RP#









MEM_RPN RP#



Discontinued IP










MEM_RPN RP#



Notes: 1. In x8 configuration, DQ(15:8) are not used and should be treated according to manufacturer’s data sheet.

Table 12: Connection To 32-bit Memory Using 4 StrataFlash Parts (Continued)


Discontinued IP




MCH OPB EMC Timing Diagrams

XCL Protocol Cacheline Write Timing Diagrams

Figure 7 shows an XCL protocol channel performing a cacheline write on 32-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Data[0:31]

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Control

MCH_ReadData_Data[0:31]

MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A0 D0 D1 D2 D3

NOPNOP WRITE NOP WRITE NOP WRITE NOP WRITE NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

FF 0 F

T1 = (max of C_TWC_PS_MEM_x or C_TWP_PS_MEM_x) / C_MCH_OPB_CLK_PERIOD_PSHere T1 = 2 cycles

T1

Figure 7: XCL Cacheline Write Operation With 32-Bit Asynchronous SRAM

Figure 8 shows an XCL protocol channel performing a cacheline write on 32-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14

A0 D0 D1 D2 D3

NOPNOP WRITE NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

FF 0 F

Figure 8: XCL Cacheline Write Operation With 32-Bit Synchronous ZBT SRAM

Discontinued IP




XCL Protocol Cacheline Read Timing Diagrams

Figure 9 shows an XCL protocol channel performing a cacheline read on 32-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A0

D0 D1 D2 D3

NOPNOP READ NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

T1 = [(Max of C_TAVDV_PS_MEM_x or C_TCEDV_PS_MEM_x) / C_MCH_OPB_CLK_PERIOD_PS ] + 1Here T1 = 2 cycles

T1

Figure 9: XCL Cacheline Read Operation With 32-Bit Asynchronous SRAM

Figure 10 shows an XCL protocol channel performing a cacheline read on 32-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A0

D0 D1 D2 D3

NOPNOP READ NOP

A0 A0+1A0+2A0+3

D0 D1 D2 D3

Figure 10: XCL Cacheline Read Operation With 32-Bit Synchronous ZBT SRAM

Discontinued IP




XCL Protocol Cacheline Write and Read Timing Diagrams

Figure 11 shows an XCL protocol channel performing a cacheline write followed by cacheline read operation on 32-bit Asynchronous SRAM.

CYCLES

Clock

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 20 2122 2324 25 2627 2829 30 3132 3334 3536

A0 D0 D1 D2 D3 A0

D0 D1 D2 D3

NOPNOP WRITE NOPWRITE NOPWRITENOPWRITE NOP READ NOP

A0 A0+1 A0+2 A0+3 A0 A0+1 A0+2 A0+3

D0 D1 D2 D3 D0 D1 D2 D3

FF 0 F

T1 = (max of C_TWC_PS_MEM_x or C_TWP_PS_MEM_x) / C_MCH_OPB_CLK_PERIOD_PST2 = (Max of C_TAVDV_PS_MEM_x or C_TCEDV_PS_MEM_x / C_MCH_OPB_CLK_PERIOD_PS) + 1Here T1 and T2 = 2 cycles

T1 T2

Figure 11: XCL Cacheline Write and Read Operation With 32-Bit Asynchronous SRAM

Figure 12 shows an XCL protocol channel performing a cacheline write followed by cacheline read operation on 32-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2728

A0 D0 D1 D2 D3 A0

D0 D1 D2 D3

NOPNOP WRITE NOP READ NOP

A0 A0+1A0+2 A0+3 A0 A0+1 A0+2 A0+3

D0 D1 D2 D3 D0 D1 D2 D3

FF 0 F

Figure 12: XCL Cacheline Write and Read Operation With 32-Bit Synchronous ZBT SRAM

Discontinued IP




XCL Protocol Single Write Timing Diagrams

Figure 13 shows an XCL protocol channel performing a single write operation on 8-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:7]

Mem_BEN

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A0 D


A0 A0+1 A0+2 A0+3

D[0:7] D[8:15] D[16:23] D[24:31]

FF 0 F


T1

Figure 13: XCL Single Write Operation With 8-Bit Asynchronous SRAM

Figure 14 shows an XCL protocol channel performing a single write operation on 8-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:7]

Mem_BEN

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14

A0 D

NOPNOP WRITE NOP

A0 A0+1 A0+2 A0+3

D[0:7]D[8:15] D[16:23] D[24:31]

FF 0 F

Figure 14: XCL Single Write Operation With 8-Bit Synchronous ZBT SRAM

Discontinued IP




XCL Protocol Single Read Timing Diagrams

Figure 15 shows an XCL protocol channel performing a single read operation on 8-bit Asynchronous SRAM.

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:7]

A0

D0D1D2D3

NOPNOP READ NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3


T1

Figure 15: XCL Single Read Operation With 8-Bit Asynchronous SRAM

Figure 16 shows an XCL protocol channel performing a single read operation on 8-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control


MCH_Access_Full

MCH_ReadData_Read



MCH_ReadData_Exists

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:7]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A0

D0D1D2D3

NOPNOP READ NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

Figure 16: XCL Single Read Operation With 8-Bit Synchronous ZBT SRAM

Discontinued IP




OPB Burst Write Timing Diagrams

Figure 17 shows an OPB burst write operation on 32-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

A0 A1 A2 A3

D0 D1 D2 D3

F


A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

FF 0 F


T1

Figure 17: OPB Burst Write Operation With 32-Bit Asynchronous SRAM

Figure 18 shows an OPB burst write operation on 32-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

Mem_BEN[0:3]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A0 A1 A2 A3

D0 D1 D2 D3

F

NOPNOP WRITE NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

FF 0 F

Figure 18: OPB Burst Write Operation With 32-Bit Synchronous ZBT SRAM

Discontinued IP




OPB Burst Read Timing Diagrams

Figure 19 shows an OPB burst read operation on 32-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

A0 A1 A2 A3

D0 D1 D2 D3

F

NOPNOP READ NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3


T1

Figure 19: OPB Burst Read Operation With 32-Bit Asynchronous SRAM

Figure 20 shows an OPB burst read operation on 32-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:31]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A0 A1 A2 A3

D0 D1 D2 D3

F

NOPNOP READ NOP

A0 A0+1 A0+2 A0+3

D0 D1 D2 D3

Figure 20: OPB Burst Read Operation With 32-Bit Synchronous ZBT SRAM

Discontinued IP




OPB Single Write Timing Diagrams

Figure 21 shows an OPB single write operation on 16-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:15]

Mem_BEN[0:1]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

A0

D

F

NOPNOP WRITE NOP WRITE NOP

A0 A0+1

D[0:15] D[16:31]

FF 0 F


T1

Figure 21: OPB Single Write Operation With 16-Bit Asynchronous SRAM

Figure 22 shows an OPB single write operation on 16-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:15]

Mem_BEN[0:1]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A0

D

F

NOPNOP WRITE NOP

A0 A0+1

D[0:15] D[16:31]

FF 0 F

Figure 22: OPB Single Write Operation With 16-Bit Synchronous ZBT SRAM

Discontinued IP




OPB Single Read Timing Diagrams

Figure 23 shows an OPB single read operation on 16-bit Asynchronous SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:15]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A0

D0D1

F

NOPNOP READ NOP

A0 A0+1

D0 D1


T1

Figure 23: OPB Single Read With 16-Bit Asynchronous SRAM

Figure 24 shows an OPB single read operation on 16-bit Synchronous ZBT SRAM.

CYCLES

MCH_OPB_CLK

OPB_Select

OPB_RNW

OPB_ABus[0:31]

OPB_DBus[0:31]

OPB_BE[0:3]

OPB_seqAddr

Sln_xferAck

Command

Mem_A[0:31]

Mem_CEN

Mem_OEN

Mem_WEN

Mem_DQ[0:15]

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A0

D0D1

F

NOPNOP READ NOP

A0 A0+1

D0 D1

Figure 24: OPB Single Read With 16-Bit Synchronous ZBT SRAM

Discontinued IP




Design Constraints

Timing ConstraintsA timing constraint should be placed on the system clock, setting the frequency to meet the bus timing requirements. An example is shown in Figure 25.

Figure 25: MCH OPB EMC Timing Constraints

NET "MCH_OPB_Clk" TNM_NET = "MCH_OPB_Clk";

TIMESPEC "TS_MCH_OPB_Clk" = PERIOD "MCH_OPB_Clk" 10 ns HIGH 50 %;

Pin ConstraintsIf external pullups/pulldowns are not available on the MEM_DQ signals, then these pins should be specified to use pullup or pulldown resistors. An example is shown in Figure 26.

Figure 26: MCH OPB EMC Pin Constraints

NET "MEM_DQ" PULLDOWN;


. . . . .


Discontinued IP




Design Implementation

Target TechnologyThe intended target technology is Spartan-3, Virtex-II Pro and Virtex-4 family FPGAs.

Device Utilization and Performance BenchmarksThe MCH OPB EMC is a module that will be used with other designs in the FPGA. Thus, the utilization and timing numbers reported in this section are estimates and will vary.

The MCH OPB EMC benchmarks are shown in Table 13 for Virtex-II Pro XC2VP30-6 FPGA.

Table 13: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Virtex-II Pro)

Sr. No.

Parameter Values Device Resources

FmaxC_N

UM

_CH

AN

NE

LS

C_I

NC

LU

DE

_OP

B_I

PIF

C_I

NC

LU

DE

_OP

B_B

UR

ST

_SU

PP

OR

T

C_M

AX

_ME

M_W

IDT

H

C_I

NC

LU

DE

_DA

TAW

IDT

H_M

AT

CH

ING

_x

C_S

YN

CH

_ME

M_x

Slices

Slice Flip- Flops

4-input LUTs

1 1 0 0 8 0 0 240 259 267 101.7812 2 0 0 8 0 1 397 359 548 100.9183 3 0 0 8 1 0 757 591 1001 101.5024 4 0 0 8 1 1 922 701 1233 100.885 1 0 1 8 0 0 240 259 267 101.7816 2 0 1 8 0 1 397 359 548 100.9187 3 0 1 8 1 0 757 591 1001 101.5028 4 0 1 8 1 1 922 701 1233 100.8889 1 1 0 8 0 0 393 439 461 100.817

10 2 1 0 8 0 1 596 521 709 100.41211 3 1 0 8 1 0 922 807 1122 100.42212 4 1 0 8 1 1 1316 915 1377 100.0213 1 1 1 8 0 0 527 520 656 100.3214 2 1 1 8 0 1 850 603 887 100.66415 3 1 1 8 1 0 106 889 1335 100.77616 4 1 1 8 1 1 1424 1000 1609 100.41217 1 0 0 16 0 0 256 293 275 101.47118 2 0 0 16 0 1 430 409 572 100.88819 3 0 0 16 1 0 757 591 1001 10020 4 0 0 16 1 1 922 701 1233 100.19

Discontinued IP




21 1 0 1 16 0 0 256 293 275 101.47122 2 0 1 16 0 1 430 409 572 100.88823 3 0 1 16 1 0 757 591 1001 10024 4 0 1 16 1 1 922 701 1123 100.1925 1 1 0 16 0 0 422 490 495 100.87826 2 1 0 16 0 1 651 588 760 100.27127 3 1 0 16 1 0 916 807 1122 100.35128 4 1 0 16 1 1 1084 915 1377 100.42229 1 1 1 16 0 0 562 572 699 102.40730 2 1 1 16 0 1 970 671 947 100.65431 3 1 1 16 1 0 1238 889 1335 100.1232 4 1 1 16 1 1 1460 1000 1609 100.0933 1 0 0 32 0 0 289 361 291 101.67834 2 0 0 32 0 1 499 509 620 103.11435 3 0 0 32 1 0 757 591 1001 100.91836 4 0 0 32 1 1 922 701 1233 100.0437 1 0 1 32 0 0 289 361 291 101.67838 2 0 1 32 0 1 499 509 620 103.11439 3 0 1 32 1 0 757 591 100 100.91840 4 0 1 32 1 1 922 701 1233 100.0441 1 1 0 32 0 0 484 592 539 100.27142 2 1 0 32 0 1 761 722 838 101.4343 3 1 0 32 1 0 935 807 1122 100.0244 4 1 0 32 1 1 1086 915 1377 100.2245 1 1 1 32 0 0 632 676 760 101.36846 2 1 1 32 0 1 1105 807 1042 100.9947 3 1 1 32 1 0 1258 889 1343 100.26148 4 1 1 32 1 1 1434 1000 1609 100

Table 13: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Virtex-II Pro) (Continued)

Discontinued IP




The MCH OPB EMC benchmarks are shown in Table 14 for Virtex-4 XC4VLX40-11 FPGA.

Table 14: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Virtex-4)

Sr. No.


FmaxC_N

UM

_CH

AN

NE

LS

C_I

NC

LU

DE

_OP

B_I

PIF

C_I

NC

LU

DE

_OP

B_B

UR

ST

_SU

PP

OR

T

C_M

AX

_ME

M_W

IDT

H

C_I

NC

LU

DE

_DA

TAW

IDT

H_M

AT

CH

ING

_x

C_S

YN

CH

_ME

M_x

Slices

Slice Flip- Flops

4-input LUTs

1 1 0 0 8 0 0 238 258 265 163.5592 2 0 0 8 0 1 423 362 592 124.9223 3 0 0 8 1 0 778 593 1042 107.8984 4 0 0 8 1 1 948 701 1294 106.0115 1 0 1 8 0 0 238 258 265 163.5596 2 0 1 8 0 1 423 362 592 124.922 7 3 0 1 8 1 0 778 593 1042 107.8988 4 0 1 8 1 1 948 701 129 106.0119 1 1 0 8 0 0 402 441 484 137.684

10 2 1 0 8 0 1 615 521 767 108.8611 3 1 0 8 1 0 948 805 1186 107.37712 4 1 0 8 1 1 1127 921 147 106.168 13 1 1 1 8 0 0 533 518 675 117.398 14 2 1 1 8 0 1 745 602 980 103.584 15 3 1 1 8 1 0 1098 890 1422 101.399 16 4 1 1 8 1 1 1269 1001 1724 102.041 17 1 0 0 16 0 0 254 292 273 162.20618 2 0 0 16 0 1 455 412 616 124.61119 3 0 0 16 1 0 778 593 1042 107.747 20 4 0 0 16 1 1 948 701 1294 107.285 21 1 0 1 16 0 0 254 292 273 162.206 22 2 0 1 16 0 1 455 412 616 124.61123 3 0 1 16 1 0 778 593 1042 107.747 24 4 0 1 16 1 1 948 701 1294 107.285 25 1 1 0 16 0 0 436 492 526 118.008 26 2 1 0 16 0 1 670 588 818 106.815 27 3 1 0 16 1 0 948 805 1186 104.603

Discontinued IP




28 4 1 0 16 1 1 1127 921 1477 101.15329 1 1 1 16 0 0 571 570 717 117.93830 2 1 1 16 0 1 808 670 1040 108.956 31 3 1 1 16 1 0 1097 890 1422 102.40732 4 1 1 16 1 1 1269 1001 1724 102.333 33 1 0 0 32 0 0 288 360 289 151.722 34 2 0 0 32 0 1 522 512 664 131.544 35 3 0 0 32 1 0 778 593 1042 112.18336 4 0 0 32 1 1 951 701 1294 101.34837 1 0 1 32 0 0 288 360 289 151.722 38 2 0 1 32 0 1 522 512 664 131.54439 3 0 1 32 1 0 778 593 1042 112.18340 4 0 1 32 1 1 951 701 1129 101.348 41 1 1 0 32 0 0 498 594 586 131.527 42 2 1 0 32 0 1 780 722 896 113.13543 3 1 0 32 1 0 948 805 1186 101.01 44 4 1 0 32 1 1 1127 921 1477 101.4245 1 1 1 32 0 0 639 674 778 113.084 46 2 1 1 32 0 1 930 806 1135 103.55247 3 1 1 32 1 0 1097 890 1422 101.97848 4 1 1 32 1 1 1266 1001 1724 101.317

Table 14: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Virtex-4) (Continued)

Discontinued IP




The MCH OPB EMC benchmarks are shown in Table 15 for Spartan-3 XC3S2000-5 FPGA.

Table 15: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Spartan-3)

Sr. No.


FmaxC_N

UM

_CH

AN

NE

LS

C_I

NC

LU

DE

_OP

B_I

PIF

C_I

NC

LU

DE

_OP

B_B

UR

ST

_SU

PP

OR

T

C_M

AX

_ME

M_W

IDT

H

C_I

NC

LU

DE

_DA

TAW

IDT

H_M

AT

CH

ING

_x

C_S

YN

CH

_ME

M_x

Slices

Slice Flip- Flops

4-input LUTs

1 1 0 0 8 0 0 292 258 369 98.0202 2 0 0 8 0 1 412 363 582 100.043 3 0 0 8 1 0 922 591 1044 72.2754 4 0 0 8 1 1 1097 700 1269 72.7755 1 0 1 8 0 0 239 258 269 101.3896 2 0 1 8 0 1 412 363 582 100.047 3 0 1 8 1 0 922 591 1044 72.2758 4 0 1 8 1 1 1097 700 1269 72.7759 1 1 0 8 0 0 399 438 484 102.40710 2 1 0 8 0 1 711 521 743 73.87711 3 1 0 8 1 0 1128 807 1168 72.1612 4 1 0 8 1 1 1376 915 1445 71.90113 1 1 1 8 0 0 633 519 668 73.93214 2 1 1 8 0 1 887 601 922 72.80115 3 1 1 8 1 0 1263 892 1393 71.96816 4 1 1 8 1 1 1508 1066 1655 71.99917 1 0 0 16 0 0 255 292 277 101.46118 2 0 0 16 0 1 448 413 606 101.49219 3 0 0 16 1 0 870 591 1044 71.83420 4 0 0 16 1 1 1094 700 1269 72.53221 1 0 1 16 0 0 255 292 277 101.46122 2 0 1 16 0 1 448 413 606 101.49223 3 0 1 16 1 0 870 591 1044 71.83424 4 0 1 16 1 1 1094 700 1269 72.53225 1 1 0 16 0 0 428 489 518 100.1126 2 1 0 16 0 1 804 588 794 71.96827 3 1 0 16 1 0 1160 807 1168 71.829

Discontinued IP




Reference DocumentsThe following documents contain reference information important to understand the MCH OPB EMC design:

1. MicroBlaze Processor Reference Guide (UG081)

2. MCH OPB IPIF Design Specification(DS 494)

3. OPB EMC Product specifications(DS 421)

4. OPB IPIF Design specification (v3_01_a)

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision Editor

3/16/06 1.0 Initial Xilinx release. vpk

28 4 1 0 16 1 1 1311 915 1445 72.19229 1 1 1 16 0 0 632 571 711 72.90230 2 1 1 16 0 1 929 669 982 72.20231 3 1 1 16 1 0 1294 892 1393 72.11932 4 1 1 16 1 1 1495 999 1653 71.4933 1 0 0 32 0 0 288 360 293 103.61634 2 0 0 32 0 1 514 513 654 101.28635 3 0 0 32 1 0 911 591 1044 72.14536 4 0 0 32 1 1 1116 700 1269 72.60637 1 0 1 32 0 0 288 360 293 103.61638 2 0 1 32 0 1 514 513 654 101.28639 3 0 1 32 1 0 911 591 1044 72.14540 4 0 1 32 1 1 1116 700 1269 72.60641 1 1 0 32 0 0 487 591 562 100.34142 2 1 0 32 0 1 992 722 872 74.5143 3 1 0 32 1 0 1133 807 1168 72.12444 4 1 0 32 1 1 1324 915 1445 71.5145 1 1 1 32 0 0 807 675 772 74.58246 2 1 1 32 0 1 1095 805 1077 72.29647 3 1 1 32 1 0 1252 892 1393 72.40148 4 1 1 32 1 1 1482 999 1653 71.613

Table 15: MCH OPB EMC FPGA Performance and Resource Utilization Benchmarks (Spartan-3) (Continued)

Discontinued IP



Multi-CHannel OPB External Memory Controller (MCH OPB EMC) (v1.00a)IntroductionFeaturesMCH OPB EMC Design ParametersAllowable Parameter CombinationsOptimal MCH Parameter SettingsMCH OPB EMC I/O Signals

Parameter Port DependenciesMCH OPB EMC Address Map DescriptionMemory Data Types and OrganizationMCH OPB EMC Block diagramMCH OPB EMC Top level block diagramMCH OPB IPIFSelect ParametersMem State MachineMem SteerAddress Counter MuxCountersI/O RegistersIPIC Interface

Connecting to MemoryClocking Synchronous MemoryAddress Bus, Data Bus and Control Signal ConnectionsExample Memory ConnectionsConnecting to SRAMExample 1: Connection to 32-bit memory using 2 IDT71V416S SRAM parts.

Connecting to Intel StrataFlashExample 2: Connection to 32-bit memory using 2 StrataFlash parts in x16 mode.Example 3: Connection to 32-bit memory using 4 StrataFlash parts in x8 mode.

MCH OPB EMC Timing DiagramsXCL Protocol Cacheline Write Timing DiagramsFigure 7 shows an XCL protocol channel performing a cacheline write on 32-bit Asynchronous SRAM.Figure 8 shows an XCL protocol channel performing a cacheline write on 32-bit Synchronous ZBT SRAM.

XCL Protocol Cacheline Read Timing DiagramsFigure 9 shows an XCL protocol channel performing a cacheline read on 32-bit Asynchronous SRAM.Figure 10 shows an XCL protocol channel performing a cacheline read on 32-bit Synchronous ZBT SRAM.

XCL Protocol Cacheline Write and Read Timing DiagramsFigure 11 shows an XCL protocol channel performing a cacheline write followed by cacheline read operation on 32-bit Asynchronous SRAM.Figure 12 shows an XCL protocol channel performing a cacheline write followed by cacheline read operation on 32-bit Synchronous ZBT SRAM.

XCL Protocol Single Write Timing DiagramsFigure 13 shows an XCL protocol channel performing a single write operation on 8-bit Asynchronous SRAM.Figure 14 shows an XCL protocol channel performing a single write operation on 8-bit Synchronous ZBT SRAM.

XCL Protocol Single Read Timing DiagramsFigure 15 shows an XCL protocol channel performing a single read operation on 8-bit Asynchronous SRAM.Figure 16 shows an XCL protocol channel performing a single read operation on 8-bit Synchronous ZBT SRAM.

OPB Burst Write Timing DiagramsFigure 17 shows an OPB burst write operation on 32-bit Asynchronous SRAM.Figure 18 shows an OPB burst write operation on 32-bit Synchronous ZBT SRAM.

OPB Burst Read Timing DiagramsFigure 19 shows an OPB burst read operation on 32-bit Asynchronous SRAM.Figure 20 shows an OPB burst read operation on 32-bit Synchronous ZBT SRAM.

OPB Single Write Timing DiagramsFigure 21 shows an OPB single write operation on 16-bit Asynchronous SRAM.Figure 22 shows an OPB single write operation on 16-bit Synchronous ZBT SRAM.

OPB Single Read Timing DiagramsFigure 23 shows an OPB single read operation on 16-bit Asynchronous SRAM.Figure 24 shows an OPB single read operation on 16-bit Synchronous ZBT SRAM.

Design ConstraintsTiming ConstraintsPin Constraints

Design ImplementationTarget TechnologyDevice Utilization and Performance Benchmarks

Reference DocumentsRevision History

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