DS532 PLB Double Data Rate (DDR) Synchronous DRAM (SDRAM) … · 2019-10-13 · NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the

IntroductionThe Xilinx Multi-CHannel On-chip Peripheral Bus Double Data Rate Synchronous DRAM (MCH OPB DDR2 SDRAM) controller for Xilinx FPGAs provides a DDR2 SDRAM con-troller that connects to the OPB and multiple channel inter-faces and provides the control interface for DDR2 SDRAMs It is assumed that the reader is familiar with DDR2 SDRAM and the MCH protocol

FeaturesThe Xilinx MCH OPB DDR2 SDRAM Controller is a soft IP core designed for Xilinx FPGAs and contains the following features

bull Parameterizable number of channel (MCH) interfaces that can be configured with the Xilinx Cachelink (XCL) protocol (see Reference Documents on page 53)

bull Optional OPB interface amp indeterminate burst support

bull Performs device initialization sequence upon power-up and reset conditions for ~200 us

bull Performs auto-refresh cycles

bull Supports DDR2 SDRAM self refresh mode

bull Supports CAS latencies of 3 4 and 5

bull Supports target word first XCL cacheline transactions of 1 4 8 and 16 words

bull Supports 16-bits 32-bits and 64-bits DDR2 SDRAM devices

bull Provides big-endian connections to memory devices

bull Supports multiple (up to 4) external DDR2 memory banks

bull Selectable On Die Termination (ODT)

bull Supports DDR2 burst size of 4

bull Supports differential DQSbull Capable to separate DDR2 clock frequency domain

from MCHOPB clock frequency domain Following combinations of frequencies are tested

- MCHOPB clock 66 MHz amp DDR2 clock 133 MHz

- MCHOPB clock100 MHz amp DDR2 clock 133 MHz

- MCHOPB clock100 MHz amp DDR2 clock 200 MHz

Multi-CHannel OPB Double Data Rate (DDR2) Synchronous DRAM (SDRAM) Controller

DS532 March 20 2006 0 0 Product Specification

LogiCOREtrade Facts

Core Specifics

Supported Device Family

QProtrade-R Virtextrade-II QPro Virtex-II Virtex-II Virtex-II

Pro Virtex-4 Spartantrade-3

Version of Core mch_opb_ddr2 v100a

Resources Used

Min Max

Please refer to Table 13 on page 48 Table 14 on page 50 and

Table 15 on page 52

Slices

Block RAMs

Provided with Core

Documentation Product Specification

Design File Formats

Constraints File NA

Verification NA

Instantiation Template

Reference Designs None

Design Tool Requirements

Xilinx Implementation Tools

ISE 81i or later

Verification NA

Simulation ModelSim SEEE 60a or later

Synthesis XST 81i or later

Support

Support provided by Xilinx Inc

Discontinued IP

DS532 March 20 2006 wwwxilinxcom 1Product Specification

copy 2004 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and further disclaimers are as listed at httpwwwxilinxcomlegalhtm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice

NOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this fea-ture application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any war-ranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose

MCH OPB DDR2 SDRAM Controller Design ParametersTo allow the user to create a MCH OPB DDR2 SDRAM controller that is uniquely tailored for the system certain features are parameterizable in the MCH OPB DDR2 SDRAM controller design This allows the user to have a design that only utilizes the resources required by the system and runs at the best possible performance The features that are parameterizable in the MCH OPB DDR2 SDRAM controller are shown in Table 1

Table 1 MCH OPB DDR2 SDRAM Controller Design Parameters

Generic Feature Description Parameter Name Allowable ValuesDefault Value

VHDL Type

MCH OPB DDR2 SDRAM Controller Features

G1 Target FPGA family C_FAMILY virtex2p spartan3 virtex4

virtex2p string

G2 Include support for registered DIMM

C_REG_DIMM 0 = DDR2 device is not registered DIMM

1 = DDR2 device is registered DIMM

0 integer

G3 Include logic to create extra setup time on DDR2 address and control signals[1]

C_EXTRA_TSU 0 = Donrsquot include logic to support extra setup time

1 = Include logic to support extra setup time

0 integer

G4 Supported number of external DDR2 SDRAM memory banks[2]

C_NUM_BANKS_MEM 1 - 4 1 integer

G5 Number of generated clock pairs supplied to the DDR2 memory

C_NUM_CLK_PAIRS 1 - 4 1 integer

G6 Include logic to support asynchronous DDR2 SDRAM clock from OPB bus clock

C_DDR_ASYNC_SUPPORT 1 = Include logic to separate DDR2 SDRAM clock domain from MCHOPB clock domain

0 = Not supported

1 integer

G7 Enable differential DQS capability for DDR2 memory devices

C_DDR_ENABLE_DIFF_DQS 0 = Disable differential DQS logic

1= Enable differential DQS logic

0 integer

G8 Specify number of IDELAYCTRL modules to instantiate for Virtex-4 implementation

C_NUM_IDELAYCTRL 1 - 20 1 integer

G9 On Die Termination selection

C_DDR2_ODT_SETTING 0 75 150

0 = ODT will be disabled

75 = ODT enabled and On Die Terminating resistance (Rtt) will be 75

150 = ODT enabled and Rtt will be 150

0 integer

Discontinued IP

2 wwwxilinxcom DS532 March 20 2006Product Specification

G10 Include OPB Slave Interface

C_INCLUDE_OPB_IPIF 0 = Donrsquot include OPB IPIF

1 = Include OPB IPIF

1 integer

G11 Include logic to support OPB bursts

C_INCLUDE_OPB_BURST_SUPPORT

0 = Donrsquot include logic to support OPB bursts

1 = Include logic to support OPB bursts

0 integer

G12 Arbitration mode between OPB and MCH interfaces

C_PRIORITY_MODE 0 = Fixed priority mode 0 integer

G13 Data bus width for MCH and OPB (if included in design)

C_MCH_OPB_DWIDTH 32 32 integer

G14 Address bus width for MCH and OPB (if included in design)

C_MCH_OPB_AWIDTH 32 32 integer

G15 MCHOPB clock period (ps)

C_MCH_OPB_CLK_PERIOD_PS

10000 15000 10000 integer

MCH Interface

G16 Number of MCH channels

C_NUM_CHANNELS 0 - 4 2 integer

G17 MCH protocol[3][4] C_MCHx_PROTOCOL 0 = XCL protocol (see Reference Documents on page 53)

0 integer

G18 Depth of MCH access buffer[3][5]

C_MCHx_ACCESSBUF_DEPTH

4 8 16 16 integer

G19 Depth of MCH read data buffer[3][6]

C_MCHx_RDDATABUF_DEPTH

0 4 8 16 16 integer

G20 Cacheline size[3] (in number of 32-bit words)

C_XCLx_LINESIZE 1 4 8 16 4 integer

G21 Write transfer type[3][7] C_XCLx_WRITEXFER 0 = No write transfers

1 = Single transfers only

2 = Cacheline transfers only

1 integer

G22 Include timeout counter C_INCLUDE_TIMEOUT_CNTR 0 = Donrsquot include an acknowledge timeout counter

0 integer

Table 1 MCH OPB DDR2 SDRAM Controller Design Parameters (Continued)

VHDL Type

Discontinued IP

G23 Number of clocks to wait for transfer acknowledge from the DDR2 controller before issuing a timeout error

C_TIMEOUT 1 - 512 16 integer

DDR2 SDRAM Controller Features

G24 Load Mode Register command cycle time (ps)

C_DDR_TMRD Note[8] 15000 integer

G25 Write Recovery Time (ps)

C_DDR_TWR Note[8] 15000 integer

G26 Write-to-Read Command Delay (Tck)

C_DDR_TWTR Note[8] 1 integer

G27 Delay after ACTIVE command before PRECHARGE command (ps)

C_DDR_TRAS Note[8] 45000 integer

G28 Delay after ACTIVE command before another ACTIVE or AUTOREFRESH command (ps)

C_DDR_TRC Note[8] 65000 integer

G29 Delay after AUTOREFRESH before another command (ps)

C_DDR_TRFC Note[8] 75000 integer

G30 Delay after ACTIVE command before READWRITE command (ps)

C_DDR_TRCD Note[8] 21000 integer

G31 Delay after ACTIVE command for a row before an ACTIVE command for another row (ps)

C_DDR_TRRD Note[8] 10000 integer

G32 Delay after a PRECHARGE command (ps)

C_DDR_TRP Note[8] 20000 integer

G33 Average periodic refresh command interval (ps)

C_DDR_TREFI Note[8] 7800000 integer

G34 Self refresh exit delay before issuing an ACTIVE command

C_DDR_TXSR Note[8] 80000 integer

VHDL Type

Discontinued IP

G35 ACTIVE command for a row before an ACTIVE command for another row when crossing internal 4 banks (ps)

C_DDR_TFAW Note[8][9] 50000 integer

G36 CAS Latency C_DDR_CAS_LAT 3 4 5 3 integer

G37 Cumulative data width of DDR2 SDRAM

C_DDR_DWIDTH 16 32 64 16 integer

G38 DDR2 SDRAM address width

C_DDR_AWIDTH See note[10] 13 integer

G39 DDR2 SDRAM column address width

C_DDR_COL_AWIDTH See note[10] 9 integer

G40 DDR2 SDRAM bank address width

C_DDR_BANK_AWIDTH 2 3[10] 2 integer

G41 DDR2 SDRAM clock period (ps)

C_DDR_CLK_PERIOD_PS 5000 7500 5000 integer

Address Space

G42 Base Address for Memory Bank x (x = 0 to 3)

C_MEMx_BASEADDR Valid address[11][12] - std_logic_vector

G43 High Address for Memory Bank x (x = 0 to 3)

C_MEMx_HIGHADDR Valid address[11][12] - std_logic_vector

VHDL Type

Discontinued IP

Simulation Only

G44 DDR2 Initialization time for simulation[13] (ps)

C_SIM_INIT_TIME_PS ge 200 us 2000000 00

integer

Notes 1 C_EXTRA_TSU parameter is only valid when C_REG_DIMM = 0 When C_EXTRA_TSU = 1 the design creates extra setup time on

the following signals DDR_CSn DDR_RASn DDR_CASn DDR_WEn DDR_BankAddr and DDR_Addr Setting C_EXTRA_TSU = 1 is useful for certain memory board applications with high input capacitance on DDR2 control and address connections

2 C_NUM_BANKS_MEM specifies the number of DDR2 SDRAM memory banks with identical device characteristics All the DDR2 SDRAM device characteristics specified in parameters G33 through G50 are applicable for all memory banks The C_NUM_BANKS_MEM parameter specifies the size of the DDR_CSn signal(s)

3 This design can accommodate up to 4 channels The generics associated with the MCH interfaces are designated with a C_MCHx_ prefix where x indicates the channel number and must be value between 0 and 3

4 C_MCHx_PROTOCOL = 0 (or XCL Xilinx Cachelink) is the only supported protocol5 The depth of the MCH access buffer (C_MCHx_ACCESSBUF_DEPTH) must be large enough to hold a cacheline write

C_MCHx_ACCESSBUF_DEPTH ge C_XCLx_LINESIZE for optimal performance6 If the master connected to the MCH interface can consume data as soon as it is available (ie instruction cache masters) the Read

Data buffer depth can be set to zero to save resources and eliminate extra latency Otherwise the Read Data buffer depth must be sized to accommodate any latency the master may have in reading data from this buffer

7 If the master connecting to the channel x will only perform read transfers (ie instruction cache masters) set C_XCLx_WRITEXFER = 0 to save resources

8 Values are as per DDR2 JEDEC standard9 C_DDR_TFAW setting is only valid when C_DDR_BANK_AWIDTH = 310 C_DDR_AWIDTH + C_DDR_COL_AWIDTH + C_DDR_BANK_AWIDTH + log2(C_DDR_DWIDTH8) must be lt

C_MCH_OPB_AWIDTH - 111 This design can accommodate up to 4 banks of DDR2 memory The address range generics are designated as

C_MEM0_BASEADDR C_MEM1_BASEADDR C_MEM0_HIGHADDR C_MEM1_HIGHADDR etc12 The range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must comprise a complete contiguous power of two

range such that range = 2m and the m least significant bits of C_MEMx_BASEADDR must be zero Any MCH or OPB transaction can be mapped to any DDR2 memory bank

13 This parameter adjusts the initialization time of the DDR2 for simulation only Must be ge 200 us

VHDL Type

Discontinued IP

Allowable Parameter CombinationsThe user must be aware of the following parameter combinations

bull The MCH OPB DDR2 SDRAM controller supports up to 4 banks of memory Each bank of memory has its own independent base address and address range Each address range specified by C_MEMx_BASEADDR and C_MEMx_HIGHADDR must comprise a complete contiguous power of two range such that range = 2m and the m least significant bits of C_MEMx_BASEADDR must be zero

bull The range specified by these parameters should not exceed the MCH OPB DDR2 SDRAM memory space

bull The OPB slave interface is only included in this design if C_INCLUDE_OPB_IPIF = 1 When C_INCLUDE_OPB_IPIF = 0 the C_INCLUDE_OPB_BURST_SUPPORT is unused

bull The parameter C_EXTRA_TSU is ignored when C_REG_DIMM = 1

Optimal MCH Parameter SettingsIf an XCL channel is connected to a master that will only perform read transactions then C_XCLx_WRITEXFER should be set to 0 indicating that no write transfers will be performed This will reduce the channel logic to only contain logic for read transactions

If an XCL channel is connected to a master that can consume data as soon as its available then C_MCHx_RDDATABUF_DEPTH for that channel should be set to 0 This will eliminate the read data buffer and eliminate the latency that would normally exist in reading data from this buffer If the master can not consume data as soon as its avail-able then C_MCHx_RDDATABUF_DEPTH for that channel should be set to accommodate any latency the master has in reading data from the Read Data buffer

Optimal performance will be achieved when the buffer depth of the Access buffer is set greater than or equal to the line size of the channel (C_MCHx_ACCESSBUF_DEPTH ge C_XCLx_LINESIZE)

Discontinued IP

MCH OPB DDR2 SDRAM Controller IO SignalsTable 2 provides a summary of all MCH OPB DDR2 SDRAM controller inputoutput (IO) signals

Table 2 MCH OPB DDR2 SDRAM Controller Pin Descriptions

Port Signal NameInterfa

ce IOInitial State Description

DDR2 SDRAM Signals

P1 DDR_Clk [0C_NUM_CLK_PAIRS-1] DDR2 O 0 DDR2 SDRAM clock

P2 DDR_Clkn [0C_NUM_CLK_PAIRS-1]

DDR2 O 1 DDR2 SDRAM inverted clock

P3 DDR_CKE [0C_NUM_BANKS_MEM-1]

DDR2 O 0 DDR2 SDRAM clock enable(s)

P4 DDR_CSn [0C_NUM_BANKS_MEM-1]

DDR2 O 1 Active low DDR2 SDRAM chip select(s)

P5 DDR_RASn DDR2 O 1 Active low DDR2 SDRAM row address strobe

P6 DDR_CASn DDR2 O 1 Active low DDR2 SDRAM column address strobe

P7 DDR_WEn DDR2 O 1 Active low DDR2 SDRAM write enable

P8 DDR_DM[0C_DDR_DWIDTH8-1] DDR2 O 0 DDR2 SDRAM data mask

P9 DDR_BankAddr[0C_DDR_BANK_AWIDTH-1]

DDR2 O 0 DDR2 SDRAM bank address

P10 DDR_Addr[0C_DDR_AWIDTH-1] DDR2 O 0 DDR2 SDRAM address

P11 DDR_DQ_o[0C_DDR_DWIDTH-1] DDR2 O 0 Output data to DDR2 SDRAM

P12 DDR_DQ_i[0C_DDR_DWIDTH-1] DDR2 I - Input data from DDR2 SDRAM

P13 DDR_DQ_t[0C_DDR_DWIDTH-1] DDR2 O 0 3-state control for DDR2 SDRAM data buffers

P14 DDR_DQS_o[0C_DDR_DWIDTH8-1]

DDR2 O 0 Output data strobe to DDR2 SDRAM

P15 DDR_DQS_i[0C_DDR_DWIDTH8-1]

DDR2 I - Input data strobe from DDR2 SDRAM

P16 DDR_DQS_t[0C_DDR_DWIDTH8-1]

DDR2 O 1 3-state control for DDR2 SDRAM data strobe buffers

P17 DDR_DQSn_o[0C_DDR_DWIDTH8-1]

DDR2 O 0 Output differential data strobe to DDR2 SDRAM

P18 DDR_DQSn_i[0C_DDR_DWIDTH8-1]

DDR2 I - Input differential data strobe from DDR2 SDRAM

P19 DDR_DQSn_t[0C_DDR_DWIDTH8-1]

DDR2 O 1 3-state enable for DDR2 SDRAM differential data strobe buffers

P20 DDR_ODT[0C_NUM_BANKS_MEM-1][1]

DDR2 O 0 On Die Termination (ODT) signal for DDR2 SDRAM

P21 DDR_Init_done DDR2 O 0 Indicates that the DDR2 initialization is complete

Clock Signals

Discontinued IP

P22 Device_Clk[2] CLK I - Device clock

P23 Device_Clk_n[2][3] CLK I - Device clock phase shifted by 180 degrees

P24 Device_Clk90_in[2] CLK I - Device clock phase shifted by 90 degrees

P25 Device_Clk90_in_n[2][3] CLK I - Device clock phase shifted by 270 degrees

P26 DDR_Clk90_in[2][3] CLK I - DDR2 SDRAM feedback clock shifted by 90 degrees

P27 DDR_Clk90_in_n[2][3] CLK I - DDR2 SDRAM feedback clock shifted by 270 degrees

P28 Clk_200[2][4] CLK I - 200 MHz clock input used in Virtex-4 implementation for IDELAYCTRL module

P29 Cal_Clk[2][4] CLK I - 14 Clk_200 clock input used in Virtex-4 implementation

OPB Slave Signals[5][6]

P30 OPB_Select OPB I - OPB select

P31 OPB_RNW OPB I - OPB read not write

P32 OPB_ABus[0C_MCH_OPB_AWIDTH-1]

OPB I - OPB address bus

P33 OPB_DBus[0C_MCH_OPB_DWIDTH-1]

OPB I - OPB data bus

P34 OPB_BE[0C_MCH_OPB_DWIDTH8-1]

OPB I - OPB byte enables

P35 OPB_seqAddr OPB I - OPB sequential address

P36 Sl_xferAck OPB O 0 OPB DDR2 SDRAM controller transfer acknowledge

P37 Sl_errAck OPB O 0 OPB DDR2 SDRAM controller error acknowledge

P38 Sl_toutSup OPB O 0 OPB DDR2 SDRAM controller time-out suppress

P39 Sl_retry OPB O 0 OPB DDR2 SDRAM controller retry

P40 Sl_DBus[0C_MCH_OPB_DWIDTH-1]

OPB O 0 OPB DDR2 SDRAM controller OPB slave data bus

MCH Signals[7]

P41 MCH_OPB_Clk MCH I - MCHOPB clock

P42 MCH_OPB_Rst MCH I - MCHOPB reset

P43 MCHx_Access_Control (x = 0 to 3) MCH I - Control signal to the Access buffer of MCH interface x (x = 0 to 3) This signal indicates the type of access to be performed (read or write) and the size of the access (byte halfword or word)

Table 2 MCH OPB DDR2 SDRAM Controller Pin Descriptions (Continued)

Discontinued IP

Parameter-Port DependenciesThe dependencies between the MCH OPB DDR2 SDRAM controller design parameters and IO signals are shown in Table 3 Table 3 shows when certain features are parameterized out of the design the related logic will no longer be part of the design The unused input signals and related output signals are set to a specified value

P44 MCHx_Access_Data(0C_MCH_OPB_DWIDTH-1) (x = 0 to 3)

MCH I - Write Data to the Access buffer of MCH interface x (x = 0 to 3)

P45 MCHx_Access_Write (x = 0 to 3) MCH I - Write signal to the Access buffer of MCH interface x (x = 0 to 3)

P46 MCHx_Access_Full (x = 0 to 3) MCH O 0 Indicator that the Access buffer of MCH interface x is full (x = 0 to 3)

P47 MCHx_ReadData_Control (x = 0 to 3) MCH O 1 Control signal for the Read Data buffer of MCH interface x (x = 0 to 3) This signal indicates if the data from the Read Data buffer is valid

P48 MCHx_ReadData_Data(0C_MCH_OPB_DWIDTH-1) (x = 0 to 3)

MCH O 0 Read data from the Read Data buffer of MCH interface x (x = 0 to 3)

P49 MCHx_ReadData_Read (x = 0 to 3) MCH I - Read signal to the Read Data buffer of MCH interface x (x = 0 to 3)

P50 MCHx_ReadData_Exists (x = 0 to 3) MCH O 0 Indicator that the Read Data buffer of MCH interface x is non-empty (x = 0 to 3)

P51 DDR_Sleep System I - Rising edge on this signal enters the DDR2 SDRAM self refresh mode A minimum period of 50us after the assertion of DDR_Sleep is required before MCH_OPB_Rst can be asserted

P52 DDR_WakeUp System I - This signal indicates whether the DDR2 SDRAM must go through the power-up initialization after reset or if only the sequence to exit the self refresh mode needs to be executed This signal is sampled when reset negates and therefore should be asserted before MCH_OPB_Rst negates

Notes 1 When this signal is asserted high the selected Rtt value is specified by the parameter C_DDR2_ODT_SETTING For more

information please refer to section On Die Termination (ODT)2 For more information on clocking options please refer to section DDR2 Clocking on page 313 Input signal is unused when targeting for Virtex-4 architecture It is recommended to ground these inputs4 Input signal is unused when targeting architecture other than Virtex-4 It is recommended to ground these inputs5 Please refer to the IBM OPB Architecture Specification for more detailed information on these signals6 OPB signals are not available when C_INCLUDE_OPB_IPIF = 07 MCH signals are unavailable when C_NUM_CHANNELS = 0 with the exception of MCH_OPB_Clk and MCH_OPB_Rst

Discontinued IP

Table 3 Parameter-Port Dependencies

Generic or Port Parameter Affects Depends Description

Design Parameters

G1 C_FAMILY P23 P25 P26 P27 P28 P29

- P23 P25 P26 P27 are not used when C_FAMILY = virtex4

P28 P29 are not used when C_FAMILY ne virtex4

G4 C_NUM_BANKS_MEM P3 P4 P20

- Specifies the number of DDR2 SDRAM memory banks

G5 C_NUM_CLK_PAIRS P1 P2 - Number of generated DDR2 clock pairs

G7 C_DDR_ENABLE_DIFF_DQS P17 P18

- Input signals are unused and output signals are set to the default value when C_DDR_ENABLE_DIFF_DQS = 0

G10 C_INCLUDE_OPB_IPIF P30 P31 P32 P33 P34 P35 P36 P37 P38 P39

- Input signals are unused and output signals are set to the default value when C_INCLUDE_OPB_IPIF = 0

G11 C_INCLUDE_OPB_BURST_SUPPORT

- G9 Unused if C_INCLUDE_OPB_IPIF = 0

G13 C_MCH_OPB_DWIDTH P33 P34 P40 P44

- Affects OPB data width when C_INCLUDE_OPB_IPIF = 1

G14 C_MCH_OPB_AWIDTH P32 - Affects OPB address width when C_INCLUDE_OPB_IPIF = 1

G16 C_NUM_CHANNELS P43 P44 P45 P46 P47 P48 P49 P50

- Input signals are unused and output signals are set to the default value when C_NUM_CHANNELS = 0

G46 C_DDR_DWIDTH P8

P11 - P19

- Specified DDR2 memory data width

G47 C_DDR_AWIDTH P10 -

G49 C_DDR_BANK_AWIDTH P9 -

G3 C_EXTRA_TSU - G2 Valid only when C_REG_DIMM = 0

IO Signals

P1 DDR_Clk [0C_NUM_CLK_PAIRS-1]

- G5 The number of clock pairs is generated based on C_NUM_CLK_PAIRS

- G5 The number of inverted clock pairs is generated based on C_NUM_CLK_PAIRS

- G4 The number of clock enables is generated based on C_NUM_BANKS_MEM

Discontinued IP

- G4 The number of chip selects is generated based on C_NUM_BANKS_MEM

P8 DDR_DM[0C_DDR_DWIDTH8-1] - G37 Width of data mask signal depends on generic C_DDR_DWIDTH

P9 DDR_BankAddr[0C_DDR_BANK_AWIDTH]

- G40 Bank address width depends on generic C_DDR_BANK_AWIDTH

P10 DDR_Addr[0C_DDR_AWIDTH] - G38 DDR2 address width depends on generic C_DDR_AWIDTH

P11 DDR_DQ_o[0C_DDR_DWIDTH-1] - G37 Data output width depends on generic C_DDR_DWIDTH

P12 DDR_DQ_i[0C_DDR_DWIDTH-1] - G37 Data input width depends on generic C_DDR_DWIDTH

P13 DDR_DQ_t[0C_DDR_DWIDTH-1] - G37 Data 3-state enable signal width depends on generic C_DDR_DWIDTH

- G37 Output data strobe width depends on generic C_DDR_DWIDTH

- G37 Input data strobe width depends on generic C_DDR_DWIDTH

- G37 3-state enable data strobe width depends on generic C_DDR_DWIDTH

- G37 Output differential data strobe width depends on generic C_DDR_DWIDTH Output is driven high when C_DDR_ENABLE_DIFF_DQS = 0

- G37 Input differential data strobe width depends on generic C_DDR_DWIDTH Input signals is unused when C_DDR_ENABLE_DIFF_DQS = 0

- G37 3-state enable differential data strobe width depends on generic C_DDR_DWIDTH Signals is unused when C_DDR_ENABLE_DIFF_DQS = 0

P20 DDR_ODT[0C_NUM_BANKS_MEM-1]

- G4 On Die Termination (ODT) signal width depends on generic C_NUM_BANKS_MEM

P23 Device_Clk_n - G1 Unused when C_FAMILY = virtex4

P25 Device_Clk90_in_n - G1 Unused when C_FAMILY = virtex4

P26 DDR_Clk90_in - G1 Unused when C_FAMILY = virtex4

P27 DDR_Clk90_in_n - G1 Unused when C_FAMILY = virtex4

P28 Clk_200 - G1 Unused when C_FAMILY ne virtex4

P29 Cal_Clk - G1 Unused when C_FAMILY ne virtex4

P30 OPB_Select - G10 Unused when C_INCLUDE_OPB_IPIF = 0

Table 3 Parameter-Port Dependencies (Continued)

Discontinued IP

P31 OPB_RNW - G10 Unused when C_INCLUDE_OPB_IPIF = 0

- G10 G14 Unused when C_INCLUDE_OPB_IPIF = 0

P35 OPB_seqAddr - G10 Unused when C_INCLUDE_OPB_IPIF = 0

P36 Sl_xferAck - G10 Unused when C_INCLUDE_OPB_IPIF = 0

P37 Sl_errAck - G10 Unused when C_INCLUDE_OPB_IPIF = 0

P38 Sl_toutSup - G10 Unused when C_INCLUDE_OPB_IPIF = 0

P39 Sl_retry - G10 Unused when C_INCLUDE_OPB_IPIF = 0

P43 MCHx_Access_Control (x = 0 to 3) - G16 Unused when C_NUM_CHANNELS = 0

P44 MCHx_Access_Data[0C_MCH_OPB_DWIDTH-1] (x = 0 to 3)

- G13 G16 Unused when C_NUM_CHANNELS = 0

P45 MCHx_Access_Write (x = 0 to 3) - G16 Unused when C_NUM_CHANNELS = 0

P46 MCHx_Access_Full (x = 0 to 3) - G16 Unused when C_NUM_CHANNELS = 0

P47 MCHx_ReadData_Control (x = 0 to 3)

- G16 Unused when C_NUM_CHANNELS = 0

P48 MCHx_ReadData_Data[0C_MCH_OPB_DWIDTH-1] (x = 0 to 3)

P49 MCHx_ReadData_Read (x = 0 to 3) - G16 Unused when C_NUM_CHANNELS = 0

P50 MCHx_ReadData_Exists (x = 0 to 3)

Discontinued IP

Connecting to Memory

Big-Endian Memory Data Types and OrganizationDDR2 SDRAM memory can be accessed as byte (8 bits) halfword (2 bytes) word (4 bytes) or double word (8 bytes) depending on the size of the bus to which the processor is attached From the point of view of the MCHOPB data is orga-nized as big-endian The bit and byte labeling for the big-endian data types is shown below in Figure 1

Memory to MCH OPB DDR2 SDRAM Controller ConnectionsThe data and address signals at the MCH OPB DDR2 SDRAM controller are labeled with big-endian bit labeling (for exam-ple D(031) D(0) is the MSB) whereas most memory devices are either endian agnostic (they can be connected either way) or little-endian D(310) with D(31) as the MSB

Caution must be exercised with the connections to the external memory devices to avoid incorrect data and address con-nections

Table 6 shows the correct mapping of MCH OPB DDR2 SDRAM controller pins to DDR2 SDRAM device pins

Figure 1 Big-Endian Data Types

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

Example 1 32-bit ConnectionFigure 2 illustrates an example of connecting memory to the MCH OPB DDR2 SDRAM controller design The example shown here has the following specified parameters

bull C_NUM_BANKS_MEM = 1

bull C_DDR_DWIDTH = 32

bull C_DDR_BANK_AWIDTH = 2

bull C_DDR_AWIDTH = 13

bull C_DDR_ENABLE_DIFF_DQS = 0

Table 6 MCH OPB DDR2 SDRAM controller interconnect to DDR2 SDRAM

DescriptionMCH OPB DDR2 SDRAM Controller Signals

(MSBLSB)DDR2 SDRAM Signals

(MSBLSB)

Data Bus DDR_DQ[0C_DDR_DWIDTH - 1] DQ[C_DDR_DWIDTH - 10]

Bank Address DDR_BankAddr[0C_DDR_BANK_AWIDTH - 1] BA[C_DDR_BANK_AWIDTH - 10]

Address DDR_Addr[0C_DDR_AWIDTH - 1] A[C_DDR_AWIDTH - 10]

Data Strobe DDR_DQS[0C_DDR_DWIDTH8 - 1] UDQS LDQS

Differential Data Strobe DDR_DQSn[0C_DDR_DWIDTH8 - 1] UDQS LDQS

Data Mask DDR_DM[0C_DDR_DWIDTH8 - 1] UDM LDM

Figure 2 MCH OPB DDR2 SDRAM Controller Connection Example to 32-bit DDR2 SDRAM

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Example 2 16-bit Connection Figure 3 illustrates an example of connecting memory to the MCH OPB DDR2 SDRAM controller for 16-bit DDR2 SDRAM The example shown here has the following specified parameters

DDR2 SDRAM Address Mapping

An address offset is calculated based on the width of the DDR2 SDRAM data bus The DDR2 SDRAM column address is then mapped to the MCH OPB address bus followed by the row address and bank address

The MCH OPB address bus bit locations for the DDR2 SDRAM column row and bank addresses are calculated as shown in Table 7 and Table 8

Table 7 DDR2 SDRAM Address Offset Calculations

Variable Equation

ADDR_OFFSET log2(C_DDR_DWIDTH8)

COLADDR_STARTBIT C_MCH_OPB_AWIDTH - (C_DDR_COL_AWIDTH + ADDR_OFFSET)

COLADDR_ENDBIT COLADDR_STARTBIT + C_DDR_COL_AWIDTH - 1

ROWADDR_STARTBIT COLADDR_STARTBIT - C_DDR_AWIDTH

ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH - 1

BANKADDR_STARTBIT ROWADDR_STARTBIT - C_DDR_BANK_AWIDTH

BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BANK_AWIDTH - 1

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

MCH OPB DDR2 SDRAM Controller

DM(10)DDR_DM(01)

Discontinued IP

Table 9 and Table 10 show an example of the mapping between the MCH or OPB address and the DDR2 SDRAM address when the data width of the DDR2 SDRAM is 16 and the data width of the MCHOPB bus is 32 the column address width is 9 the row address width is 13 and the bank address width is 2

IMPORTANT Virtex-4 Virtex-II Pro and Spartan-3 IO pairs share input and output clock signals Since the DDR registers in the IO blocks use both of the input and output clock signals the ports assigned to the IO pairs must use the same input and output clocks Care should be taken when making port IO assignments The DDR_DQ and DDR_DM signals use the system clock as the output clock and the DDR_DQS signals use a 90 degree phase shift of the system clock as the output clock Therefore a DDR_DQS signal should not be assigned with a DDR_DQ signal or a DDR_DM signal in an IO pair

Note this MCH OPB DDR2 SDRAM controller design utilizes the DDR registers in the FGPA IO blocks and must be targeted to FPGA families that support this feature

The DDR_DQ and DDR_DQS buses are 3-stateable the user should pullup these signals in the FPGA IO blocks or external to the FPGA in the board design Note that the MCH OPB DDR2 SDRAM controller design will drive the DQS signals to a high value lsquo1rsquo during the IDLE state so only one MCH OPB DDR2 SDRAM controller can be used to control a DDR2 SDRAM ie two MCH OPB DDR2 SDRAM controllers can not share the same DDR2 SDRAM

Table 8 DDR2 SDRAM - Address Bus Assignments

DDR2 SDRAM Address MCH OPB Address Bus

Column Address MCH_OPB_ABus(COLADDR_STARTBIT to COLADDR_ENDBIT)

Row Address MCH_OPB_ABus(ROWADDR_STARTBIT to ROWADDR_ENDBIT)

Bank Address MCH_OPB_ABus(BANKADDR_STARTBIT to BANKADDR_ENDBIT)

Table 9 MCH OPB Example DDR2 SDRAM Address Offset Calculations

Variable Equation Value

ADDR_OFFSET log2(C_DDR_DWIDTH8) log2(16 8) = 1

32 - (9 + 1) = 22

COLADDR_ENDBIT COLADDR_STARTBIT + C_DDR_COL_AWIDTH - 1 22 + (9 - 1) = 30

ROWADDR_STARTBIT COLADDR_STARTBIT - C_DDR_AWIDTH 22 - 13 = 9

ROWADDR_ENDBIT ROWADDR_STARTBIT + C_DDR_AWIDTH - 1 9 + 13 - 1 = 21

BANKADDR_STARTBIT ROWADDR_STARTBIT - C_DDR_BANK_AWIDTH 9 - 2 = 7

BANKADDR_ENDBIT BANKADDR_STARTBIT + C_DDR_BANK_AWIDTH - 1 7 + 2 - 1 = 8

Table 10 MCH OPB DDR2 SDRAM Controller Address Bus Assignment Example

DDR2 SDRAM Address MCH or OPB Address Bus

Column Address MCH_OPB_ABus(2230) amp lsquo0rsquo

Row Address MCH_OPB_ABus(921)

Bank Address MCH_OPB_ABus(78)

Discontinued IP

MCH OPB DDR2 SDRAM Controller DesignThe block diagram for the MCH OPB DDR2 SDRAM controller is shown in Figure 4 The MCH OPB DDR2 SDRAM control-ler consists of the MCH OPB IPIF and the DDR2 SDRAM controller The MCH OPB IPIF provides the bus protocol and Multi-CHannel (MCH) interface The DDR2 SDRAM controller provides the DDR2 SDRAM interface including the control state machines initialization logic and IO registers

The separation of the Command State Machine and the Data State Machine allows for the application of commands to the DDR2 while data receptiontransmission is in progress Overlapping the DDR2 SDRAM commands with the data transfer when accessing data in the same row of the same bank allows for more optimal DDR2 SDRAM operation

The MCH OPB DDR2 SDRAM controller consists of

a The MCH OPB IPIF module provides the interface between the MCH and OPB connections to the DDR2 SDRAM controller

b The Init State Machine module is responsible for initialization sequence of commands that are issued to the DDR2 SDRAM upon power up or self refresh

c The Command State Machine is responsible to issue commands (readwrite self refreshauto refresh precharge etc) to the DDR2 SDRAM after the completion of initialization

d The Data State Machine is responsible for controlling the flow of data to and from the DDR2 SDRAM

e The Write Async FIFO module separates the DDR2 SDRAM clock domain from the MCHOPB clock domain This allows the MCH OPB DDR2 SDRAM controller to operate on two independent frequencies

f The Tap Control amp Data Tap Increment modules calibrate the IDELAY tap value required to center align the data with respect to internal read clock for Virtex-4 devices

g The Reg Unreg module is responsible to register the commands issued to the DDR2 SDRAM when the parameter C_REG_DIMM = 1

h The IO Reg module is responsible to register the control and data signals to and from the DDR2 SDRAM

i The Read Data Path module is responsible for storing the data captured from IO Reg module in to an asynchronous FIFO and will transfer the same to the MCHOPB

j The Counters module incorporates logic to count various DDR2 SDRAM timing parameters and enable Command State Machine to issue commands at the end of the count

k The Multiple Data Width module is instantiated when the data width of the DDR memory is equal to or greater than the data width of the OPB or MCH channels In this controller the Multiple Data Width module will be instantiated when the C_DDR_DWIDTH = 32 or C_DDR_DWIDTH = 64

l FIFO Read Control module is responsible to generate read enable signal to the Async FIFO used in the Write Async FIFO module

m Module Clock Generator is responsible to generate the complemented clocks (DDR_Clk amp DDR_Clkn) to the DDR2 SDRAM

n The IDELAYCTRL module(s) are specific to Virtex-4 devices The IDELAYCTRL module requires a 200 MHz clock and controls the tap value of the IDELAY modules instantiated in the IO Reg module

Discontinued IP

Self RefreshThe MCH OPB DDR2 controller is capable of placing the DDR2 SDRAM into self refresh mode When the DDR2 SDRAM is placed in to self refresh mode the contents of memory are saved due to the memory itself issuing refresh cycles

DDR_Sleep and DDR_Wakeup are two inputs to the MCH OPB DDR2 SDRAM controller to support the DDR2 SDRAM self refresh mode These are discrete input signals and must be generated at the system level they are not derived from theinterface

A rising edge of the DDR_Sleep signal will cause the MCH OPB DDR2 SDRAM controller to execute the command sequences required to place the DDR2 SDRAM into self refresh MCH_OPB_Rst is then asserted to place the entire system into reset A minimum period of 50 us from the assertion of DDR_Sleep to the assertion of MCH_OPB_Rst is required to insure the DDR2 SDRAM is in the self refresh mode Note that the MCH OPB DDR2 SDRAM controller does not provide the timing for the reset assertion this should be done at the system level Please refer to Figure 5 for information on the timing relationships of these signals

Figure 4 MCH OPB DDR2 SDRAM Controller Block Diagram

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

Clk_DDR_Rddata Clk_DDR_Rddata_n2

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Note 1 Included only when C_FAMILY = Virtex-4Note 2 Included only when C_FAMILY = not Virtex-4

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

TAP Control1Calib Done

DDR_ReadDQS_Rise

Valid tap count amp idelay

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

DDR_Sleep DDR_Wakeup

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DM[0n]DDR_BankAddr [0n]

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

The DDR_WakeUp signal is used to inform the MCH OPB DDR2 SDRAM controller if the power-up initialization sequence needs to be performed or if the sequence to instruct the DDR2 SDRAM to exit self refresh needs to be performed If the DDR_WakeUp signal is de-asserted when MCH_OPB_Rst de-asserted the MCH OPB DDR2 SDRAM controller will per-form the initialization sequence for DDR2 SDRAM If the DDR_WakeUp signal is asserted when MCH_OPB_Rst negates the MCH OPB DDR2 SDRAM controller will instruct the DDR2 SDRAM to exit the self refresh mode Note that the DDR_WakeUp signal must be at its desired level at least 5 clock periods before MCH_OPB_Rst negates It is assumed that the clock is stable before MCH_OPB_Rst de-asserted Please refer to Figure 6 for information on the timing relationships of these signals

Figure 5 Entering DDR2 Self Refresh

Figure 6 Exiting DDR2 Self Refresh

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP ACT NOP WRITE NOP PRE NOP RFSH NOP

A=50 us minimum delay from asserting DDR_Sleep before MCH_OPB_Rst can be asserted

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A = DDR_Wakeup setup time to negation of resetAssumes clock is stable when reset is negated

Txsr=Time to exit Self Refresh mode

A Txsr

Discontinued IP

Init State MachineDDR2 SDRAM must be powered-up and initialized in a predefined manner After power supplies and all the clocks are sta-ble the DDR2 SDRAM requires a 200 us delay prior to applying an executable command

The Init State Machine provides the 200 us delay and the sequencing of the required DDR2 SDRAM start-up commands It instructs the command state machine to send the proper commands in the proper sequence to the DDR2 SDRAM This state machine starts execution after reset and returns to the IDLE state when reset is applied

When the initialization sequence has been completed the DDR_Init_done signal is asserted

Note that after reset has been applied the 200 us delay is again implemented before any commands are issued to the DDR2 SDRAM The 200 us delay must be accounted for simulation as well as the delay of the command sequence

Command State MachineThe Command State Machine provides the address bus and commands signals to the DDR2 SDRAM It sends the enable signal to the Data State Machine to start the receptiontransmission of data If a burst transaction is in progress or a second-

Figure 7 Init State Machine

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

(calib_done and FIFO_rst_done) = 1

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ary transaction has been received the Command State Machine will send the next command to the DDR2 SDRAM while data receptiontransmission is still in progress to optimize the DDR2 SDRAM operation

A simplified version of the Command State Machine is shown in Figure 8 For readability only the major state transitions are shown

Figure 8 Command State Machine

Tras_min_end + FIFO_rst_done

Refresh|Trefi_endIDLEIDLE

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

Comb_Bus2IP_CS +GPcnt_end

Comb_Bus2IP_CS +GPcnt_end READ_CAL_CMD

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

Tras_min_end +Trefi_end | CS

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

Tcmd_end + Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

Data State MachineThe Data State Machine is responsible for controlling the flow of data to and from the DDR2 SDRAM The Data State Machine monitors the pend_read or pend_write signals from the Command State Machine to determine if more data trans-missions are necessary The Data State Machine waits for C_DDR_CAS_LAT during read operations and asserts the ddr_brst_end signal when the DDR2 SDRAM has completed the data transfer The Data State Machine provides the read_data_en signal to the input DDR registers of an FPGA and Read Data Path FIFO A simplified version of the Data State Machine is shown in Figure 9

Write Async FIFO and FIFO Read ControlThis core requires the OPB or MCH logic to operate at a separate clock frequency than the DDR2 SDRAM interface The parameter C_DDR_ASYNC_SUPPORT is set to the constant value of 1 to allow the user to separate the system and DDR2 device clock domains The MCH_OPB_Clk is used for writing in to the Async FIFO and the DDR2 Device_Clk is used for reading the data from the FIFO The logic includes a state machine and an asynchronous FIFO in order to synchronize the command data address data mask and control signals The logic in this module is shown in Figure 10 which includes state machine logic as well as instantiation of multiple asynchronous FIFOs The output of the asynchronous FIFO is then pro-vided in to the IO reg module

The Command FIFO write enable signal (cmd_fifo_wr_en) is asserted when a DDR2 SDRAM command (Active Write Read Refresh Precharge) is issued by the Command State Machine The control signal dq_oe_cmb enables writing of data and commands to the Data FIFO and Command FIFO respectively Reading of both the Command FIFO and the Data FIFO is controlled by the FIFO Read Control module The FIFO Read Control module monitors the empty flags of Command FIFO and Data FIFO to enable reading each FIFO

Figure 9 Data State Machine

WRITE_DATAREAD_DATA

pend_write

ddr_brst_endpend_read

pend_write

pend_writeddr_brst_end

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Figure 10 Block Diagram of Write Path Asynchronous Logic

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

command_fifo_read_en

Data FIFO

DDR_write_data DDR_write_data_mask

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

RASn CASn WEn CSn BankAdrr Addr Dq_oe_cmb din

write_data write_data_mask

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_RASn DDR_CASn DDR_WEn DDR_CSn DDR_BankAdrr DDR_Addr

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

Tap Control and Data Tap IncrementThe Tap Control and Data Tap Increment modules (shown in Figure 12) are only instantiated when targeting Virtex-4 archi-tectures (C_FAMILY = virtex4) Non Virtex-4 implementations do not instantiate these modules The IDELAY module instan-tiation on all DQ and DQS signals is shown in Figure 22

The Tap Control module issues back to back read cycles to the memory during the initialization sequence During these read cycles the incoming DQS signal(s) are sampled and the midpoint of the pulse is determined

Once the midpointtap value is determined for the DQS signal(s) the Data Tap Increment module also sets the IDELAY tap value of the corresponding DQ data bits to the same value

The IDELAY modules (in the IOB) are calibrated at an incremental value determined by the clock input to the IDELAYCTRL module(s) In this design a 200 MHz clock is applied to the IDELAYCTRL module(s) which in turn set the time delay of the 64 count tap value

IO Registers

Control SignalsAll control signals and the address bus to the DDR2 SDRAM are registered in the IOBs of the FPGA

Write Data The DDR IO registers are used to output the write data to the DDR2 SDRAM as shown in Figure 11 Since the DDR2 clocks (DDR_Clk and DDR_Clkn) are generated from the Clk90 output of the DCM the CLK0 output of the DCM is used to clock out the data so that the DDR2 clock is centered on the DDR2 SDRAM data

Discontinued IP

Figure 11 Write Data Path

CDevice_Clk

Write_data_en

Write_data[0C_DDR_DWIDTH-1]

Write_data[C_DDR_DWIDTH to C_DDR_DWIDTH2-1]

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

CNot included in core logic

Device_Clk

Write_data_mask DDR_DM [i]1

Not included in core logic

Device_Clk_n

Device_Clk90_n

Note1 Signals are duplicated based on the parameter C_DDR_DWIDTH

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Read Data (Non Virtex-4 Implementation)The DDR IO registers sample the read data from the DDR2 SDRAM as shown in Figure 12 The clock output (DDR_Clk) is used to supply the feedback clock (matching trace lengths) back into the FPGA This feedback clock is fed into a DCM and generates DDR_Clk90_in and DDR_Clk90_in_n These clock signals are used to capture the read data at the IOB during a read cycle as shown in Figure 12

During a read cycle the data strobe signal from the DDR2 SDRAM (DDR_DQS) is registered only on the rising edge of DDR_Clk90_in so that it is always high while the DDR2 SDRAM is transmitting data This signal will be used by the Read Data Path logic as the write enable into a FIFO

Read Data (Virtex-4 Implementation)The IOB IDELAY components and IDDR registers are used to read data from the DDR2 SDRAM as shown in Figure 13 The IDELAY modules are calibrated during the initialization sequence to center align the input DQ and DQS signals to the Device_Clk The calibration determines the appropriate sample time based on Tsu and Th requirements on the IDDR reg-ister components

Figure 12 DDR2 Input Data Registers

Q0DDR_RdData_high

Q1 DDR_RdData_lowDDR_RdData

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

CENot included in core logic

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Figure 13 V4 IDDR Register Usage

Discontinued IP

Read Data Path LogicThe read data output from the IOB will be a vector of size C_DDR_DWIDTH 2 when applied as an input to the Read Data Path module

The Read Data Path logic consists of an asynchronous FIFO in which the DDR2 SDRAM data is written on the rising edge of the Clk_DDR_Rddata (derived from DDR_Clk90_in the DCM CLK90 output from the DDR feedback clock for non Virtex4 implementations) clock and read on the rising edge of MCH OPB clock For Virtex-4 design implementations the FIFO write clock is the rising edge of the Device_Clk the same clock used to capture data in the IOB IDDR register components

The asynchronous FIFO width is C_DDR_DWIDTH 2 Once the FIFO is not empty the data is read from the FIFO and a read acknowledge is generated The asynchronous FIFO of the Read Data Path module is shown in Figure 14

The asynchronous FIFO of the Read Data Path module for Virtex-4 implementation is shown in Figure 15

Multiple Data WidthThe Multiple Data Width module is instantiated when the data width of the DDR memory is equal to or greater than the data width of the OPB or MCH channels In this controller the Multiple Data Width module will be instantiated when the C_DDR_DWIDTH = 32 or C_DDR_DWIDTH = 64

Figure 14 Read Data Path Module for Non Virtex-4 Architecture

Figure 15 Read Data Path Module for Virtex-4 Architecture

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

DDR_ReadData [0C_DDR_ DWIDTH2-1]

Discontinued IP

On Die Termination (ODT)Termination resistance can be enabled on the DDR2 SDRAM memory devices ODT allows selectable effective resistance (Rtt (effective)) to be enabled or disabled on a per transaction basis

The ODT feature minimizes signal reflections in addition to the termination available in the FPGA IO buffers

The MCH OPB DDR2 Controller signal DDR_ODT allows the controller to independently turn on or off the termination resistance internal to the DDR2 memory devices

The impedance value of On Die Termination effective resistance (Rtt) can be selected using the parameter C_DDR2_ODT_SETTING described in Table 1 as ldquoODT not selectedrdquo or ODT selected (75 or 150 ) Rtt values are set during DDR2 SDRAM initialization process using the Extended Mode Register (EMRS1) by the controller based on the parameter setting Figure 16 shows the ODT structure

Figure 16 ODT Structure

When C_DDR2_ODT_SETTING = 75

MCH OPB DDR2

Controllerto internal logic

150 Ω

150 ΩDDR_DQ [0n]DDR_DQS [0n]DDR_DQSn[0n]DDR_DM [0n]

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DQ [0n]DDR_DQS [0n]DDR_DQSn[0n]

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

Figure 17 shows the ODT turn-on delay tAOND and turn-off delay tAOFD timing When ODT is enabled it will be active for all memory transactions The ODT pin will be asserted (equal to 1) tAOND before the data is active on the data pins and ODT will be disabled (equal to 0) once tAOFD is met

Differential DQSDDR2 SDRAM supports an additional differential data strobe DQSn Differential DQS is enabled by the Initialization State Machine in writing to the Extended Mode Register of the DDR2 SDRAM memory (when C_DDR_ENABLE_DIFF_DQS = 1) If differential strobes are enabled DQS operates the same as in single-ended mode with the addition of DQSn operating as the complement of DQS

Since the DQS signal behavior is source-synchronous during read operations the DDR2 SDRAM will drive both the DQS and DQSn signals if differential DQS is enabled During write operations the MCH OPB DDR2 controller will drive the DQS and DQSn

The DQS and DQSn signals are designed as two independent IO signals to the DDR2 memory a differential IO buffer in the FPGA is not required

DDR2 Clocking

MCH OPB DDR2 SDRAM ClockingTable 12 shows the clock frequency combinations supported in the MCH OPB DDR2 SDRAM controller for the MCHOPB bus and the DDR2 SDRAM clock

Non Virtex-4 Clock GenerationThe clocking scheme required in the FPGA (for the design implementations other than Virtex-4) and used by the MCH OPB DDR2 SDRAM controller is shown in Figure 18 and Figure 19

Figure 17 ODT Timing

Table 12 Supported Clocking Configurations

C_MCH_OPB_CLK_PERIOD_PS C_DDR_CLK_PERIOD_PS

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

Figure 18 MCH OPB DDR2 SDRAM Controller - Non-Virtex-4 Clocking (Option 1)

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

Device_ClkDevice_Clk_n

Device_Clk90_inDevice_Clk90_in_n

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses local clock inversion for the generation of Device_Clk_n Device_Clk90_in_namp DDR_Clk90_in_n

Note 2 An additional BUFG is used for the MCH_OPB_Clk in this configuration

Note 3 A total of 5 BUFGs are used in this configuration

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

DDR2 SDRAM Clock Input SynchronizationFor design implementations other than Virtex-4 a DCM is required for the DDR feedback clock DDR_Clk_FB The DCM on the feedback clock is used to create a clock pair that is center aligned with the DQ signals during a read cycle The DDR_Clk output shown in Figure 18 will need to be connected to the DDR_Clk_fb shown in Figure 19 as an external board connec-tion The CLK90 output of the DDR_Clk_FB DCM is used by the MCH OPB DDR2 SDRAM core to register the data (DQ) during a read cycle

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

Note 1 This clocking configuration uses global clock inversion for the generation of Device_Clk_n Device_Clk90_in_n

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

Due to the variance in board layout and timing on the DDR_DQ amp DDR_DQS signals the phase shifting on the DDR_Clk_FB should be analyzed

Virtex-4 Clock GenerationThe clocking scheme required in the FPGA for the design implementations targeting for Virtex-4 and used by the MCH OPB DDR2 SDRAM controller are shown in Figure 20

Controller Clock InputsA DCM is required to generate the clocks used by MCH OPB DDR2 SDRAM controller as shown in Figure 18 through Figure 20 A 90 degree and 270 degree phase shifted output of the DCM is a required input to the MCH OPB DDR2 SDRAM controller core These are used to generate the DDR_ClkDDR_Clkn and DQS signals to DDR2 SDRAM The inverted clock can be derived using local inversion (to minimize BUFG system resource usage) or use direct outputs of the DCM

DDR2 Clock GenerationThe clock output to the DDR2 SDRAM is generated using the DDR IOB registers as shown in Figure 21 The Device_Clk90_in is used to generate the DDR_Clk (and DDR_Clkn) so that the clock is centered on the DQ signal to the DDR2 SDRAM

Figure 20 MCH OPB DDR2 controller - Virtex-4 Clocking

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

Note 1 An additional BUFG is used for the MCH_OPB_Clk in this configurationNote 2 A total of 5 BUFGs are used in this configuration

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Figure 21 DDR2 SDRAM Clock Generation

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

DDR2 SDRAM Controller

Device_Clk90_in_n

Note 1 Duplicated based on parameter C_NUM_CLK_PAIRS

Discontinued IP

Timing Diagrams

XCL Protocol Cacheline Write Timing Diagrams

Figure 22 shows an XCL protocol channel performing a cacheline write on 32-bit DDR2 SDRAM

Figure 22 XCL Cacheline Write Operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Data[031]

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Control

MCH_ReadData_Data[031]

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

IDLE IDLE ACT BW WTWR PC IDLE

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

RA=Row Address CA=Column AddressBA=Bank Address PC=Precharge CommandBW=Burst Write WTWR=Wait TWR

RA CA CA+1 CA+2 CA+3

Discontinued IP

XCL Protocol Cacheline Read Timing Diagrams

Figure 23 shows an XCL protocol channel performing a cacheline read on 32-bit DDR2 SDRAM

Figure 23 XCL Cacheline Read Operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

IDLE IDLE ACT BR PC IDLE

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

RA=Row Address CA=Column Address BA=Bank Address PC=Precharge BR=Burst Read

Discontinued IP

XCL Protocol Single Write Timing Diagrams

Figure 24 shows an XCL protocol channel performing a single write on 32-bit DDR2 SDRAM

Figure 24 XCL Single Write Operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

IDLE IDLE ACT SW WTwr PC IDLE

0000 1FFF

RA(x)=Row Address CA(x)=Column Address BA(x)=Bank AddressPC=Precharge Command BW=Burst Write Command WTwr=Wait TWR Command

RA(A0) CA(A0)

Discontinued IP

XCL Protocol Single Read Timing Diagrams

Figure 25 shows an XCL protocol channel performing a single read on 32-bit DDR2 SDRAM

Figure 25 XCL Single Read Operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

IDLE IDLE ACT SR PC IDLE

RA=Row Address CA=Column AddressBA=Bank Address PC=PrechargeSR=Single Read

RA(A0) CA(A0)

Discontinued IP

OPB Burst Write Timing DiagramsFigure 26 shows an OPB burst write operation on 32-bit DDR2 SDRAM

Figure 26 OPB Burst Write operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

RA=Row Address CA=Column AddressBA=Bank Address PC=PrechargeBW=Burst Write WTWR=Wait TWR

CA+2 CA+3CA+1CARA

Discontinued IP

Figure 27 shows an OPB burst write operation on 16-bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

IDLE IDLE ACT BW WTwr PC IDLE

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

RA=Row Address CA=Column AddressBA=Bank Address PC=PrechargeBW=Burst Write WTwr=Wait TWR

CA+6 CA+4 CA+2 CA RA

Discontinued IP

OPB Burst Read Timing DiagramsFigure 28 shows an OPB burst read operation on 32-bit DDR2 SDRAM

Figure 28 OPB Burst Read operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

RA=Row Address CA=Column AddressBA=Bank Address PC=PrechargeBR=Burst Read

Discontinued IP

Figure 29 shows an OPB burst read operation on 16-bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

OPB Single Write Timing DiagramsFigure 30 shows an OPB single write operation on 32-bit DDR2 SDRAM

Figure 30 OPB Single Write operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

IDLE IDLE ACT SW WTWR PC IDLE

0000 1FFF

0 F0F0

RA=Row Address CA=Column AddressBA=Bank Address PC=PrechargeSW=Single Write WTWR=Wait TWR

Discontinued IP

OPB Single Read Timing DiagramsFigure 31 shows an OPB single read operation on 32-bit DDR2 SDRAM

Design ConstraintsNote An example UCF for this core is available and must be modified for use in the system Please refer to the EDK Getting Started Guide for the location of this file

Timing ConstraintsFor complete timing coverage all clock inputs to the FPGA should be assigned a timing constraint Using any of the recom-mended DCM configurations (for design implementations other than Virtex4) shown in Figure 18 on page 32 or Figure 19 on page 33 the ISE tools will derive all proper timing constraints for the DDR2 core For design implementations other than Vir-tex-4 a timing constraint should be placed on the system clock input as well as the DDR clock feedback An example for run-ning the MCH and OPB at 100 MHz and the DDR2 clock at 133 MHz is shown in Figure 32

Figure 31 OPB Single Read operation With 32-Bit DDR2 SDRAM

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

For Virtex-4 design implementations using the recommended DCM setup shown in Figure 20 on page 34 only the external clock inputs are required to be assigned a timing constraint An example for a Virtex-4 implementation is shown in Figure 33where the MCH OPB clock is running at 100 MHz and the DDR2 clock frequency is 133 MHz

Pin ConstraintsThe DDR2 SDRAM IO should be set to the SSTL18 IO standard If external pullupspulldowns are not available on the DDR2 SDRAM DQ and DQS signals then these pins should be specified to use pullup or pulldown resistors Pulldown resis-tors are preferred An example is shown in Figure 34

IDELAY ConstraintsFor Virtex-4 design implementations the use of the IDELAY in the IOB modules is required With using any IDELAY compo-nents within the FPGA an IDELAYCTRL module is necessary The IDELAYCTRL module provides the necessary tap incre-ments for each IDELAY module to which it is associated

In the ISE tools if only one IDELAYCTRL module is instantiated and the DDR2 SDRAM signal pin assignments are across multiple clock regions the tools will replicate the IDELAYCTRL module To prevent the tools from duplicating the IDELAYC-TRL to all locations on the FPGA the user must specify how many IDELAYCTRL modules are needed This is specified with

NET MCH_OPB_Clk TNM_NET = MCH_OPB_ClkTIMESPEC TS_MCH_OPB_Clk = PERIOD MCH_OPB_Clk 10 ns HIGH 50

NET Device_Clk TNM_NET = Device_ClkTIMESPEC TS_Device_Clk = PERIOD Device_Clk 75 ns HIGH 50

NET DDR_Clk_fb TNM_NET = DDR_Clk_fbTIMESPEC TS_DDR_Clk_fb = PERIOD DDR_Clk_fb 75 ns HIGH 50

Figure 32 Non Virtex-4 Timing Constraints

NET Clk_200 TNM_NET = Clk_200TIMESPEC TS_Clk_200 = PERIOD Clk_200 5 ns HIGH 50

Figure 33 DDR2 Timing Constraints for Virtex4

NET DDR_Clk IOSTANDARD = SSTL18_INET DDR_Clkn IOSTANDARD = SSTL18_INET DDR_CKE IOSTANDARD = SSTL18_INET DDR_CSn IOSTANDARD = SSTL18_INET DDR_RASn IOSTANDARD = SSTL18_INET DDR_CASn IOSTANDARD = SSTL18_INET DDR_WEn IOSTANDARD = SSTL18_INET DDR_DMltgt IOSTANDARD = SSTL18_INET DDR_BankAddrltgt IOSTANDARD = SSTL18_INET DDR_Addrltgt IOSTANDARD = SSTL18_INET DDR_DQltgt IOSTANDARD = SSTL18_IINET DDR_DQSltgt IOSTANDARD = SSTL18_IINET DDR_DQSnltgt IOSTANDARD = SSTL18_IINET DDR_ODT IOSTANDARD = SSTL18_I

Figure 34 MCH OPB DDR2 SDRAM Controllerrsquos Pin Constraints

Discontinued IP

the C_NUM_IDELAYCTRL design parameter It is the responsibility of the designer to location constrain each IDELAYCTRL based on the clock regions where IOB DDR2 SDRAM IOB signals reside

For instance if C_NUM_IDELAYCTRL = 4 then the user must add UCF constraints to location constrain these modules as shown in Figure 35

Design Implementation

Target TechnologyThe intended target technology is Spartan-3 Virtex-II Pro and Virtex-4 family FPGAs

Device Utilization and Performance BenchmarksThe MCH OPB DDR2 SDRAM controller is a module that will be used with other design pieces in the FPGA the utilization and timing numbers reported in this section are estimates As the MCH OPB DDR2 SDRAM controller is combined with other pieces of the FPGA design the utilization of FPGA resources and timing of the MCH OPB DDR2 SDRAM controller design will vary from the results reported here The MCH OPB DDR2 SDRAM controller benchmarks are shown in Table 13 Table 14 and Table 15 for a Spartan-3 (xc3s2000) Virtex-II Pro (xc2vp20) and Virtex-4 (xc4vlx40) FPGAs

INST mch_opb_ddr2_0IDELAYCTRL_I0 LOC=IDELAYCTRL_XnYm INST mch_opb_ddr2_0IDELAYCTRL_I1 LOC=IDELAYCTRL_XnYm INST mch_opb_ddr2_0IDELAYCTRL_I2 LOC=IDELAYCTRL_XnYm INST mch_opb_ddr2_0IDELAYCTRL_I3 LOC=IDELAYCTRL_XnYm

Figure 35 Virtex-4 IDELAY Constraints

Discontinued IP

Table 13 Performance and Resource Utilization (Spartan-3)

Parameter Values Device Resources PerformanceC

Slices Slice FFs4-input LUTs

MCH OPB Clock Fmax (MHz)

DDR2 Device Clock Fmax (MHz)

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

Table 14 Performance and Resource Utilization Benchmarks (Virtex-II Pro)

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

Table 15 Performance and Resource Utilization Benchmarks (Virtex-4)

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

Specification Exceptions1 Additive latency feature of DDR2 SDRAM memory is not supported Additive latency of DDR2 memories is set to zero

which causes read latencies of DDR2 SDRAM memory is same as its CAS latency

2 Off Chip Driver (OCD) calibration of DDR2 SDRAM memory is not supported

Reference DocumentsThe following documents contain reference information important to understanding the MCH OPB DDR2 SDRAM Controller design

1 MicroBlaze Processor Reference Guide UG081

2 MCH OPB IPIF Specification DS494

3 JEDECrsquos DDR2 SDRAM specification JESD79-2A

4 OPB IPIF Specification DS414

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Table 15 Performance and Resource Utilization Benchmarks (Virtex-4) (Continued)

Discontinued IP

5 PLB DDR2 SDRAM Specification DS326

6 MCH OPB DDR Specification DS496

Revision History

Date Version Revision Ed

122105 10 Initial release PK

031706 11 Updated document with resource utilization and performance table

032006 12 Updated the document with timing diagrams bsbDiscontinued IP

Introduction

Features

MCH OPB DDR2 SDRAM Controller Design Parameters

Allowable Parameter Combinations

Optimal MCH Parameter Settings

MCH OPB DDR2 SDRAM Controller IO Signals

Parameter-Port Dependencies


Big-Endian Memory Data Types and Organization

Memory to MCH OPB DDR2 SDRAM Controller Connections

Example 1 32-bit Connection



MCH OPB DDR2 SDRAM Controller Design

Self Refresh

Init State Machine

Command State Machine

Data State Machine

Write Async FIFO and FIFO Read Control

Tap Control and Data Tap Increment

IO Registers

Control Signals

Write Data

Read Data (Non Virtex-4 Implementation)

Read Data (Virtex-4 Implementation)

Read Data Path Logic

Multiple Data Width

On Die Termination (ODT)

Differential DQS

DDR2 Clocking

MCH OPB DDR2 SDRAM Clocking

Non Virtex-4 Clock Generation

DDR2 SDRAM Clock Input Synchronization

Virtex-4 Clock Generation

Controller Clock Inputs

DDR2 Clock Generation

Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology

Device Utilization and Performance Benchmarks

Specification Exceptions

Reference Documents

Revision History

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ltFEFF004f007000740069006f006e00730020007000650072006d0065007400740061006e007400200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000500044004600200064006f007400e900730020006400270075006e00650020007200e90073006f006c007500740069006f006e002000e9006c0065007600e9006500200070006f0075007200200075006e00650020007100750061006c0069007400e90020006400270069006d007000720065007300730069006f006e00200061006d00e9006c0069006f007200e90065002e00200049006c002000650073007400200070006f0073007300690062006c0065002000640027006f00750076007200690072002000630065007300200064006f00630075006d0065006e007400730020005000440046002000640061006e00730020004100630072006f0062006100740020006500740020005200650061006400650072002c002000760065007200730069006f006e002000200035002e00300020006f007500200075006c007400e9007200690065007500720065002egt ENU (Use these settings to create PDF documents with higher image resolution for improved printing quality The PDF documents can be opened with Acrobat and Reader 50 and later) JPN ltFEFF3053306e8a2d5b9a306f30019ad889e350cf5ea6753b50cf3092542b308000200050004400460020658766f830924f5c62103059308b3068304d306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e305930023053306e8a2d5b9a30674f5c62103057305f00200050004400460020658766f8306f0020004100630072006f0062006100740020304a30883073002000520065006100640065007200200035002e003000204ee5964d30678868793a3067304d307e30593002gt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e0020005000440046002d0044006f006b0075006d0065006e00740065006e0020006d00690074002000650069006e006500720020006800f60068006500720065006e002000420069006c0064006100750066006c00f600730075006e0067002c00200075006d002000650069006e0065002000760065007200620065007300730065007200740065002000420069006c0064007100750061006c0069007400e400740020007a0075002000650072007a00690065006c0065006e002e00200044006900650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f0062006100740020006f0064006500720020006d00690074002000640065006d002000520065006100640065007200200035002e003000200075006e00640020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt PTB ltFEFF005500740069006c0069007a006500200065007300740061007300200063006f006e00660069006700750072006100e700f5006500730020007000610072006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000500044004600200063006f006d00200075006d00610020007200650073006f006c007500e700e3006f00200064006500200069006d006100670065006d0020007300750070006500720069006f0072002000700061007200610020006f006200740065007200200075006d00610020007100750061006c0069006400610064006500200064006500200069006d0070007200650073007300e3006f0020006d0065006c0068006f0072002e0020004f007300200064006f00630075006d0065006e0074006f0073002000500044004600200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002c002000520065006100640065007200200035002e0030002000650020007300750070006500720069006f0072002egt DAN ltFEFF004200720075006700200064006900730073006500200069006e0064007300740069006c006c0069006e006700650072002000740069006c0020006100740020006f0070007200650074007400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006d006500640020006800f8006a006500720065002000620069006c006c00650064006f0070006c00f80073006e0069006e006700200066006f00720020006100740020006600e50020006200650064007200650020007500640073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e006500730020006d006500640020004100630072006f0062006100740020006f0067002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt NLD ltFEFF004700650062007200750069006b002000640065007a006500200069006e007300740065006c006c0069006e00670065006e0020006f006d0020005000440046002d0064006f00630075006d0065006e00740065006e0020007400650020006d0061006b0065006e0020006d00650074002000650065006e00200068006f0067006500720065002000610066006200650065006c00640069006e00670073007200650073006f006c007500740069006500200076006f006f0072002000650065006e0020006200650074006500720065002000610066006400720075006b006b00770061006c00690074006500690074002e0020004400650020005000440046002d0064006f00630075006d0065006e00740065006e0020006b0075006e006e0065006e00200077006f007200640065006e002000670065006f00700065006e00640020006d006500740020004100630072006f00620061007400200065006e002000520065006100640065007200200035002e003000200065006e00200068006f006700650072002egt ESP ltFEFF0055007300650020006500730074006100730020006f007000630069006f006e006500730020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000500044004600200063006f006e0020006d00610079006f00720020007200650073006f006c00750063006900f3006e00200064006500200069006d006100670065006e00200070006100720061002000610075006d0065006e0074006100720020006c0061002000630061006c006900640061006400200061006c00200069006d007000720069006d00690072002e0020004c006f007300200064006f00630075006d0065006e0074006f00730020005000440046002000730065002000700075006500640065006e00200061006200720069007200200063006f006e0020004100630072006f00620061007400200079002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004e00e4006900640065006e002000610073006500740075007300740065006e0020006100760075006c006c006100200076006f0069006400610061006e0020006c0075006f006400610020005000440046002d0061007300690061006b00690072006a006f006a0061002c0020006a006f006900640065006e002000740075006c006f0073007400750073006c00610061007400750020006f006e0020006b006f0072006b006500610020006a00610020006b007500760061006e0020007400610072006b006b007500750073002000730075007500720069002e0020005000440046002d0061007300690061006b00690072006a0061007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f006200610074002d0020006a00610020004100630072006f006200610074002000520065006100640065007200200035002e00300020002d006f0068006a0065006c006d0061006c006c0061002000740061006900200075007500640065006d006d0061006c006c0061002000760065007200730069006f006c006c0061002egt ITA ltFEFF00550073006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000500044004600200063006f006e00200075006e00610020007200690073006f006c0075007a0069006f006e00650020006d0061006700670069006f00720065002000700065007200200075006e00610020007100750061006c0069007400e00020006400690020007300740061006d007000610020006d00690067006c0069006f00720065002e0020004900200064006f00630075006d0065006e00740069002000500044004600200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f00700070007200650074007400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006d006500640020006800f80079006500720065002000620069006c00640065006f00700070006c00f80073006e0069006e006700200066006f00720020006200650064007200650020007500740073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e006500730020006d006500640020004100630072006f0062006100740020006f0067002000520065006100640065007200200035002e00300020006f0067002000730065006e006500720065002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006e00e40072002000640075002000760069006c006c00200073006b0061007000610020005000440046002d0064006f006b0075006d0065006e00740020006d006500640020006800f6006700720065002000620069006c0064007500700070006c00f60073006e0069006e00670020006f006300680020006400e40072006d006500640020006600e50020006200e400740074007200650020007500740073006b00720069006600740073006b00760061006c0069007400650074002e0020005000440046002d0064006f006b0075006d0065006e00740065006e0020006b0061006e002000f600700070006e006100730020006d006500640020004100630072006f0062006100740020006f00630068002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006100720065002egt KOR ltFEFFd5a5c0c1b41c0020c778c1c40020d488c9c8c7440020c5bbae300020c704d5740020ace0d574c0c1b3c4c7580020c774bbf8c9c0b97c0020c0acc6a9d558c5ec00200050004400460020bb38c11cb97c0020b9ccb4e4b824ba740020c7740020c124c815c7440020c0acc6a9d558c2edc2dcc624002e0020c7740020c124c815c7440020c0acc6a9d558c5ec0020b9ccb4e000200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt CHS ltFEFF4f7f75288fd94e9b8bbe7f6e521b5efa76840020005000440046002065876863ff0c5c065305542b66f49ad8768456fe50cf52068fa87387ff0c4ee563d09ad8625353708d2891cf30028be5002000500044004600206587686353ef4ee54f7f752800200020004100630072006f00620061007400204e0e002000520065006100640065007200200035002e00300020548c66f49ad87248672c62535f003002gt CHT ltFEFF4f7f752890194e9b8a2d5b9a5efa7acb76840020005000440046002065874ef65305542b8f039ad876845f7150cf89e367905ea6ff0c4fbf65bc63d066075217537054c18cea3002005000440046002065874ef653ef4ee54f7f75280020004100630072006f0062006100740020548c002000520065006100640065007200200035002e0030002053ca66f465b07248672c4f86958b555f3002gt gtgtgtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice

MCH OPB DDR2 SDRAM Controller Design ParametersTo allow the user to create a MCH OPB DDR2 SDRAM controller that is uniquely tailored for the system certain features are parameterizable in the MCH OPB DDR2 SDRAM controller design This allows the user to have a design that only utilizes the resources required by the system and runs at the best possible performance The features that are parameterizable in the MCH OPB DDR2 SDRAM controller are shown in Table 1

Table 1 MCH OPB DDR2 SDRAM Controller Design Parameters

VHDL Type

MCH OPB DDR2 SDRAM Controller Features

G1 Target FPGA family C_FAMILY virtex2p spartan3 virtex4

virtex2p string

G2 Include support for registered DIMM

C_REG_DIMM 0 = DDR2 device is not registered DIMM

1 = DDR2 device is registered DIMM

0 integer

G3 Include logic to create extra setup time on DDR2 address and control signals[1]

C_EXTRA_TSU 0 = Donrsquot include logic to support extra setup time

1 = Include logic to support extra setup time

0 integer

G4 Supported number of external DDR2 SDRAM memory banks[2]

C_NUM_BANKS_MEM 1 - 4 1 integer

G5 Number of generated clock pairs supplied to the DDR2 memory

C_NUM_CLK_PAIRS 1 - 4 1 integer

G6 Include logic to support asynchronous DDR2 SDRAM clock from OPB bus clock

C_DDR_ASYNC_SUPPORT 1 = Include logic to separate DDR2 SDRAM clock domain from MCHOPB clock domain

0 = Not supported

1 integer

G7 Enable differential DQS capability for DDR2 memory devices

C_DDR_ENABLE_DIFF_DQS 0 = Disable differential DQS logic

1= Enable differential DQS logic

0 integer

G8 Specify number of IDELAYCTRL modules to instantiate for Virtex-4 implementation

C_NUM_IDELAYCTRL 1 - 20 1 integer

G9 On Die Termination selection

C_DDR2_ODT_SETTING 0 75 150

0 = ODT will be disabled

75 = ODT enabled and On Die Terminating resistance (Rtt) will be 75

150 = ODT enabled and Rtt will be 150

0 integer

Discontinued IP

1 integer

0 integer

10000 15000 10000 integer

MCH Interface

0 integer

4 8 16 16 integer

0 4 8 16 16 integer

1 integer

0 integer

VHDL Type

Discontinued IP

VHDL Type

Discontinued IP

Address Space

VHDL Type

Discontinued IP

Simulation Only

integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


1 integer

0 integer

10000 15000 10000 integer

MCH Interface

0 integer

4 8 16 16 integer

0 4 8 16 16 integer

1 integer

0 integer

VHDL Type

Discontinued IP

VHDL Type

Discontinued IP

Address Space

VHDL Type

Discontinued IP

Simulation Only

integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


VHDL Type

Discontinued IP

Address Space

VHDL Type

Discontinued IP

Simulation Only

integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Address Space

VHDL Type

Discontinued IP

Simulation Only

integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Simulation Only

integer

VHDL Type

Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


DDR2 SDRAM Signals

Clock Signals

Discontinued IP

MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


MCH Signals[7]

Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Design Parameters

G46 C_DDR_DWIDTH P8

P11 - P19

IO Signals

Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


n n+1 n+2 n+3

0 1 2 3

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

Halfword

MSB LSB

MSBit LSBit

Byte address

Byte label

Byte significance

Bit label

Bit significance

n+1 n+2 n+3 n+4 n+5 n+6 n+7

3 4 5 6 7Double

Discontinued IP

(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


(MSBLSB)

DDR_DQ(015)

DDR_DQS(01)

DDR_DM(01)

DDR2 SDRAM

DDR_DQ(1631)

DDR_DQS(23)

DDR_DM(23)

Memory 1x16

DDR2 SDRAMMemory 2

MCH OPB DDR2

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

UDQS LDQS

UDM LDM

DQ(150)

UDQS LDQS

UDM LDM

SDRAM Controller

Discontinued IP

Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Variable Equation

DDR_DQ(015)

DDR_DQS(01)

DDR_DQSn(01)

DDR2 SDRAMMemory 1

DDR_Addr(012)

DDR_BankAddr(01)

DQ(150)

DQS(10)

DQSn(10)

DM(10)DDR_DM(01)

Discontinued IP

32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


32 - (9 + 1) = 22

Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Write AsyncFIFO

MCH_OPB_Clk

Clock Generator

ClkClk_n

Clk90 Clk90_n

DDR_Clk

DDR_Clk_n

Device_Clk

Device_Clk_n2

Device_Clk90_in

Device_Clk90_in_n2

DDR_Clk90_in2

DDR_Clk90_in_n2

Sys_Clk

counters

Init State

Machine

Command State

Machine

Data State

Machine

Read Data Path

DDR_ReadDQS_Rise

control signals

IDELAY Logic1

MultipleDataWidth

FIFO ReadControl

IDELAYCTRL1

Cal_Clk1

Clk_200

Data Tap Increment1

Reg Unreg

DDR_CKE

DDR_RASn

DDR_CSn

DDR_CASn

DDR_WEn

DDR_DQ_t[0n]

DDR_Addr [0n]

DDR_DQ_o[0n]

DDR_DQ_i[0n

DDR_DQSn_o[0n]

DDR_DQSn_i[0n]

DDR_DQSn_t[0n]

DDR_DQS_i [0n]

DDR_DQS_o[0n]

DDR_DQS_t[0n]

DDR_ODT

Discontinued IP

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

MCH_OPB_Clk

MCH_OPB_Rst

DDR_Sleep

DDR_Wakeup

DDR_CMD

DDR_CKE

DDR_CSn

DDR_RASn

DDR_CASn

DDR_WEn

NOPNOP RFSH

A Txsr

Discontinued IP

Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Wait 400 ns

PRECHARGE1

ISSUE EMR2

ISSUE EMR3

ENABLE_DLL

RESET_DLL

PRECHARGE2

REFRESH1

OCD_DEFAULT

OCD_EXIT

CALIB_STAGE

cmd_done cmd_done

REFRESH2 SET_OP

cmd_done

cmd_done cmd_done

cmd_donecmd_done

Virtex-4

ODT_ACTIVE

odt_count

WAIT_TXSR

REFRESH_SNG

REFRESH3

reset ddr_waakeup

txsr_end

cmd_done

Not Virtex-4

Discontinued IP

ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


ACT_CMD

LOAD_MR_CMD

REFRESH_CMD

ACT_CAL_CMD

PRECHARGE_CMD

Load_mr

Precharge

GPcnt_end

GPcnt_endCalib_rd+

Calib_Done

WAIT_TRAS

FIFO_rst_done

SINGLE_READ_CMD

BURST_READ_CMD

SINGLE_WRITE_CMD

BURST_WRITE_CMD

WrReq + Burst

Tras_min_end

Tcmd_end

Tras_min_end

RdReq + Burst

Tras_min_end

WAIT_TWR

Twr_end

Tras_min_end

Twr_end

WrReq + Burst

GPcnt_end + Trc_end

Tras_min_end

Calib_rd

Tras_min_end

RdReq + Burst

SELF_REFRESH_CMD

ddr_sleep init_done

Discontinued IP

WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


WRITE_DATAREAD_DATA

pend_write

pend_writepend_read

WAIT_CASLAT

pend_read

tcaslat_end

pend_read

pend_writepend_read

WRITE_DATA

twr_end

Discontinued IP

Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Command FIFO

FIFORead Control

Device_Clk

FIFO_Empty

Device_Clk

Data FIFO

FIFO_Empty

data_fifo_read_en

Device_Clk

IO REG MODULE

DDR_dq_oe_cmb

MCH_OPB_Clkwr_clk

data_fifo_wr_en

MCH_OPB_Clkwr_clk

DDR_dq_oe_cmb

rd_clk

emptycmd_fifo_wr_en

IO REG MODULE

Discontinued IP

IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


IO Registers

Discontinued IP

CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CDevice_Clk

Write_data_en

DDR_DQ_t [i]1

DDR_DQ_o [i]1

DDR_DQS_t [i]1

DDR_DQS_o[i]1

Write_dqs_en

Device_Clk90

Device_Clk

Device_Clk_n

Device_Clk90_n

DDR_DQSn_t [i]1

DDR_DQSn_o[i]1

Write_dqsn_en

Device_Clk90

Device_Clk90_n

Discontinued IP

Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Q0DDR_RdData_high

DDR_Clk90_in

DDR_DQ_i[i]1

DDR_RdDQS

DDR_DQS_i[i]1

ddr_read_data_en

read_data_en

DDR_Clk90_in

DDR_Clk90_in_n

DDR_RdDQSn

DDR_DQSn_i[i]1

ddr_read_dqs_ce DQ

read_dqs_ce

DDR_Clk90_in

Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Read_dataDIN

EMPTYCLR

Bus_Clk

DDR_ReadData

fifo_wren

Clk_ddr_rddata

fifo_empty

RdenRdAck

Read_data_en

Read_data

fifo_rden

MCH_OPB_Clk

fifo_empty

fifo_wr_data

fifo_wren

Device_Clk

DQS_Cal_Rise

fifo_wren_rise

fifo_wren_fall

fifo_wr_data_rise

fifo_wr_data_fall0

Device_Clk

Discontinued IP

MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


MCH OPB DDR2

150 Ω

DDR2 SDRAM

Rtt ( eff ) = 75Ω

MCH OPB DDR2

300 Ω

Rtt ( eff ) = 150Ω

DDR_DM [0n]

DDR2 SDRAM

Discontinued IP

DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


DDR2 Clocking

15000 ps (66 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 7500 ps (133 MHz)

10000 ps (100 MHz) 5000 ps (200 MHz)

tAONDtAOFD

Discontinued IP

CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CLK90External

DDR2 SDRAM

DDR_Clk90_in

DDR_Clk

CLK CLKn DDR_Clkn

DDR_Clk90_in_n

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

ControllerSDRAM

Discontinued IP

CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CLK90External

DDR2 SDRAM

FPGAMCH OPB DDR2

DDR_Clk90_in

DDR_Clk

DDR_Clkn

Device_Clk

Device_Clk_n

Device_Clk90_in

Device_Clk90_in_n

DDR_Clk90_in_n

CLK180

CLK270

MCH_OPB_Clk

System Clk

DDR2 Device

amp DDR_Clk90_in_n

SDRAM Controller

CLK CLKn

Discontinued IP

CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CLK90External

Cal_Clk

DDR_Clk

DDR_ClknClock

Device_Clk

Device_Clk90_in

MCH_OPB_Clk

System Clk

DDR2 Device

MCH OPB DDR2

Controller

200 MHz ClkSDRAM

IDELAYCTRL

Clk_200

Discontinued IP

Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Device_Clk90_in

DDR_Clk[i](1)

DDR_Clkn[i](1)

Device_Clk90_in_n

Discontinued IP

Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Timing Diagrams

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

MCH_Access_Control

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

A0 D0 D1 D2 D3

0000 0000 0000 1FFF

F 0 F 0 F 0 F 0 F

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

D0 D1 D2 D3

0 F0F0 F 0 0 F 0 F0F0F 0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_Access_Full

MCH_ReadData_Read

MCH_ReadData_Exists

DDR_Clk90n

DDR_Clk

DDR_CKE

DDR_CSn

Command

MCH_OPB_CLK

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

0000 1FFF

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

MCH_Access_Write

MCH_Access_Control

MCH_ReadData_Exists

MCH_ReadData_Read

MCH_Access_Full

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132

RA(A0) CA(A0)

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 38 39

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

F F F F F

D0 D1 D2 D3

0F0 F0 0 0 0

CA+2 CA+3CA+1CARA

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

1 2 3 4 5 6 7 8 9 10 1112 1314 1516 17 1819 2021 2223 24 2526 2728 2930 3132 33 3435 3637 3839

A0 A1 A2 A3

D0 D1 D2 D3

0000 0000 0000 0000 1FFF

3 0 3 0 3 0 3 0 F

D0 D1 D2 D3

03 0 3 0 03 3 0 3 3 03 3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

A0 A0 A1 A2 A3

D0 D1 D2 D3

0 F0F0 0 0 0 F 0 0 0 0 0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_Dbus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[01]

DDR_DQ[015]

DDR_DQS[01]

2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

A0 A1 A2 A

D0 D1 D2

IDLE IDLE ACT BR PC

0 3030 0 3 3 0 03 03 0 03 03 0

RA CA+6CA+4CA+2CA

D0 D1 D2 D3

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

00 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122 232425 262728 29

0000 1FFF

0 F0F0

Discontinued IP

CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


CYCLES

MCH_OPB_CLK

OPB_RNW

OPB_ABus[031]

OPB_BE[03]

OPB_DBus[031]

OPB_seqAddr

Sln_xferAck

DDR_Clk

DDR_CKE

DDR_CSn

Command

DDR_RASn

DDR_CASn

DDR_WEn

DDR_BankAddr[01]

DDR_Addr[012]

DDR_DM[03]

DDR_DQ[031]

DDR_DQS[03]

2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930313233

0 F0F0

Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Discontinued IP

1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

4 0 0 0 1 32 1616 1058 1829 68 133

2 1 0 0 1 32 1387 1017 1463 69 133

2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

2 1 1 0 2 32 1489 1036 1740 68 134

2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

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4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

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2 1 0 0 2 16 1309 880 1419 100 203

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2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

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1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

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2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


1 1 0 0 1 16 800 572 868 81 139

1 0 0 0 4 16 819 579 867 76 136

4 0 0 0 1 16 1465 916 1747 69 139

2 1 0 0 1 16 1304 883 1391 70 138

2 1 1 0 1 16 1353 916 1609 70 141

4 1 1 0 1 16 1705 1108 2094 69 136

2 1 1 0 2 16 1366 898 1650 69 143

2 1 0 0 2 16 1308 888 1446 69 135

4 1 1 0 4 16 1767 1122 2210 68 135

2 1 1 1 1 16 1434 972 1613 70 138

4 1 1 1 1 16 1726 1164 2098 68 136

2 1 1 1 2 16 1449 954 1654 70 137

2 1 0 1 2 16 1309 944 1450 70 134

4 1 1 1 4 16 1789 1178 2214 68 137

1 1 0 0 1 32 969 704 962 79 136

1 0 0 0 4 32 962 711 932 79 135

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2 1 1 0 1 32 1498 1215 1676 68 134

4 1 1 0 1 32 1889 1246 2218 68 135

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2 1 0 0 2 32 1439 1021 1505 68 134

4 1 1 0 4 32 1939 1268 2322 68 135

2 1 1 1 1 32 1537 1167 1680 68 136

4 1 1 1 1 32 1975 1367 2222 67 141

2 1 1 1 2 32 1617 1155 1744 69 136

Discontinued IP

2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

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4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


2 1 0 1 2 32 1531 1140 1509 69 134

4 1 1 1 4 32 2032 1382 2327 68 137

1 1 0 0 1 64 1366 1048 1230 81 137

1 0 0 0 4 64 1348 1048 1208 80 136

4 0 0 0 1 64 1934 1384 2094 68 140

2 1 0 0 1 64 1864 1361 1766 69 137

2 1 1 0 1 64 1947 1395 1964 67 136

4 1 1 0 1 64 2299 1589 2470 67 134

2 1 1 0 2 64 1893 1377 2002 68 135

2 1 0 0 2 64 1796 1359 17777 67 134

4 1 1 0 4 64 2382 1603 2585 68 136

2 1 1 1 1 64 2113 1603 1968 68 136

4 1 1 1 1 64 2481 1794 2474 67 135

2 1 1 1 2 64 2139 1585 2006 69 134

2 1 0 1 2 64 2065 1587 1781 68 135

4 1 1 1 4 64 2538 1811 2590 68 134

Discontinued IP

1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


1 1 0 0 1 16 767 579 822 101 203

1 0 0 0 4 16 783 588 876 102 202

4 0 0 0 1 16 1400 918 1750 100 203

2 1 0 0 1 16 1290 876 1362 101 204

2 1 1 0 1 16 1350 908 1573 100 204

4 1 1 0 1 16 1707 1129 2109 100 202

2 1 1 0 2 16 1328 899 1617 100 204

2 1 0 0 2 16 1309 880 1419 100 203

4 1 1 0 4 16 1678 1137 2236 100 200

2 1 1 1 1 16 1426 966 1577 100 202

4 1 1 1 1 16 1742 1186 2113 100 202

2 1 1 1 2 16 1378 956 1622 100 202

2 1 0 1 2 16 1260 937 1423 100 201

4 1 1 1 4 16 1749 1194 2240 100 200

1 1 0 0 1 32 1007 722 952 100 204

1 0 0 0 4 32 945 727 946 100 204

4 0 0 0 1 32 1575 1048 1809 100 203

2 1 0 0 1 32 1223 1006 1443 100 205

2 1 1 0 1 32 1483 1042 1648 100 204

4 1 1 0 1 32 1768 1261 2186 100 202

2 1 1 0 2 32 1411 1033 1680 100 202

2 1 0 0 2 32 1393 1010 1488 100 202

4 1 1 0 4 32 1886 1274 2318 100 200

2 1 1 1 1 32 1548 1164 1652 100 200

4 1 1 1 1 32 1782 1383 2190 100 200

2 1 1 1 2 32 1587 1160 1689 100 200

Discontinued IP

2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


2 1 0 1 2 32 1449 1130 1492 100 204

4 1 1 1 4 32 1959 1382 2314 100 200

1 1 0 0 1 64 1305 1044 1190 100 200

1 0 0 0 4 64 1305 1056 1193 100 200

4 0 0 0 1 64 1815 1365 2061 100 201

2 1 0 0 1 64 1662 1328 1686 100 202

2 1 1 0 1 64 1750 1369 1920 100 202

4 1 1 0 1 64 2114 1589 2445 100 200

2 1 1 0 2 64 1787 1589 1978 100 200

2 1 0 0 2 64 1730 1341 1770 101 200

4 1 1 0 4 64 2198 1591 2547 100 202

2 1 1 1 1 64 1949 1577 1924 100 202

4 1 1 1 1 64 2281 1797 2449 100 203

2 1 1 1 2 64 1867 1571 1982 100 204

2 1 0 1 2 64 1876 1549 1774 100 202

4 1 1 1 4 64 2375 1821 2603 100 200

Discontinued IP

1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


1 1 0 0 1 16 1054 893 1190 127 226

1 0 0 0 4 16 1134 901 1204 116 216

4 0 0 0 1 16 1714 1237 2059 101 209

2 1 0 0 1 16 1594 1193 1702 107 229

2 1 1 0 1 16 1624 1217 1925 105 206

4 1 1 0 1 16 2104 1433 2454 101 207

2 1 1 0 2 16 1756 1213 1978 105 214

2 1 0 0 2 16 1670 1207 1766 102 213

4 1 1 0 4 16 2143 1450 2588 101 205

2 1 1 1 1 16 1744 1275 1931 106 203

4 1 1 1 1 16 2024 1491 2460 103 206

2 1 1 1 2 16 1847 1271 1984 104 203

2 1 0 1 2 16 1671 1265 1732 103 204

4 1 1 1 4 16 2114 1508 2594 102 203

1 1 0 0 1 32 1599 1270 1552 114 203

1 0 0 0 4 32 1513 1276 1579 126 202

4 0 0 0 1 32 2122 1607 2448 107 203

2 1 0 0 1 32 2016 1570 2068 103 204

2 1 1 0 1 32 2110 1600 2285 101 205

4 1 1 0 1 32 2532 1820 2833 102 211

2 1 1 0 2 32 2019 1590 2331 102 200

2 1 0 0 2 32 1911 1586 2118 105 206

4 1 1 0 4 32 2354 1621 2964 101 209

2 1 1 1 1 32 2032 1703 2295 106 212

4 1 1 1 1 32 2641 1923 2843 101 205

2 1 1 1 2 32 2262 1695 2341 102 202

Discontinued IP

2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


2 1 0 1 2 32 2205 1691 2128 106 201

4 1 1 1 4 32 2506 1935 2974 101 223

1 1 0 0 1 64 2302 2165 2442 108 205

1 0 0 0 4 64 2256 2171 2467 121 202

4 0 0 0 1 64 2941 2511 3328 102 203

2 1 0 0 1 64 2742 2467 2954 104 201

2 1 1 0 1 64 3171 2500 3179 102 208

4 1 1 0 1 64 3301 2717 3739 101 209

2 1 1 0 2 64 2850 2485 3225 102 202

2 1 0 0 2 64 2790 2485 3014 102 205

4 1 1 0 4 64 3223 2727 3844 102 206

2 1 1 1 1 64 3054 2723 3197 105 206

4 1 1 1 1 64 3558 2940 3757 102 203

2 1 1 1 2 64 3110 2708 3243 103 203

2 1 0 1 2 64 2911 2708 3032 105 208

4 1 1 1 4 64 3446 2949 3843 103 201

Discontinued IP

Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History


Revision History

Introduction

Features













Self Refresh

Init State Machine


Data State Machine



IO Registers

Control Signals

Write Data




Multiple Data Width


Differential DQS

DDR2 Clocking







Timing Diagrams







Design Constraints

Timing Constraints

Pin Constraints

IDELAY Constraints


Target Technology



Reference Documents

Revision History
