© 2010 Altera Corporation—Public

DSP Innovations in 28-nm FPGAs

Danny BiranSenior VP of Marketing

© 2010 Altera Corporation—Public

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Ever-Increasing Bandwidth…

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….Demands ever-increasing processing performance

© 2010 Altera Corporation—Public

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High bandwidth I/O High-speed transceivers up to 28-Gbps

(total 1.6 Tbps) Up to 7 x 72-bit 1,600 Mbps DDR3 interfaces

High performance core More than 1M logic elements More than 50 Mb of RAM High-performance, variable-precision DSP with up to

3,680 18 x 18 multipliers (1,840 GMACS) Application-targeted hard IP

Power and cost 3rd Generation Programmable Power Technology HardCopy V ASIC provides risk-free path to ASIC

New capabilities Embedded HardCopy Blocks Partial reconfiguration

Stratix V FPGAs – “More Than Moore”

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Increasing Processing with Strict Power and Cost Budgets

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Processing

Price/Power

Time

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Video Processing

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Standard Definition 0.4M pixels per frame

9 x 9 precision

High Definition (1080p)2M pixels per frame

9 x 9 → 12 x 12 precision

4K Resolution ~10M pixels per frame

9 x 9 → 18 x 18 precision

DSP performance 25X pixels processed per frame

© 2010 Altera Corporation—Public

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Wireless Evolution

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Single antenna5 MHz, 1 carrier

18 x 18 precision

10 Mbps 100 Mbps 1,000 Mbps

2 x 2 MIMO20 MHz, 1 carrier18 x 18 precision

4x4 MIMO20-50 MHz, 5 carrier

18 x 18 → 27 x 27 precision

3G LTE LTE Advanced

DSP performance 200X (multiple carriers, multiple antennae)

© 2010 Altera Corporation—Public

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Military Radar

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Ground mapping and see-thru wall radars

Limited Target Detection

Simultaneous multiple target detection

1000s of transmit-receive modules

100s of sub-channels

DSP performance → 100X (multiple targets and transmit-receive modules)

Up to Floating-Point Precision

18x18 precision

© 2010 Altera Corporation—Public

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Today’s FPGA DSP Technology Does NOT Scale

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Video Surveillance

BroadcastSystems

Wireless Basestations

Medical Imaging

Military Radar

High-PerformanceComputing

100 GMAC/s

9-bit PrecisionTERA FLOPs

Floating-Point Precision

Fixed-precision DSP architecture can not meet increasing performance needs within

cost and power budgets

© 2010 Altera Corporation—Public

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Set the precision dial to match your application

Industry’s First Variable-Precision DSP Block

© 2010 Altera Corporation—Public

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New Levels of DSP FPGA Performance

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1,840 GMACS or 1,000 GFLOPS

performance in a single device

FPGA Industry Firsts

Integrated coefficient registers 64-bit cascade and adder to implement higher precision data-paths Efficient support for floating-point DSP

High-Precision Mode 18-bit Precision Mode

© 2010 Altera Corporation—Public

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Variable-Precision DSP AdvantagePrice and Power

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Video Processing Wireless Basestations Military Radar

FixedPrecision

⅓ DSP Resources

½ DSP Resources

½ DSP Resources

VariablePrecision

FixedPrecision

VariablePrecision

VariablePrecision

FixedPrecision

© 2010 Altera Corporation—Public

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Total DSP Portfolio

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DSP BlockArchitecture

TotalDSP Solutions

Video DesignFramework

DSP BuilderTiming-Driven

Simulink Synthesis

ComprehensiveFloating-Point IP

© 2010 Altera Corporation—Public

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Altera Video Design Framework

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Higher designer productivity = Faster time to market

© 2010 Altera Corporation—Public

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Altera Video Design FrameworkCustomer Application

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Video Wall

Over 100 active customers to date

Altera Video Framework Function

Image: Apantac LLC.

Color Space Conversion

CRS and Color Space Conversion

CRS and Color Space Conversion

Motion-Adaptive Deinterlacing

Clipping

ProprietaryVideo Processing

Clipping

Scaling

Scaling

Color Space Conversion + CRS

Color Space Conversion + CRS

Test Pattern Generation

Motion-Adaptive Deinterlacing

Video Mixer

CompositeImageClipping

Video 1

Video 2

Video 3

Video 4

© 2010 Altera Corporation—Public

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DSP Builder Advanced Blockset (DSPB-AB)

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HDL automatically optimized for system clock frequency and latency

© 2010 Altera Corporation—Public

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Altera’s Floating-Point Portfolio

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FFT MegaCore offers floating-point optionSine and cosine: Expected in Quartus software v.10.1

Largest portfolio of floating-point

cores

© 2010 Altera Corporation—Public

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Replacing Floating-Point Digital Signal Processors in Radar Systems

Stratix V FPGA(EP5SGSB7 )

DSP Farm*

Performance ~700 GFLOPS ~90 GFLOPS

Power ~60 W ~128 W

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* 32 floating-point digital signal processors—2.7 GFLOP/s , 4 W each

Industry’s highest floating-point processing at the lowest power

© 2010 Altera Corporation—Public

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Replacing Multicore Digital Signal Processors in a LTE Channel Card

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Stratix V FPGA (EP5SGXA3)

Multicore DigitalSignal Processors

Performance ~200 GMAC/s ~50 GMAC/s

Power ~10 to 20 W ~10 to 20 W

© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Choice of LTE Towards a FPGA-Centric Architecture

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DSP Centric FPGA Centric

© 2010 Altera Corporation—Public

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Replacing ASSPs and Digital Signal Processors in High-End Conferencing Systems

Video Design Framework

PerformanceSystem Costs

© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Summary

Expanding bandwidth demands driving need for increased processing performance

Fixed-precision DSP blocks cannot meet increasing performance needs within cost and power budgets

Altera is offering industry’s first variable-precision DSP block

Altera’s DSP solution is replacing digital signal processors and ASSPs

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