Dual Band High Efficiency Power Amplifier Based on CRLH Lines · 2010-04-10 · Dual Band High Efficiency Power Amplifier Based on CRLH Lines ... dual frequency high efficiency amplifiers

RADIOENGINEERING, VOL. 18, NO. 4, DECEMBER 2009 567

Dual Band High Efficiency Power Amplifier Based on CRLH Lines

J. L. JIMÉNEZ-MARTÍN 1, V. GONZÁLEZ-POSADAS 1, F. J. ARQUÉS 1, L. E. GARCÍA-MUÑOZ 2, D. SEGOVIA-VARGAS 2

1 DIAC, Universidad. Politécnica de Madrid, Ctra. Valencia km 7, 28031 Madrid 2DTSC. Universidad Carlos III de Madrid, Avda. Universidad 30, 28911, Leganés, Madrid

[email protected], [email protected]

Abstract. In this paper we propose the use of Composite Right/Left Hand (CRLH) and Extended Composite Right/Left Hand (ECRLH) transmission lines for the design of dual band high efficiency power amplifiers working in CE class. The harmonic termination can be synthesized using the meta-lines is particularly suitable for CE class amplifiers, which have a termination not as sensitive to the third harmonic as F class amplifier. This paper presents the design procedure and the design equations. The non-linear phase response of a CRLH and ECRLH transmis-sion line has been utilized to design arbitrary dual-band amplifiers.

Keywords Power Amplifier, Meta-materials, CE class, CRLH, ECRLH, Diplexer, Statistical Sensitivity.

1. Introduction The demand on wireless communication systems is

forcing frequency spectrum to get higher. As frequency arises two problems appear: firstly, losses in transmission lines increase quite a lot and secondly, radio-frequency (RF) solid state devices are power limited. Due to the cur-rent demand on multi-frequency systems over several wireless communication bands, systems simultaneously working at some of the following bands (GSM, TETRA, DCS, PCS, IMT-2000, WLAN, or UWB) are currently being developed and are widely used in new portable wireless handsets.

In addition to the multi-frequency performance re-quired, other critical problem is the great amount of RF power needed or the power consumption in portable de-vices (high power consumption results in large batteries and/or short battery lifetimes). For the first matter it could be thought of combining a lot of RF devices to reach the required RF power level. While, for the second matter, efficient electronics designs would maximize the device power performance. The circuit within such a device that

typically consumes most power (sometimes as much as half of the DC power supplied) is the RF power amplifier, which converts the DC power from the battery into the RF signal that is transmitted through an antenna. Maximizing the efficiency of the power amplifier can allow reducing the battery size and/or increasing the battery life or the signal strength. Furthermore, efficient amplifiers also generate less heat, increasing the device lifetime and reliability.

Then, due to the high demand of wireless services at different frequencies, the availability of multi-frequency (or at least dual frequency) high efficiency amplifiers would be welcome. Some attempts have been undertaken in order to achieve that goal. In this way, the use of switches [1], varying lumped components [2] or diplexers [3] have been proposed as potential techniques for achiev-ing dual-frequency high efficiency amplifiers.

During last years the appearance of CRLH lines [4] has opened new possibilities in the design of dual band amplifiers. Up to the authors’ knowledge only one approach using CRLH lines to design to dual band high efficiency amplifiers has been proposed [5]. However, that amplifier lacks of the harmonic termination to achieve high efficiency. This paper pays attention to the harmonic ter-minations in high efficiency amplifiers at dual frequencies to achieve efficiency as high as possible. A second attempt to achieve dual frequency high efficiency amplifiers has been proposed in [6]. A dual frequency network tries to match the fundamental and the harmonic frequencies to aim at high efficiency amplifiers. However, the study presented in this paper shows that these networks are ex-tremely sensitive to the components tolerance limiting the performance of the dual band amplifiers.

Recently, some generalizations on CRLH lines have appeared [7, 8] what could allow obtaining suitable phase conditions at three or four different frequencies. For in-stance, the extended E-CRLH lines [7] present load control at four frequencies allowing the design of a quad-band amplifier (with harmonic conditions not only to the second harmonic, but to third or fourth, or as it is shown later in this paper, dual amplifiers with load conditions to the second harmonic).

568 J.L. JIMENEZ, V. GONZALEZ, F. J. ARQUES, L. GARCIA, D. SEGOVIA, DUAL BAND HIGH EFFICIENCY POWER AMPLIFIER…

The load, bias conditions and the harmonics termina-tion to overdrive the power level for single frequency RF power amplifiers (A, B, C, D, E, or F) have been summa-rized in [9] and [10]. The choice of a class implies a trade-off between various power amplifier figures of merit, which include gain, linearity, and efficiency. In this paper the authors have studied the realization and performance of dual frequency high efficiency amplifiers. Five possible solutions using meta-lines are proposed for this goal (the first two solutions are based in the same way as the one described by Dupuy et al. [11]). We will be mainly con-cerned on CE class power amplifiers since they provide larger efficiency and low bias supply and, what is more, the fact that it is the fundamental high efficiency amplify-ing class in bipolar transistor:

a) CRLH lines at the input and output to control two fre-quencies (f1 and f2), and conventional lines to control output harmonics (2f1 and 2f2) (Fig. 1a).

b) CRLH lines at the input and output to control two fre-quencies (f1 and f2), and conventional lines mixed with CRLH lines to control output harmonics (2f1 and 2f2) (Fig. 1b).

c) CRLH lines at the input and output to control two fre-quencies (f1 and f2), and CRLH lines to control output harmonics (2f1 and 2f2) (Fig. 1c).

d) CRLH lines at the input to control two frequencies (f1 and f2), and E-CRLH lines to control output frequen-cies (f1 and f2) and their harmonics (2f1 and 2f2) (Fig. 1d).

e) CRLH diplexer both at the input and output to control two frequencies (f1 and f2) and their harmonics (Fig. 1e).

Conventional Lines

s.c. or o.c.

Amp

f1, f2

CRLH

f1, f2

CRLH

2f1, 2f2

Harmonic Loads

(a)

CRLH s.c. or o.c.

& Conventional

Lines

Amp

f1, f2

CRLH

f1, f2

CRLH

2f1, 2f2

Harmonic Loads

(b)

CRLH s.c. or o.c.

Amp

f1, f2

CRLH

f1, f2

CRLH

2f1, 2f2

Harmonic Loads

(c)

Amp

f1, f2

CRLH

f1, 2f1, f2, 2f2

E-CRLH

(d)

Amp. f1

CRLH Diplexer

Amp. f2

CRLH Diplexer

f1, f2

f1

f2

f1, f2

(e)

Fig. 1. Five solutions to implement dual band high efficiency amplifiers.

2. Composite Right/Left-Handed Transmission Line Metamaterials The concept of composite right/left-handed (CRLH)

transmission line meta-materials, introduced in [4] and extensively developed in successive papers, has been shown as a powerful tool for deep insight and efficient design of microwave devices. A CRLH meta-material is a practical transmission line meta-material structure which exhibits a left- handed (LH) band at lower frequencies and a right-handed (RH) band at higher frequencies, including a transition frequency where infinite-wavelength propaga-tion occurs under a so-called balance condition.

(a)

(b)

Fig. 2. CRLH structure: a) with lumped elements, b) with distributed and lumped elements.

Fig. 2 illustrates the equivalent circuit and its symmet-rical model implemented with CRLH transmission lines. The calculus of the network components values are ex-plained in detail in the reference [5]. A program to calcu-late the lumped element values for the design of the basic


CRLH transmission line structures in the high efficiency amplifiers has been developed. Recently the so called dual CRLH (D-CRLH) line has been developed as a tool that behaves as left-handed at higher frequencies and right-handed at lower frequencies. In this case the series-series configuration is changed by series-shunt configuration and the shunted shunt configuration by a shunted series one.

An Extended Composite Right/Left Handed transmis-sion line (E-CRLH TL) is characterized by eight LC parameters (four C-CRLH - conventional CRLH- and four D-CRLH – dual-CRLH ), which allow unprecedented diversity in the manipulation of the dispersion relation of the resulting TL structure. In particular, an E-CRLH TL meta-material, under an extended balance condition, exhibits two frequencies of infinite wavelength propaga-tion. In addition, the E-CRLH is intrinsically a quad-band (arbitrary quadruplet of frequencies) structure, to provide the appropriate harmonic impedance to dual band high efficiency amplifiers. Fig. 3 illustrates the E-CRLH. The values of the components can be calculated by using other program developing to calculate these values according to the reference [7].

Fig. 3. E-CRLH structure according to the reference [7].

3. High Efficiency Power Amplifiers One feasible solution to achieve dual frequency high

efficiency amplifiers comes from [6], where a dual network to match the impedance at the fundamental and harmonics frequencies (mainly 2nd) has been used. If this termination were not implemented, the efficiency would decrease, while if more harmonic terminations were implemented, a higher efficiency could be obtained. The 3rd and 4th har-monic impedances have low effect on the efficiency and are omitted for most practical cases. (With the exception of the class F and F inverted where termination at third harmonic is very important).

Depending on the desired class for the high efficiency amplifier, different impedances associated to the corre-sponding harmonic frequency for that class will have to be matched. The most common classes are represented in Tab. 1, which describes the theoretical maximum effi-ciency that can be achieved, and the impedances to be

presented at the fundamental frequency and second har-monic (and 3rd at class F and F inverted).

Class

Max. Output

Efficiency out

Fundamental Impedance

Zfo

2nd Harmonic Impedance

Z second harmonic

A saturated 63.5% Real S.C.

A saturated and

overexcited 80% Real S.C.

B 78.5% Real S.C.

C 100% Real S.C.

C saturated 100% Real S.C.

C_E > 90% Complex O.C.

D 100% Real S.C.

E 100% Complex O.C.

F 88% Real S.C.

( O.C. 3rd)

F-1 88% Real O.C.

( S.C. 3rd)

Tab. 1. Classes of high efficiency power amplifiers (S.C = Short Circuit, O.C. = Open Circuit).

Due to the physical characteristics of bipolar transis-tors C class amplifiers are not suitable at microwave frequencies. Similar amplifying characteristics can be achieved with CE class amplifiers. This amplifying mode has its maximum efficiency when the load impedance (at fundamental frequency) is the one given (approximately) by the equation (1) and the impedance at 2nd harmonic is an open circuit.

ob

pout

satccp C

XP

VVR

·

1;

·2·625.0

2

(1)

where Rp and Xp are the equivalent parallel impedance of load.

In any case, it should be noted that this is an approach that have to be adjusted with a load-pull analysis, (to in-clude the most significant parasitic of transistor output network and effect of overdrive). The input impedance will be the one that allows the maximum power transfer under the corresponding load conditions. The shapes of the cur-rents and voltages have been carefully described in [12]. If the quotient between previous magnitudes is calculated the


load at the different harmonic frequencies is obtained. In this case it corresponds to open circuits at the harmonic frequency of the fundamental one.

.).(·(;1

1)( 0 cofnZ

Xj

R

fZ

pp

o

(2)

4. Dual Band Class CE Power Amplifier: Solutions Description This section will provide the descriptions to

implement a dual amplifier with meta-lines as presented previously. Then:

Conventional lines are used with the architecture shown in Fig. 1a to implement the harmonic control. Traps (made with open or short circuited stubs) are implemented at 2f1 and 2f2 by means of conventional lines. This circuit can be implemented for a short cir-cuit condition instead of an open circuit one.

CRLH lines are used to implement the control har-monic in Fig. 1b. These two variants are shown in Fig. 4a and 4b. Traps are implemented at 2f1 and 2f2 by means of conventional lines and E-CRLH. In this way the output presents infinite impedance at these frequencies, working in CE class. Fig. 4 shows the schemes with open circuit. As in the previous case, depending on the configuration chosen, so will be the size of the resulting circuit.

Optimal implementation is shown in Fig. 4a; how-ever, this solution is difficult to perform because the o.c. traps must provide four performances at four fre-quencies (first and second harmonic of f1 and f2). For this reason a suitable solution is represented in Fig. 4b. For this solution, two among the four previous conditions are fulfilled while the other two only need to achieve a phase difference larger than 90º. This solution is easily implemented using CRLH lines.

90º @ 2·f2

180º @ f1

180º @ 2·f1

180º @ f2

90º @ 2·f2

180º @ f1

90º @ 2·f1

180º @ f2

180º @ 2·f2

90º @ 2·f1 Match network f1 and f2

50

CRLH

(a)

90º @ 2·f2

90º @ f1

180º @ 2·f1

90º @ f2

90º @ 2·f2

90º @ f1

90º @ 2·f1

90º @ f2

180º @ 2·f2

90º @ 2·f1 Match network f1 and f2

50

CRLH

CR

LH

CR

LH

(b)

Fig. 4. Proposed structure with conventional lines and CRLH lines for dual band CE amplifier.

Fig. 1c replaces conventional lines with CRLH lines which can present arbitrary phase conditions at two frequencies. This solution is more compact, as it is shown in Fig. 5.

90º @ 2·f2

90º @ 2·f2

90º @ 2·f1

90º @ 2·f1 Matching network at f1 and f2

50

CRLH CRLH

CR

LH

Fig. 5. Proposed structure with CRLH lines for dual band CE

amplifier.

The solution proposed in Fig. 1d is implemented with E-CRLH lines to satisfy four different output imped-ance conditions. In this solution the input network is a CRLH structure. The input impedance at the optimum desired frequencies are given by:

22222

11111

,,)(

,,)(

inpinsininin

inpinsininin

jXRfZ

jXRfZ

(3)

where θinsx and θinpx are the electrical lenghts of the equivalent transmission line, in series or parallel, to synthesize the input impedance at the corresponding x frequency (1 at f1 and 2 at f2 in Fig. 5).

The output network in the structure shown in Fig. 6 is based on an E-CRLH structure, establishing four impedance conditions

º90,º90.),.()·2(

,,)(

º90,º90.),.()·2(

,,)(

2

22222

1

11111

p

pspp

ps

pspp

scofZ

jXRfZ

cofZ

jXRfZ

(4)


where θsx and θpx are the electrical lengths of the equivalent transmission line in series or parallel to synthesize the output impedance at the corresponding x frequency (1 at f1 and 2 at f2 in Fig. 6). As discussed above, an E-CRLH line is able to meet four frequency conditions simultaneously. Therefore, with a single network the output impedance in class CE can be implemented.

Amp CRLH S

CR

LH

P

º90,º90.),()·2(

,,)(

º90,º90.),()·2(

,,)(

2

22222

1

11111

p

pspp

p

pspp

sofZ

jXRfZ

sofZ

jXRfZ

22222

11111

,,)(

,,)(

inpinsinin

inpinsinin

jXRfZin

jXRfZin

E

CR

LH

P

ECRLH S

Fig. 6. Proposed structure with CRLH and E-CRLH lines for dual band CE amplifier.

The solution presented in Fig. 1e solves the dual amplifier with two diplexers at the input and output. Each of the diplexers divides the signal towards the corresponding amplifier depending on the frequency. Both diplexers are implemented with CRLH lines [13], offering an optimal performance and a more compact design.

5. Practical Design and Simulations

DC

RFRF&DC

12

3

BIASTEEID=X1

3:Bias

1 2

HBTUNER2ID=TU1Mag1=0.3Ang1=131 DegMag2=0.99Ang2=0 DegMag3=0.99Ang3=0 DegFo=0.38 GHzZo=50 Ohm

DCVSID=V1V=4.5 V

INDID=L1L=25.05 nH

CAPID=C1C=11.9 pF

RESID=R1R=36 Ohm

SLCID=LC1L=1 nHC=18 pF

INDID=L2L=0.5 nH

C

B

E

1

2

3

SUBCKTID=S1NET="BFG591"

PORTP=2Z=50 Ohm

PORT1P=1Z=50 OhmPwr=18 dBm

(a)

(b)

Fig. 7. BFG591 transistor. a) Simulated electrical circuit with padding. b) Transistor padding detail view 3D.

For practical designs and simulations the TETRA (380 MHz) and GSM (960 MHz) bandwidths have been chosen. These frequencies are widely used in portable wireless handsets and are a good application example. The chosen transistor must satisfy the following criteria:

1. Single supply operation and low bias (<5V).

2. 26 dBm output capability at 1 GHz

3. Efficient operation (PAE>60%)

4. Availability of a large signal model

5. Available as discrete packaged device

The choice of the BFG591 transistor allows an easy modeling with the Microwave Office (AWR 2007). An input resistive padding (with frequency equalization) has been used to stabilize it at low frequencies (see Fig. 7). The separation between frequencies allows that the order of the CRLH networks would not be very high.

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

load_pull_380Swp Max

315

Swp Min1

p30p29

p28p27

p26p25p24

p23p22p21p20p19

p18p17p16p15p14

p13p12p11p10

p9p8p7p6p5p4p3

p2p1

Mag 0.3034Ang 130.8 Deg

Mag 0.2445Ang 100.9 DegMag 0.3877

Ang 151.8 Deg

LPCS(27.5,20,0.5)pout_380

LPCSMAX()pout_380

LPCS(71,60,1)pae_380

LPCSMAX()pae_380

p1: = 60

p2: = 61

p3: = 62

p4: = 63

p5: = 64

p6: = 65

p7: = 66

p8: = 67

p9: = 68

p10: = 69

p11: = 70

p12: = 71

p13: = 71.796

p14: = 20

p15: = 20.5

p16: = 21

p17: = 21.5

p18: = 22

p19: = 22.5

p20: = 23

p21: = 23.5

p22: = 24

p23: = 24.5

p24: = 25

p25: = 25.5

p26: = 26

p27: = 26.5

p28: = 27

p29: = 27.5

p30: = 27.626 Fig. 8. 380 MHz Load Pull Simulation. PAE and Pout contours

to determine the optimal load impedance.

0 2 4 5.263Time (ns)

Vce & Ic (380 MHz) conv. lines

0

5

10

15

20

-100

25

150

275

400

1.843 ns317.7 mA

0.2021 ns19.85 V

load_pull_380 (L, V)

load_pull_380 (R, mA) Fig. 9. Voltage Vce and current Ic waveforms (380 MHz).

A load-pull analysis has been undertaken in order to select the necessary input and output impedance device. For this case it is usual to take a compromise between efficiency and output power. Figs 8 to 10 show the effi-ciency and power contours obtained for the device stabi-lized at design frequencies, 380 and 960 MHz. The signals waveforms VCE and IC of the implemented circuit with


these impedances, clearly demonstrate a typical behavior of the CE class at both frequencies (see Fig. 9 and 11).

0 1.0

1.0

-1.0

10.0

10.0

-10.0

5.0

5.0

-5.0

2.0

2.0

-2.0

3.0

3.0

-3.0

4.0

4.0

-4.0

0.2

0.2

-0.2

0.4

0.4

-0.4

0.6

0.6

-0.6

0.8

0.8

-0.8

load_pull_960Swp Max

323

Swp Min1

p28p27

p26p25

p24p23

p22p21p20

p19p18p17p16

p15p14p13

p12p11

p10p9p8p7

p6p5p4p3p2p1

Mag 0.2915Ang 133.3 Deg

LPCS(26,19,0.5)pout_960

LPCSMAX()pout_960

LPCS(68,58,1)pae_960

LPCSMAX()pae_960

p1: = 58

p2: = 59

p3: = 60

p4: = 61

p5: = 62

p6: = 63

p7: = 64

p8: = 65

p9: = 66

p10: = 67

p11: = 68

p12: = 68.013

p13: = 19

p14: = 19.5

p15: = 20

p16: = 20.5

p17: = 21

p18: = 21.5

p19: = 22

p20: = 22.5

p21: = 23

p22: = 23.5

p23: = 24

p24: = 24.5

p25: = 25

p26: = 25.5

p27: = 26

p28: = 26.06 Fig. 10. 960 MHz Load Pull Simulation. PAE and Pout contours

to determine optimal load impedance.

0 0.5 1 1.5 22.083Time (ns)

Vce & Ic (960 MHz) conv. lines

0

5

10

15

-100

33.3

167

300

0.7586 ns258 mA

0.06967 ns14.55 V

load_pull_960 (L, V)

load_pull_960 (R, mA) Fig. 11. Voltage Vce and current Ic waveforms (960 MHz).

After an optimization procedure the needed conjugate impedances at the working frequency with an open circuit at the second harmonics are presented in Tab. 2.

f1=380 MHz

PAE= 70.95% DCRF=81.18% Pout=27dBm

Vce=4.41·Vcc Zin=16.56-36.27j Zout=30.67-15.26j

f2=960 MHz

PAE= 66.64% DCRF=92.77% Pout=26dBm

Vce=3.23·Vcc Zin=13.01-4.12j Zout=30.95-14.33j

Tab. 2. Transistor values summary.

MHz Line

f1=380 2f1=720 f2=960 2f2=1920

Input

Series Line 14.45º N.D. 27.75º N.D.

Shunt Line 127.6º N.D. 54.31º N.D.

Output

Series Line 57.5º ±90º 54.82º ±90º

Shunt Line 45.41º ±90º 39.3º ±90º

Tab. 3. Conventional lines values summary.

The simulated results with a transistor model includ-ing the actual components of resistors and capacitors show

small differences respect to the presented results due to the corresponding package tolerances. Tab. 3 shows the values of the results obtained by conventional lines calculation.

DC

RFRF&DC

12

3

BIASTEEID=X1

DC

RFRF&DC

1 2

3

BIASTEEID=X2

TLINID=TL1Z0=50 OhmEL=14.45 DegF0=0.38 GHz

TLOCID=TL2Z0=50 OhmEL=127.8 DegF0=0.38 GHz



DCVSID=V1V=4.5 V

C

B

E

1

2

SUBCKTID=S1NET="transistor"

PORTP=2Z=50 Ohm


(a)

0.361 0.371 0.381 0.391 0.399Frequency (GHz)

Pout, PAE & S11 (380MHz) conv. lines

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.38 GHz-33.08 dB

0.38 GHz65.88

0.38 GHz25.63 dBm

DB(|Pcomp(PORT_2,1)|) (L, dBm)

PAE(PORT_1,PORT_2) (R)

DB(|LSSnm(PORT_1,PORT_1,1,1)| ) (L)

(b)

Fig. 12. Conventional Lines amplifier: Output power, PAE and return loss (380 MHz).

DCRF

RF&DC

12

3

BIASTEEID=X1

DCRF

RF&DC

1 2

3

BIASTEEID=X2

DCVSID=V1V=4.5 V





C

B

E

1

2


PORTP=2Z=50 Ohm

PORT1P=1Z=50 OhmPwr=20.5 dBm

(a)

0.912 0.932 0.952 0.972 0.992 1.008Frequency (GHz)

Pout, PAE & S11 (960MHz) conv. lines

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.96 GHz-33.35 dB

0.96 GHz63.58

0.96 GHz25.39 dBm

DB(|Pcomp(PORT_2,1)|) (L, dBm)


DB(|LSSnm(PORT_1,PORT_1,1,1)|) (L)

(b)

Fig. 13. Conventional Lines amplifier: Output power, PAE and return loss (960MHz).


5.1 Design with CRLH Meta-Lines and Conventional Lines

In this case the input networks (with lumped and dis-tributed components) are synthesized with CRLH transmis-sion lines (only two phase conditions are needed). The obtained values, according to Fig. 2b, are shown in Tab. 4 (capacities in pF, inductances in nH, and lengths referred to electrical degrees at f1=380 MHz).

CL LL Length

CRLH S 8.46 21.16 41.26º

CRLH P 13.5 33.69 53.26º

Tab. 4. Input CRLH line. Values summary Conventional Lines amplifier: Output power, PAE and return loss (960 MHz).

Simulated circuit is shown in Fig. 14. This circuit shall provide a dual frequency performance so that at each of the two working frequencies, the transistor input and output impedances will be the typical of a CE class.

DCRF

RF&DC

1 2

3

BIASTEEID=X1

DC

RFRF&DC

12

3

BIASTEEID=X2

DCVSID=V1V=6 V

TLINID=TL1Z0=50 OhmEL=45 DegF0=0.96 GHz


TLOCID=TL2Z0=50 OhmEL=45 DegF0=0.96 GHz

TLOCID=TL4Z0=50 OhmEL=45 DegF0=0.38 GHz

OPENID=J1

OPENID=J2

C

B

E

1

2


SUBCKTID=S2NET="metalinea_1"PhiR=PhiRssCL=CLssLL=LLss

SUBCKTID=S3NET="metalinea_1"PhiR=PhiRspCL=CLspLL=LLsp

SUBCKTID=S4NET="metalinea_1"PhiR=PhiResCL=CLesLL=LLes

SUBCKTID=S5NET="metalinea_1"PhiR=PhiRepCL=CLepLL=LLep

PORT1P=1Z=50 OhmPwr={16} dBm

PORTP=2Z=50 Ohm

PhiRes=42.96

CLes=24.82

LLes=62.05

PhiRep=49.24

CLep=11.69

LLep=29.24

PhiRss=39.04

CLss=11.44

LLss=28.59

PhiRsp=53.62

CLsp=9.976

LLsp=24.94

(a)

CAPID=C1C=2*CL pF

INDID=L1L=LL nH

CAPID=C3C=2*CL pF

TLINID=TL1Z0=50 OhmEL=PhiR DegF0=0.380 GHz

TLINID=TL2Z0=50 OhmEL=PhiR DegF0=0.380 GHz

PORTP=1Z=50 Ohm

PORTP=2Z=50 Ohm

LL<<0

CL<<0

PhiR<<0

(b)

Fig. 14. CRLH & Conventional Lines dual amplifier: Circuit (a) and CRLH line detail (b).

0.361 0.371 0.381 0.391 0.399Frequency (GHz)

Pout, PAE & S11 (380MHz) CRLH - conv. lines

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.38 GHz-21.41 dB

0.38 GHz66.85

0.38 GHz26.36 dBm

DB(Re(Pcomp(PORT_2,1))) (L, dBm)



Fig. 15. CRLH & Conventional Lines dual amplifier: Output

power, PAE and return loss (380 MHz).

0.912 0.932 0.952 0.972 0.992 1.008Frequency (GHz)

Pout, PAE & S11 (960MHz) CRLH - conv. lines

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.96 GHz-25.03 dB

0.96 GHz69.52

0.96 GHz25.57 dBm




Fig. 16. CRLH & Conventional Lines dual amplifier: Output

power, PAE and return loss (960MHz).

The results at both frequencies are shown in Fig. 15 and 16. Two problems arise with this circuit: its narrow bandwidth, especially at the higher frequency and its sen-sitivity with the tolerance component.

5.2 Design with CRLH and E-CRLH Meta-Lines

In this case the output networks are synthesized with E-CRLH lines (where four phase conditions are necessary at both-fundamental and its respective harmonics), so the joint amplifier-network performance corresponds to a CE class at both operating frequencies. In particular, a meta-material E-CRLH transmission line, under a widespread equilibrium condition, has two spread frequencies of infi-nite wavelength. In addition, the E-CRLH structure is inherently a four-band (where the four frequencies are arbi-trarily chosen).

To determine the values of all components, four equations with four unknown variables (frequencies) must be solved by using the equation (5).

)(·

))·((22

22

221

2

ocR

eec

. (5)

Frequencies ω1e and ω2e are two balanced transition frequencies that satisfy equations (6) and (7).

oee 21 · (6)

cR

cR

cR

CL ·

1

(7)

The frequencies of the system have been numerically obtained and the results are used to calculate the compo-nents values. The order (number of stages of the CRLH transmission line) in both structures must be as low as possible in order to minimize the losses.

In other words, these lines allow determining four de-sired electric lengths at four selected frequencies. The input network values (capacity in pF, inductances in nH and lengths referred to electrical degrees at f1=380 MHz) are


the same as in the previous case (Tab. 4), whereas the values in Tab. 5 correspond to the output E-CRLH lines (according to Fig. 3).

E-CRLH S CRC=1.34 LR

C=3.35 CLC=10.25

CRD=15.9 LR

D=39.7 CLD=0.864

E-CRLH P CRC=1.38 LR

C=3.45 CLC=9.924

CRD=0.99 LR

D=2.48 CLD=13.78

Tab. 5. Values for the output E-CRLH line.

The resulting circuit is implemented by blocks to look for the optimal order value. An example of block and the corresponding E-CRLH line is shown in Fig. 17.

DCRF

RF&DC

1 2

3

BIASTEEID=X1

DCVSID=V1V=4.5 V

DC

RFRF&DC

12

3

BIASTEEID=X2

1

OPENID=J11

OPENID=J2

C

B

E

1

2


1 2

SUBCKTID=S2NET="ecrlh_serie"

1

2

SUBCKTID=S3NET="ecrlh_para"

1 2

SUBCKTID=S4NET="crlhs"

1

2

SUBCKTID=S5NET="crlhp"

PORTP=2Z=50 Ohm


(a)

CAPID=C1C=CLC pF

CAPID=C2C=CLD pF

CAPID=C3C=CRD pF

CAPID=C4C=CRC pF

INDID=L1L=LRC nH

INDID=L2L=LRD nH

INDID=L3L=LLD nH

INDID=L4L=LLC nH

PORTP=1Z=50 Ohm

PORTP=2Z=50 Ohm

(b)

Fig. 17. E-CRLH dual amplifier: Circuit (a) and E-CRLH line detail (b).

0.361 0.371 0.381 0.391 0.399

Frequency (GHz)

Pout, PAE & S11 (380 MHz) CRLH - ECRLH

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.38 GHz-14.92 dB

0.38 GHz57.41

0.38 GHz25.9 dBm




Fig. 18. E-CRLH dual amplifier: Output power, PAE and

return loss (380 MHz).

Fig. 18 and 19 show the output power, the power added efficiency (PAE) and the return losses at the two working frequencies. The PAE is close to 60 % at the two working frequencies but with a very narrow band at

960 MHz. The sensitivity problems still maintains, espe-cially when compared with the results of Fig. 13b. The same problems can be seen for the 380 MHz band when compared with Fig. 12b.

0.912 0.932 0.952 0.972 0.992 1.008Frequency (GHz)

Pout, PAE & S11 (960 MHz) CRLH - ECRLH

-40

-20

0

20

40

Pou

t (dB

m)

- R

etur

n Lo

sses

(dB

)

0

25

50

75

100

PA

E (

%)

0.96 GHz-18.95 dB

0.96 GHz25.4 dBm

0.96 GHz58.58




Fig. 19. E-CRLH dual amplifier: Output power, PAE and

return loss (960 MHz).

Fig. 20 and 21 show the waveforms resulting from simulation for current and voltage in the amplifier, working at 380 and 960 MHz, respectively. Both waveforms corre-spond to the response of a CE class amplifier being the voltage working cycle very lower than 50%.

0 2 4 5.263Time (ns)

Vce & Ic (380 MHz) CRLH-ECRLH

0

5

10

15

20

Vce

(V

)

-100

25

150

275

400

Ic (

mA

)

Vtime(S1\S1\V_METER.VM1,1)[20] (L, V)

Itime(S1\S1\I_METER.AMP1,1)[20] (R, mA)

Fig. 20. E-CRLH dual amplifier: voltage Vce and current Ic

waveforms (380 MHz).

0 0.5 1 1.5 22.083Time (ns)

Vce & Ic (960 MHz) CRLH-ECRLH

0

5

10

15

Vce

(V

)

-100

33.3

167

300

Ic (

mA

)

Vtime(S1\S1\V_METER.VM1,1)[49] (L, V)

Itime(S1\S1\I_METER.AMP1,1)[49] (R, mA)

Fig. 21. E-CRLH dual amplifier: voltage Vce and current Ic

waveforms (960 MHz).


5.3 Design with CRLH Diplexers

For the realization of this design authors have de-signed a CRLH diplexer [13]. Fig. 22 shows the operation of the CRLH diplexer with ideal components. A behavior according to the results of design is seen in Fig. 22. Port 2 works at 380 MHz while port 3 works at 960 MHz.

0.005 0.505 1.01 1.1Frequency (GHz)

dcrlh_ideal

-50

-40

-30

-20

-10

0

0.38 GHz-0.2711 dB 0.96 GHz

-0.3234 dB

DB(|S(2,1)|)dcrlh_ideal





Fig. 22. Diplexer. Return loss and transmission loss in dB.

If the ideal elements are replaced by complex models (see Fig. 23), an acceptable behavior is observed (see Fig. 24). The difference with previous ones is very slightly.

MLINID=TL1W=0.88 mmL=6.25 mm

MLINID=TL2W=0.88 mmL=5+x mm

MLINID=TL3W=0.88 mmL=5+x mm

1

2

3 MTEE$ID=TL7


MLINID=TL10W=0.895 mmL=4 mm

MBENDRWXID=MS1W1=0.1 mmW2=0.6 mm




1

2

3

MTEEID=TL53W1=0.1 mmW2=0.1 mmW3=0.1 mm

1

2

3




1

2

3


1

2

3


1

2

3


1

2

3




1 2

3







12

3


1 2

3






12

3




MBENDAID=TL32W=0.88 mmANG=90 Deg

MBENDAID=TL33W=0.88 mmANG=90 Deg









SUBCKTID=S4NET="via_simple"

SUBCKTID=S8NET="via_simple"

SUBCKTID=S1NET="bobina_0403_12"

SUBCKTID=S2NET="bobina_0403_5_5"

SUBCKTID=S7NET="capacitor_0402_4_3"

SUBCKTID=S15NET="capacitor_0402_1"


SUBCKTID=S16NET="capacitor_0402_4_3"





PORTP=1Z=50 Ohm

PORTP=2Z=50 Ohm

PORTP=3Z=50 Ohm

lr2=28.4

ll2=14.28

lr1=12

ll1=6

x=6.9

x2=8.4

a)

b)

Fig. 23. Physical simulated Diplexer. Schematic a) and 3D view b).

0.005 0.505 1.01 1.1Frequency (GHz)

dcrlh_sen

-50

-40

-30

-20

-10

0

0.96 GHz-0.3079 dB

0.38 GHz-0.3076 dB

DB(|S(2,1)|)dcrlh_sen





Fig. 24. Physical simulated Diplexer. Return loss and

transmission loss in dB.

The diplexer is very robust against the tolerance com-ponents. A complete dual amplifier (see Fig. 25) where each amplifier branch is composed of a driver and a power amplifier has been realized.

In the amplifier simulations, at each frequency (Fig. 26 and 27) the PAE represented takes into account the power consumed by the quiescent branch (20 mA in the 960 MHz branch, and 10 mA in the 380 MHz branch). Thus, this PAE value is actually higher, as it is evidenced in the individual simulations (Fig. 28 and 29). The PAE improves up to near 9% at 380 MHz and 5% at 960 MHz.

12

3

SUBCKTID=S1NET="diplexor"

12

3

SUBCKTID=S4NET="diplexor"

SUBCKTID=S3NET="amplificador_A1_AC_380"

SUBCKTID=S2NET="amplificador_A1_AC_960"

PORTP=2Z=50 Ohm


(a)

(b)

Fig. 25. Physical simulated Dual-Amplifier circuit. Schematic (a) and 3D view (b).


-16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12

Pin (dBm)

Dual Amplifier (A1-380 MHz)

-20

-15

-10

-5

0

5

10

15

20

25

30

Po

ut

(dB

m)

0

10

20

30

40

50

60

70

80

90

100

PA

E (

%),

Ic(

mA

)

-2 dBm25.41 dBm

-2 dBm47.01

Pout (dBm) (L, dBm)

PAE (%) (R)

Ic_CE (mA) (R, mA)

Ic_A (mA) (R, mA)

Fig. 26. Dual amplifier (A1 with diplexer): Simulated output

power, PAE, driver current (Ic_A) and stage output current (Ic_CE) at 380 MHz.

-16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12Pin (dBm)


-20

-15

-10

-5

0

5

10

15

20

25

30

Po

ut

(dB

m)

0

10

20

30

40

50

60

70

80

90

100

PA

E (

%),

Ic

(m

A)

10 dBm25.4 dBm

10 dBm50.04

Pout (dBm) (L, dBm)

PAE (%) (R)

Ic_CE (mA) (R, mA)

Ic_A (mA) (R, mA)

Fig. 27. Dual amplifier (A1 with diplexer): Simulated output

power, PAE, driver current (Ic_A) and stage output current (Ic_CE) at 960 MHz.

-16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12Pin (dBm)


-20

-15

-10

-5

0

5

10

15

20

25

30

Po

ut

(dB

m)

0

10

20

30

40

50

60

70

80

90

100

PA

E (

%),

Ic(

mA

)

-2 dBm25.41 dBm

-2 dBm56.33

Pout (dBm) (L, dBm)

PAE (%) (R)

Ic_CE (mA) (R, mA)

Ic_A (mA) (R, mA)

Fig. 28. Amplifier (A1 with diplexer): Simulated output power,

PAE (without quiescent branch consumption), driver current (Ic_A) and stage output current (Ic_CE) at 380 MHz.

-16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12Pin (dBm)


-20

-15

-10

-5

0

5

10

15

20

25

30

Po

ut

(dB

m)

0

10

20

30

40

50

60

70

80

90

100

PA

E (

%),

Ic

(m

A)

10 dBm25.4 dBm

10 dBm54.99

Pout (dBm) (L, dBm)

PAE (%) (R)

Ic_CE (mA) (R, mA)

Ic_A (mA) (R, mA)


PAE (without quiescent branch consumption), driver current (Ic_A) and stage output current (Ic_CE) at 960 MHz.

The driver has been optimized by using a load as a fi-nal stage, instead of a classic output impedance of 50 Ohms. This improves the overall efficiency (the opti-mized circuit is called A2 in Fig. 30 and 31). In the figures the PAE shown corresponds to the set of the amplifier and includes the driver consumption. The quiescent branch consumption has not been considered, while the repre-sented collector efficiency is only referred to the output power amplifier of the active branch: neither the driver nor the quiescent branch consumptions are included. The PAE is increased in more than 10 % vs. the A1 amplifier at 380 MHz. The collector efficiency obtained at 960 MHz is near to 90%.

-3 0 3 6 9 12Pin (dBm)


20

21

22

23

24

25

26

27

28

Pou

t (d

Bm

)

44

48.5

53

57.5

62

66.5

71

75.5

80

PA

E (

%),

Col

ect

or E

ffic

ien

cy (

%)

6 dBm77.54

6 dBm25.345 dBm

6 dBm61.15

Pout (dBm) (L, dBm)

PAE (%) (R)

Collector Efficiency (%) (R)


PAE and Collector Efficiency (380 MHz).

-3 0 3 6 9 12Pin (dBm)

Dual amplifier (A2-960MHz).

-8

-4

0

4

8

12

16

20

24

28

Po

ut

(dB

m)

10

20

30

40

50

60

70

80

90

100

PA

E (

%),

Co

llect

or E

ffic

ien

cy (

%)

11 dBm25.47 dBm

11 dBm89.074 11 dBm

60.215

Pout (dBm) (L, dBm)

PAE (%) (R)

Collector Efficiency (%) (R)


PAE and Collector Efficiency (960 MHz).

0.36 0.365 0.37 0.375 0.38 0.385 0.39 0.395 0.4Frequency (GHz)

380 MHz Dual Amplifier (A2)

20

21

22

23

24

25

26

27

28

Pou

t (dB

m)

50

53.75

57.5

61.25

65

68.75

72.5

76.25

80

PA

E (

%)

Pout (L, dBm)

PAE (R)

Fig. 32. Dual amplifier (A2 with diplexer): Statistical

sensitivity study of the output power and PAE (380 MHz).


Finally Fig. 32 and 33 show the study of the statistical sensitivity at both frequencies after 200 iterations with uniform statistical distribution [14], ±5% tolerance for capacitors, inductors and transistors, and ±1% for sub-strate. The tolerance performance is good, especially for the interesting input power, where the transistor output is already saturated.

0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1 1.01Frequency (GHz)

960 MHz Dual Amplifier (A2)

18

19

20

21

22

23

24

25

26

27

28

Pou

t (dB

m)

40

44

48

52

56

60

64

68

72

76

80

PA

E (

%)

Pout (L, dBm)

PAE (R)

Fig. 33. Dual amplifier (A2 with diplexer): Statistical

sensitivity study of the output power and PAE (960 MHz).

Fig. 32 and 33 also show the kindness of the design, presenting a great robustness performance with regard to other CRLH topologies. The other structures are more sensitive so their studies are not presented.

Tab. 6 shows a summary between the different simu-lated circuits, where one can see that all the alternatives offer high efficiency. The choice of one or the other de-pends on the requirements for each use and, mainly, from the sensitivity to the tolerance of the components.

380 MHz 960 MHz

PAE (%) out(%) PAE (%) out (%)

Individual Amp. conv. lines

65.9 79.5 63.6 91

CRLH+ conv. Lines 66.9 73.6 69.5 87.6

CRLH+ECRLH 57.4 68 58.6 86

CRLH Diplexers 62 80 60 89

Tab. 6. Approximate PAE and efficiency collector values of simulated amplifiers.

The circuit with CRLH and conventional lines pre-sents a higher PAE, but the design becomes more complex and very sensitive to the components tolerance. The circuit with E-CRLH is more compact and easier to implement but, also, very sensitive to the components tolerance. Fi-nally, the amplifier with diplexers has the great advantage

of its easiest design and individual control of frequencies and its better statistical sensitivity at a price of a less com-pact design. For that reason, this last topology has been manufactured. Fig. 34 shows a photo of the proposed high efficiency amplifier based on a diplexer topology.

Fig. 34. Photo of the manufactured high efficiency amplifier

based on a D-CRLH line diplexer.

Tab. 7 shows the experimental results obtained for this architecture. The efficiency results show good agree-ment with the simulations.

380 MHz 960 MHz

PAE (%) out(%) PAE (%) out (%)

CRLH Diplexers

(simulation) 62 80 60 89

CRLH Diplexers

(experimental) 64.5 71.2 61.2 91.2

Tab. 7. Approximate PAE and efficiency collector values of the diplexer D-CRLH high efficiency amplifier.

6. Conclusions In this paper the authors have presented several meth-

ods for designing dual band high efficiency power amplifi-ers. A comparison with the results for individual amplifiers has been realized demonstrating the viability of these cir-cuits, since they can provide high efficiency and compact design by means of using CRLH lines.

References

[1] FUKUDA, A., OKAZAKI, H., HIROTA, T., YAMAO, Y., QIN, Y., GAO, S., SAMBELL, A., KOROLKIEWICZ, E. Novel 900 MHz/1.9 GHz dual-mode power amplifier employing MEMS switches for optimum matching. IEEE Microw. Wireless Compon. Lett., Mar.2004, vol. 14, no. 3, pp. 121–123.

[2] UJIE, R., SATO, H., ISHIHARA, N. A dual-band RF-CMOS amplifier using inductive reactance switching. In Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. Jan 2007, pp 131-134.


[3] SOKAL, N. O., SOKAL, A. D. Class E—A new class of high-efficiency tuned single-ended switching power amplifiers. IEEE J. Solid-State Circuits, Jun. 1975, vol. SC- 10, no. 6, pp. 168–176.

[4] LIN, I., DEVINCENTIS, M., CALOZ, C., ITOH, T. Arbitrary dual-band components using composite right/left handed transmission lines. IEEE Trans. Microw. Theory Tech., Apr. 2004, vol. 50, no. 4, pp. 1142–1149.

[5] SEUNG HUN JI, CHOON SIK CHO, LEE, J. W., JAEHEUNG KIM Concurrent dual-band class-E power amplifier using composite right/left-handed transmission lines. IEEE Transactions on Microwave Theory and Techniques, June 2007, vol. 55, no. 6, part 2, pp.1341 – 1347.

[6] THIAN, M., FUSCO, V. Design strategies for dual-band class-E power amplifier using composite right/left-handed transmission lines. Microw. and Opt. Technology Letters, Nov 2007, vol 49, no 11, pp 2784-2788.

[7] RENNINGS, A., OTTO, S., MOSIG, J., CALOZ, C., WOLFF, I. Extended composite right/left-handed (E-CRLH) metamaterial and its application as quadband quarter- wavelength transmission line. In Asia-Pacific Microwave Conf. (APMC 2006). Dec. 12-15, 2006.

[8] RENNINGS, A., LIEBIG, T., CALOZ, C., WOLFF, I. Double-Lorentz transmission line metamaterial and its application to tri-band devices. In IEEE/MTT-S International Microwave Symposium, 2007, Yokohama (Japan), Jun. 2007, p. 1427-1430.

[9] KRAUSS, H. L., BOSTIAN, C. W., RAAB, F. H. Solid State Radio Engineering. New York: J. Wiley & Sons, 1980.

[10] CRIPPS, S. C. RF Power Amplifiers for Wireless Communications. New York: Artech House, 1999.

[11] DUPUY, A.; LEONG, K. M., ITOH, K. H. Class-F power amplifier using a multi-frequency composite right/left-handed transmission line harmonic tuner. In IEEE MTT-S International Microwave Symposium Digest, 2005.

[12] KAZIMIERCZUK, M. K., TABISZ, W. A. Class C-E high-efficiency tuned power amplifier. IEEE Transactions on Circuits and Systems. March 1989, vol.36, no. 3.

[13] GONZÁLEZ-POSADAS, V. , JIMÉNEZ-MARTÍN, J.L., GAR-CÍA-MUÑOZ, L. E., SEGOVIA-VARGAS, D. Novel diplexer made with dual-composite right/left handed lines (D-CRLH). In 14th Conference Microwave Techniques COMITE 2008, April 2008.

[14] GILMORE, R., BESSER, L. Practical RF Circuit Design for Modern Wireless Systems, vol. I. New York: Artech House, 2003.

About Authors ... Jose Luis JIMENEZ-MARTIN was born in Madrid, Spain, in 1967. He received in Radio-communication Technical Engineering (B.S. in Electrical Engineering) in 1991, telecommunications engineering (M.S.) and Ph.D. degrees, Universidad Politecnica de Madrid, Spain, in 2000 and 2005, respectively. Also, he received a Master's degree in High Strategic Studies from the CESEDEN (organiza-tion pertaining to the Spanish Ministry of Defense) in 2007. Currently, he is Associate Professor at the Technical Telecommunication School, Polytechnic University of Madrid. His interests are related to oscillator, amplifier, RADAR, microstrip antennas, CRLH lines and meta-mate-rials, and microwave technology. He has authored or co-

authored more than 40 technical conference, letter, and journal papers.

Vicente GONZALEZ-POSADAS was born in Madrid, Spain, in 1968. He received in Radio-communication Technical Engineering (B.S. in Electrical Engineering), Universidad Politecnica de Madrid (UPM) in 1992, the M.S. degree in physics in 1995, from the Universidad Nacional de Educacion a Distancia (UNED), and the Ph.D. degree in telecommunication engineering from the Carlos III University of Madrid in 2001. Currently, he is Associate Professor at the Technical Telecommunication School, UPM. His interests are related to active antennas, micro-strip antennas, CRLH lines and meta-materials, and mi-crowave technology. He has authored or coauthored more than 60 technical conference, letter, and journal papers. He has also been member of the European Projects Cost260, Cost284, and COST IC0603.

F. Jose ARQUES OROBON was born in Murcia, Spain, in 1966. He received Telematics Technical Engineering (B.S. in Electrical Engineering) degree, Universidad Politecnica de Madrid (UPM) in 1992, M.S. degree in Electrical engineering in 1998, Complutense University of Madrid (UCM). At the time, he is writing his Ph. D. thesis at the Department of Audiovisual Engineering and Com-munications, UPM. Currently, he is an Assistant Professor at the Technical Telecommunication School at UPM. His interests are related to CRLH lines and meta-materials, sensors and microwave technology. He has authored or coauthored in several technical conferences, letters, and journal papers. He is working in several projects with the Ministry of Environment of Spain, in the development of monitoring networks (via satellite) to control environ-mental quality.

L. Enrique GARCIA-MUÑOZ received the Telecommu-nications engineer degree and the Ph.D. degree in tele-communications, Universidad Politecnica de Madrid, Spain, in 1999 and 2003, respectively. Currently, he is Associate Professor at the Department of Signal Theory and Communications, University Carlos III, Madrid. His main research interests include radioastronomy receivers, radiotelescopes, microstrip patch antennas and arrays, as well as periodic structures applied to electromagnetics.

Daniel SEGOVIA-VARGAS was born in Madrid, Spain, in 1968. He received the telecommunications engineering and the Ph.D. degrees, Universidad Politecnica de Madrid in 1993 and 1998, respectively. From 1993 to 1998, he was an Assistant Professor at Valladolid University, Valladolid. Since 1998, he is Associate Professor at Carlos III Univer-sity, Madrid, where he is in charge of the microwaves and antenna courses. He has authored and coauthored more than 90 technical conference, letters, and journal papers. His research areas are printed antennas, active radiators and arrays, smart antennas, LH metamaterials, and passive circuits. He has also been member and National Delegate of the European Projects Cost260, Cost284, and COST IC0603.

Documents

Dual Band High Efficiency Power Amplifier Based on CRLH Lines · 2010-04-10 · Dual Band High Efficiency Power Amplifier Based on CRLH Lines ... dual frequency high efficiency amplifiers