DUSD(Labs)

EE249 Project:EE249 Project:High-Level Power Estimation High-Level Power Estimation in Metropolisin Metropolis

Mentor:Mentor:

John Moondanos,John Moondanos,

GSRC Visiting Fellow, UC BerkeleyGSRC Visiting Fellow, UC Berkeley

&&

Strategic CAD Labs Intel Corp.Strategic CAD Labs Intel Corp.

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Problem Description: POWER estimationProblem Description: POWER estimation

Main Concern during the Design CycleMain Concern during the Design Cycle

Power Consumption is the critical elementPower Consumption is the critical element

Many stringent power requirementsMany stringent power requirements

Challenging ProblemChallenging Problem Need fast estimation methods at the high levelNeed fast estimation methods at the high level

We shouldn’t have to go all the way down to the gate-level of every We shouldn’t have to go all the way down to the gate-level of every implementationimplementation

Much of the technology for low level power estimation exists either Much of the technology for low level power estimation exists either

in university research or in CAD vendors.in university research or in CAD vendors.

This is not the case in high-level design.This is not the case in high-level design.

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Goal of the ProjectGoal of the Project

Briefly Review the literature to capture the state of the artBriefly Review the literature to capture the state of the artRefer to the end of this presentation for relevant papersRefer to the end of this presentation for relevant papers

Develop technologies and methodologies for solving the Develop technologies and methodologies for solving the

power estimation problem within the Metropolis power estimation problem within the Metropolis

environmentenvironmentMethodologies will focus more on the system modeling Methodologies will focus more on the system modeling

methodology that is better suited for the capabilities of Metropolismethodology that is better suited for the capabilities of Metropolis

Technologies will focus more on the algorithms that must be used Technologies will focus more on the algorithms that must be used for power estimation using the capabilities of the Metropolis for power estimation using the capabilities of the Metropolis environment.environment.

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Goal of the Project (cont.)Goal of the Project (cont.)

Sample solution approaches:Sample solution approaches:At the system level show how Metropolis could be used to At the system level show how Metropolis could be used to

provide a power budget distribution identifying the major power provide a power budget distribution identifying the major power consumers.consumers.

Relative accuracy in the estimation at this level is much more Relative accuracy in the estimation at this level is much more important than absolute accuracy.important than absolute accuracy.

Identify Power bottlenecks.Identify Power bottlenecks.

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Suggestion for Design Driver for this ProjectSuggestion for Design Driver for this Project

For the hardware: The PXA800F cell phone processor from For the hardware: The PXA800F cell phone processor from

IntelIntelSome publicly available introductory material on the PXA800F is Some publicly available introductory material on the PXA800F is

available in the “backup material section”available in the “backup material section”

Modeling of the Xscale can happen with the GnuPro simulatorModeling of the Xscale can happen with the GnuPro simulator

For the Software: We have available Statistical Models for For the Software: We have available Statistical Models for

typical applications that run on the PXA800Ftypical applications that run on the PXA800F

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Backup MaterialBackup Material

Overview of the PXA800F cellular phone ProcessorOverview of the PXA800F cellular phone Processor

ReferencesReferences

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The Intel® PXA800F Cellular ProcessorThe Intel® PXA800F Cellular Processor

Full GSM/GPRS Class solutionFull GSM/GPRS Class solution

High-performance/Low-power Intel® XScale High-performance/Low-power Intel® XScale ™™

technology core, providing class-leading technology core, providing class-leading

headroom for rich data applicationsheadroom for rich data applications

Intel® Micro Signal ArchitectureIntel® Micro Signal Architecture

Intel® On-Chip Flash MemoryIntel® On-Chip Flash Memory GSM/GPRS Communications Stack, RTOS and GSM/GPRS Communications Stack, RTOS and

applications code for a single-chip mobile solutionapplications code for a single-chip mobile solution

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The Intel® XScale The Intel® XScale ™™ in the PXA800F in the PXA800F

High-performance, power-efficient processor supports data-intensive applicationsHigh-performance, power-efficient processor supports data-intensive applications

Processor core operates at an adjustable clock frequency from 104 to 312 MHz Processor core operates at an adjustable clock frequency from 104 to 312 MHz

Instruction cache and Data cache memories Instruction cache and Data cache memories

4 MB integrated Intel On-Chip Flash memory 4 MB integrated Intel On-Chip Flash memory

512 KB integrated SRAM 512 KB integrated SRAM

Memory controller supports synchronous Flash mode, page mode Flash, SRAM, Memory controller supports synchronous Flash mode, page mode Flash, SRAM,

DRAM, and variable latency DRAM, and variable latency

DMA controller DMA controller

Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC Clock units-GSM slow clocking, GSM frame timing, watchdog, RTC

Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP, Supports a wide range of standard interfaces-SIM, UART, USB, I2C*, SPI, SSP,

Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick, Digital Audio Interface, MultiMediaCard, Secure Digital Card, Sony Memory Stick,

Dallas* 1-Wire* Interface, keypad, PWM D/A, JTAGDallas* 1-Wire* Interface, keypad, PWM D/A, JTAG

Interfaces for Bluetooth, IrDA, GPS and digital camera peripheralsInterfaces for Bluetooth, IrDA, GPS and digital camera peripherals

LCD Controller for up to 120 x 240 display 16-bit color or gray scaleLCD Controller for up to 120 x 240 display 16-bit color or gray scale

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Intel Micro Signal Architecture in the PXA800FIntel Micro Signal Architecture in the PXA800F

Performs GSM/GPRS baseband signal processing Performs GSM/GPRS baseband signal processing

Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz Modified Harvard architecture, dual-MAC, deep pipeline, 104 MHz

execution clock execution clock

Instruction cache and 64 KB dual-banked data SRAM Instruction cache and 64 KB dual-banked data SRAM

512 KB integrated Intel On-Chip Flash for field-upgradable signal 512 KB integrated Intel On-Chip Flash for field-upgradable signal

processing firmwareprocessing firmware

Includes microprocessor instructions such as bit manipulation Includes microprocessor instructions such as bit manipulation

Includes cipher and Viterbi accelerators Includes cipher and Viterbi accelerators

Multiple sleep modes and integrated power management minimize power Multiple sleep modes and integrated power management minimize power

consumption consumption

Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-Interface support-digital I/Q, voice codec, auxiliary serial port for mixed-

signal analog baseband, I2S audio codec interface, RF synthesizer serial signal analog baseband, I2S audio codec interface, RF synthesizer serial

control interface, JTAGcontrol interface, JTAG

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The Memory SubsystemThe Memory Subsystem

The The Intel® XScale Intel® XScale ™™ Instruction and Data CacheInstruction and Data Cache

4MB of Flash & 512KB of SRAM always at 104MHz4MB of Flash & 512KB of SRAM always at 104MHz

Memory Controller managing accesses to external SRAMMemory Controller managing accesses to external SRAM

The MSAThe MSA Integrated 64KB SRAM for microcontroller like instructionsIntegrated 64KB SRAM for microcontroller like instructions

• Special instructions for maximizing GSM/GPRS performanceSpecial instructions for maximizing GSM/GPRS performance

512KB of flash for program store512KB of flash for program store

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PXA800F Block DiagramPXA800F Block DiagramUARTs for Bluetooth, IRDA

GSM Sim card I/F

External Power Management I/F

Synch Serial Port

Smart Battery I/F

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PXA800F Block DiagramPXA800F Block DiagramMemory Stick

Programmable Clock

Secure Card I/F

Pulse Width Modulator for buzzer

Timing Control UnitFor basestation timing

Encrypt/DecryptGSM data offloading MSA

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PXA800F Block DiagramPXA800F Block Diagram

Viterbi error decoding offloading MSA

High Speed Logger For debug

Full Bandwidth (Hi-Fi) digital audio I/F

DSP Synchronous Serial Ports interfacing with RF, speech

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PXA800F Block DiagramPXA800F Block Diagram

IF

ESED

ISBIUSwitch

PeripheralBus 1

PeripheralBus 2

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ReferencesReferences

““High-level power modeling, estimation, and optimization”,High-level power modeling, estimation, and optimization”,Macii, E.; Pedram, M.; Macii, E.; Pedram, M.;

Somenzi, F., Somenzi, F., IEEE Transactions on Computer-Aided Design of Integrated Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits

and Systems, Volume: 17 Issue: 11 , Nov. 1998 ,Page(s): 1061 -1079and Systems, Volume: 17 Issue: 11 , Nov. 1998 ,Page(s): 1061 -1079

““High-level power estimation” ,High-level power estimation” ,Landman, P.; Landman, P.; Low Power Electronics and Design, Low Power Electronics and Design,

1996., International Symposium on , 12-14 Aug. 1996, Page(s): 29 -351996., International Symposium on , 12-14 Aug. 1996, Page(s): 29 -35

““Towards a high-level power estimation capability”, Towards a high-level power estimation capability”, Nemani, M.; Najm, F.N.; Nemani, M.; Najm, F.N.; IEEE IEEE

Transactions on Computer-Aided Design of Integrated Circuits and Systems, Transactions on Computer-Aided Design of Integrated Circuits and Systems,

Volume: 15 Issue: 6, June 1996, Page(s): 588 -598Volume: 15 Issue: 6, June 1996, Page(s): 588 -598

Integrated hardware-software co-synthesis for design of embedded systems under Integrated hardware-software co-synthesis for design of embedded systems under

power and latency constraints, power and latency constraints, A. Doboli, A. Doboli, March 2001, Proceedings of the March 2001, Proceedings of the

conference on Design, automation and test in Europe conference on Design, automation and test in Europe

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ReferencesReferences

A methodology for high level power estimation and exploration”,A methodology for high level power estimation and exploration”,Krishna, V.; Krishna, V.;

Ranganathan, N.;, Ranganathan, N.;, VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on , VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on ,

19-21 Feb. 1998, Page(s): 420 -42519-21 Feb. 1998, Page(s): 420 -425

Probabilistic bottom-up RTL power estimation”, Probabilistic bottom-up RTL power estimation”, Ferreira, R.; Trullemans, A.-M.; Ferreira, R.; Trullemans, A.-M.;

Costa, J.; Monteiro, J., Costa, J.; Monteiro, J., Quality Electronic Design, 2000. ISQED 2000. Proceedings. Quality Electronic Design, 2000. ISQED 2000. Proceedings.

IEEE 2000 First International Symposium on , 20-22 March 2000, Page(s): 439 -446IEEE 2000 First International Symposium on , 20-22 March 2000, Page(s): 439 -446

Power modeling for high-level power estimation”, Power modeling for high-level power estimation”, Gupta, S.; Najm, F.N.;, Gupta, S.; Najm, F.N.;, Very Very

Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 8 Issue: Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 8 Issue:

1 , Feb. 2000, Page(s): 18 -291 , Feb. 2000, Page(s): 18 -29

Trace-driven system-level power evaluation of system-on-a-chip peripheral cores Trace-driven system-level power evaluation of system-on-a-chip peripheral cores

Tony D. Givargis, Frank Vahid, Jörg Henkel, Tony D. Givargis, Frank Vahid, Jörg Henkel, January 2001 Proceedings of the January 2001 Proceedings of the

conference on Asia South Pacific Design Automation Conference conference on Asia South Pacific Design Automation Conference