Ease of Design Comparison

8/11/2019 Ease of Design Comparison

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Ease

of

Design

ComparisonforaPSiP/MicroModule/PwrSoCDesign

FlowProcess

ASurveybytheDarnellGroup

April

2012

www.Darnell.com


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Copyright 2012, Darnell Group (951) 279-6684 240412 Ease of Design Comparison Page 1

Ease of Design ComparisonFor a PSiP/MicroModule/PwrSoC Design Flow Process

Table of Contents

Introduction ..........................................................................................................3Summary of Findings ...........................................................................................3

Analysis of Survey Results ....................................................................................5DC-DC Regulator vs. PSiP/MicroModule/PwrSoC Design Flow Comparison .......5DC-DC Regulator vs. PSiP/MicroModule/PwrSoC Man Hour Comparison ...........5DC-DC Regulator vs. PSiP/MicroModule/PwrSoC Comparison Man Hoursper step .................................................................................................................6Design Flow Iteration Process .............................................................................13Design Flow Issues .............................................................................................15

Web Based Tools ................................................................................................18Conclusions .........................................................................................................18


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List of Exhibits

TablesTable 1 Typical DC-DC Regulator Design Flowvs. PSiP/MicroModule/PwrSoC Design Flow ... ....................................................4

Table 2 Typical DC-DC Regulator Design Flowvs. PSiP/MicroModule/PwrSoC Design Flow Man Hour Comparison....................5

Table 3 DC-DC Regulator Design Flow Man Hours per step. ............................7

Table 4 PSiP/MicroModule/PwrSoC Design Flow Man Hours per step. ............7

Table 5 DC-DC Regulator Design Flow Man Hours PercentageBreakdown per step ..............................................................................................9

Table 6 PSiP/MicroModule/PwrSoC Design Flow Man Hours PercentageBreakdown per step ..............................................................................................9

Table 7 Typical DC-DC Regulator Design Flow Iterations. ...........................13

Table 8 Typical PSiP/Micro/Module/PwrSoC Design Flow Iterations ... ...........14

Table 9 Actual Steps including Design Flow Iterations Typical DC-DCRegulator vs. Typical PSiP/MicroModule/PwrSoC. .............................................15

Table 10 Typical DC-DC Regulator Design Flow Issues. .................................16

Table 11 PSiP/MicroModule/PwrSoC Design Flow Iterations ...........................16

GraphsGraph 1 DC-DC Regulator Design Flow Man Hours PercentageBreakdown per step ... ........................................................................................10

Graph 2 DC-DC Regulator Design Flow Man Hours PercentageBreakdown per step (With Steps 4 thru 11 Removed) ... ....................................11

Graph 3 DC-DC Regulator Design Flow Man Hour

Comparison. ........................................................................................................12

Graph 4 Typical DC-DC Regulator Design Flow Issues ..................................17

Graph 5 PSiP/MicroModule/PwrSoC Design Flow Iterations. ..........................17


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Introduction

The purpose of this Darnell Group white paper is to quantify the relative ease of design for aPSiP/MicroModule/PwrSoC design flow used in a 5A dc-dc regulator for an FPGA or similar

load vs. a typical dc-dc regulator down solution. In order to do this, the Darnell Group

qualified and validated the design steps for a general PSiP/MicroModule/PwrSoC designconfiguration by conducting a series of surveys comparing a typical DC-DC Regulator design

flow with a comparable PSiP/MicroModule/PwrSoC design flow.

In this paper, a dc-dc regulator is defined as a dc-dc converter IC that uses a switching element totransform the dc supply into an alternating current, which is then converted to a different voltage

using capacitors, inductors, and other elements, then converted back to dc. The circuit includes

regulation and filtering components to insure a steady output. Advantages include the ability togenerate voltages beyond the input supply range, higher power handling capability, and

efficiency; disadvantages include complexity and relatively higher cost. A disadvantage of

Converter/Regulator ICs is that they require the addition of external components such as

inductors, capacitors and/or resistors. The development of PwrSoC and PSiP technologies isintended to eliminate the need for external components and provide a smaller alternative and a

simplified and shorted design flow.

In conducting this survey, individuals at system makers who the Darnell Group considers

knowledgeable in the industry were contacted and asked to fill out a written questionnaire and to

consent to a series of verbal interviews. Respondents included representatives from a variety ofleading server, storage, data communications, personal computer and telecommunications

industries in the US, China and Europe.

In addition to the questionnaire, each of the individuals contacted was sent an illustration

comparing 14 specific steps it takes to design a typical dc-dc regulator (the 14 steps identified intypical dc-dc design process were validated by over 150 engineers representing a variety of fieldsworldwide) with the 6 steps it was determined to take to design a PSiP/MicroModule/PwrSoC

configuration. The illustration describing the design flows for these two technologies was used as

a basis for the questions asked and is presented in the Table 1. The table presents a side-by-side

comparison between the two design flows discussed in this paper, along with an explanation ofeach step in the process.

Summary of Findings

The duration of the design process for the PSiP/MicroModule/PwrSoC design flow takes45.0% less man hours to complete than a dc-dc regulator down solution. (Man-hoursare defined as a combination of both gross design steps and design iterations)

The dc-dc regulator design flow is a much more complex process and with designiterations included, takes over 2.8 times as many steps to complete.


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PSiP/MicroModule/PwrSoc DC-DC Design Flow

1. Review Regulator Specification vs. requirement

If on Approve Vendor List (AVL), continue

If NOT AVL. Alternatives vs. Process of qualifying

new supplier/component

1. Review PSiP/MicroModule/PwrSoC Specification vs. requi rement

If on Approve Vendor List (AVL), continue

If NOT AVL. assess alternatives vs. Process of qualifying

new supplier/component

2. Select DC-DC Regulator device 2. Device Selection

3. Solution Analysis Hand and/or spreadsheet Analysis from datasheet

to obtain inductor (then Cin/Cout)

3. Look up Components-- Use Datasheet to select Cin,Cout,

small signal components

4. Select Inductors Verify AVL Status Pre-validate/Not Required

5. Select Capacitor (Input/Output) Pre-validate/Not Required

6. Simulate Power Stage/Input/Output Filter On-Line Device Simulation; Efficiency, Stress,Ripple

Pre-validate/Not Required

7. Analyze Control Design - compensation

network selection

Gain, Stability, (varying with compensation, error

amplifier, power stage)


8. Verify Time Domain Analysis/Simulation Line/Load Transient, Overshoot, Ripple, Soft-Start,

etc.


9. Schematic Finalized 8+ pages automatical ly generated from tools Pre-val idate/Not Required

10. Custom PCB Layout & Bill of Material Uses general rules/guidelines; most often deviate

from


11. Final BOM: Component Optimization

& Trade-offs

AVL status, cost, size, performance Pre-validate/Not Required

12. System Scope Creep; Requirement Change Space decrease, power increase, cost

decrease,

4. System Scope Creep; Requirement Change

13. PCB Design (Gerbers, untested?) Design constraints; design rules are often broken;Engineering judgment required

5. PCB Design using standard/tested design files;Engineering judgment applied

14. Prototype Testing Layout issues, unforeseen parasitics, power budget,

component variations, EMI

6.Prototype Testing

Testing and Qualification Efforts Complete

Typical DC-DC "Regulator" Design Flow

Testing and Qualification Efforts Complete

The most common answer for choosing a PSiP/MicroModule/PwrSoC was toaccommodate specific board space requirements and density issues.

Even with the use of todays web-based tools, it still takes an average of 464 man-hoursto complete a dc-dc regulator design flow vs. only 254 man-hours to complete a

PSiP/MicroModule/PwrSoC design. This is for a simple 5A regulator design flow, for amore complex design, the process could take 20-40% longer.

When asked about potential design issues: noise, parasitics, load change, stability andEMI, the responses from dc-dc regulator users and PSiP users were quite similar.

Table 1Typical DC-DC Regulator Design Flow vs .PSiP/MicroModule/PwrSoC Design Flow

Comparison

Source: Darnell Group


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Analysis of Survey Results

DC-DC Regulator vs. PSiP/MicroModule/PwrSoCDesign Flow Comparison

The first question asked of the respondents was to examine the illustration presented in Table 1and determine if these steps, as well as the sequence of steps, is correct for both design flows.

All of the respondents agreed that the design flows for both the typical dc-dc regulator andPSiP/MicroModule/PwrSoC configurations seemed reasonable and correct and acknowledged

that the implementation resulted in a 57% reduction in gross design flow steps. This is the only

question in the survey that resulted in a 100% positive response.

Although several participants stated that there are many different variations in a design flow that

could be used, they all agreed that the design flow sequence presented in the illustration wassolid. When pressed to expand on each step, none of the participants could identify any specific

instances where one of the steps presented could be left out or replaced.

The next question asked of each respondent was to estimate the number of man months/hours itwould take to complete the design flow for both dc-dc regulator and PSiP/MicroModule/PwrSoC

configurations. Each of the respondents answered somewhat differently, some measuring time in

months, some in weeks and some in man hours. It was determined that in order to make applesto apples comparisons among the answers, man hours would be used in all responses.

DC-DC Regulator vs. PSiP/MicroModule/PwrSoCMan- Hour Comparison

As indicated in Table 2, the man-hour responses for the two design flows varied somewhatamong participants, but were consistent overall, with the dc-dc regulator design flow estimates

recording a mean average of 464 man-hours to complete. The median average time recorded forthis design flow was 346 man-hours to completion. Each of the survey participants stressed that

the time to completion often depended on how many engineers were working on a project, how

fast or slow those engineers were, how many other projects they were working on, and were theyworking on a tight deadline.

Table 2DC-DC Regulator vs. PSiP/MicroModule/PwrSoC

Design Flow Total Man Hour Comparison

(Time Saved wi th Integrated Power Solution)

Mean Median

DC-DC Regulators Design Flow 464 346

PSiP/MicroModule/PwrSoC Design Flow 254 207

Time Saved 45.3% 40.2%


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A number of engineers also stated that the time estimate needed to take into account whether or

not the project was a re-freshing of a system already in use or the start of a new system from

scratch. Also important was the fact that some dc-dc regulator requirements were simple andsome were more complex. Almost all of the respondents mentioned that step 14 (prototype

testing) often took more time than expected and could be unpredictable in the early stages of

development, so additional time often had to be allotted for this step.

The estimated man-hours to completion for the PSiP/MicroModule/PwrSoC design flow was

found to be significantly lower than it was for the dc-dc regulator design flow. As illustrated in

Table 2 above, the average mean time to completion for this design flow is 254 man hours, witha median average time to completion of 207 hours. All of the participants in the study examined

the side-by-side design flow presented in Table 1 and concluded that the exclusion of steps 4

through 11 from the dc-dc regulator design flow resulted in a substantial decrease in both stepsand man hours. Overall, the first question in the survey indicated that the use of the

PSiP/MicroModule/PwrSoC design flow was expected to save an average of about 45.0% in man

hours per project. In contrast to the 57.0% figure referred to earlier, this man-hour percentage

takes into account not only the actual steps, but the number of design iterations needed for eachstep.

DC-DC Regulator vs. PSiP/MicroModule/PwrSoCComparison Man Hours per Step

One of the more informative parts of this survey was the breakdown of both man-hours per step

and percentage of time per step for both dc-dc regulator and PSiP/MicroModule/PwrSoC design

flows. Each of the participants was asked to make a comparison between the man-hours requiredto complete each of the two design flows. The results from this section allowed a comparison

between each step in both of the design flows to be directly compared and quantified. Most ofthe respondents initially gave a range in both hours and percentage for each of the steps, howeverafter some consideration, each was able to identify an average time for each step.

Step 14 prototype testing (for dc-dc regulators) was considered the most time-consuming portionof the design flow in both man-hours and percentage in both design flows. Most of the

participants indicated that prototype testing, layout, parasitics, power budget, component

variation, etc. takes up most of the time, and is where most of the repetition is needed. Almost allof the respondents stated that the time it took to complete this step often depended, among other

things, on the complexity of design. As a result, many of them provided a range in both man-

hours and percentages for this step.


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A key finding in this survey was that the total man-hours (155.2 ) required to complete step 14

prototype testing in the dc-dc regulator design flow exceeded the man-hours (112.8) in step 6

prototype testing for the PSiP/MicroModule/PwrSoC design flow by 38.0%. All of the man-hours totals included both gross design steps and all of the necessary design iterations for each

step. In addition, the survey responses also found that the last three steps for the dc-dc regulator

design flow exceeded the last three steps for the PSiP/MicroModule/PwrSoC design flow. Asindicated in the actual man-hour comparisons presented in Tables 3 and 4, the average mean time

it took to complete the last three steps system scope creep, PCB design and proto type testing

took 20.0% longer for the dc-dc regulator design.

This finding verified that the original side by side comparison was indeed valid and the reduction

in time using the PSiP/MicroModule/PwrSoC design flow was a significant factor in reducing

the number of man-hours.

The responses received from the survey also found that in actual man-hours, the first three steps

in the dc-dc regulator design flow review regulator specification vs. requirement, select dc-dc

regulator device and solution analysis are similar in man-hours to the first three steps of thedesign flow for the PSiP/MicroModule/PwrSoC review PSiP/MicroModule/PwrSoC, device

selection and look up components. (See Tables 3 and 4.) According to the responses in the

questionnaire, the first three steps for the dc-dc regulator design flow are expected to take a meanaverage of 48.2 man hours, while the first three steps in the PSiP/MicroModule/PwrSoC design

flow are expected to total about 54.7 man-hours, a difference of only 13.0%.

According to this analysis, the findings suggest that when comparing the dc-dc regulator to the

PSiP/MicroModule/PwrSoC design flow, most of the time saved using the latter design flow is a

result of two factors: removing steps 4 through 11 of the dc-dc regulator design and the reductionin prototype testing. This is illustrated in a percentage comparison between Graphs 1 and 2

presented in the following pages.

In addition to the man-hour estimation, all of the participants in the survey were asked to break

down the steps for both design flows by percentage. Specifically, what percentage of the overall

design time is taken at each step of the process. Again, the design time includes all of the

necessary iterations for each specific step. The results from this portion of the survey arepresented in Table 5 and Table 6.


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Table 5DC-DC Regulator Design Flow Man Hours

Percentage Breakdown per step(Design Iterations Included)

Average Median1. Review Regulator Specification vs. Requirement 4.3% 5.0%

2. Select DC-DC Regulator device 3.0% 3.0%

3. Solution Analysis 3.3% 3.0%

4. Select Inductors 2.0% 2.0%

5. Select Capacitor -Input/Output 3.7% 3.0%

6. Simulate Power Stage/Input/Output Filter 4.3% 4.0%

7. Analyze Control Design - compensation network selection 5.3% 5.0%

8. Verify Time Domain Analysis/Simulation 4.7% 5.0%

9. Schematic Finalized 6.0% 6.0%

10. Custom PCB Layout & Bill of Material 6.3% 6.0%11. Final BOM: Component Optimization & Trade-offs 5.3% 5.0%

12. System Scope Creep; Requirement Change 8.0% 8.0%

13. PCB Design 10.0% 10.0%

14. Prototype Testing 33.7% 33.0%

Table 6PSiP/MicroModule/PwrSoC

Design Flow Man Hours PercentageBreakdown per step

(Design Iterations Included)

Average Median

1. Review PSiP/MicroModule/PwrSoC Design Flow 7.3% 7.0%

2. Device Selection 7.0% 6.9%

3. Look up Components 7.3% 8.0%

4. System Scope Creep; Requirement Change 17.7% 18.0%

5. PCB Design using standard/tested design files 16.3% 16.0%

6. Prototype Testing 44.3% 44.0%


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1. Review Regulator

Specification vs.

Requirement 4.3%

2. Select DC-DC Regulator

device 3.0%

3. Solution Analysis 3.3%

4. Select Inductors 2.0%

5. Select Capacitor -

Input/Output, 3.7%

6. Simulate Power

Stage/Input/Output Filter

4.3%

7. Analyze Control Design

- compensation network

selection 5.3%

8. Verify Time Domain

Analysis/Simulation 4.7%

9. Schematic Finalized

6.0%

10. Custom PCB Layout &

Bill of Material 6.3%

11. Final BOM:

Component Optimization

& Trade-offs 5.3%12. System Scope Creep;

Requirement Change

8.0%

13. PCB Design 10.0

14. Prototype Testing

33.7%

Graph 1DC-DC Regulator Design Flow Man Hours

Percentage Breakdown per step


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1. Review RegulatorSpecification vs.

Requirement

4.3%

2. Select DC-DC

Regulator device

3.0%

3. Solution Analysis

3.3%

Steps 4 to 11

37.7%

12. System Scope Creep;

Requirement Change

8.0%

13. PCB Design

10.0%

14. Prototype Testing

33.7%

Graph 2DC-DC Regulator Design Flow Man Hours

Percentage Breakdown per step(With Steps 4 thru 11 Removed)


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In both design flows, prototype testing takes up the largest percentage of time. In the dc-dc

regulator design flow, prototype testing (step 14) was expected to account for about 33.7% of the

design time, while in the PSiP/MicroModule/PwrSoC (step 6) it accounts for a little over 44.0%.(The contrast in man hours can be seen in Graph 3) This is consistent with the man-hour findings

presented earlier in this section, indicating that the last step, prototype testing, is expected to take

up the largest amount of time in both configurations.

Graph 3DC-DC Regulator vs. PSiP/MicroModule/PwrSoC

Design Flow Man Hour Comparison

Man-Hours

As illustrated in Graph 1, aside from the prototype testing in step 14, the rest of the steps in thedc-dc regulator design flow are expected to be fairly well distributed. With the exception of step

4 (selecting the inductors) and step 5 (selecting the capacitors) which all the participants agreed

took very little time, the average mean percentage for the other steps ranged from 3.0% and10.0% of the time.

As illustrated in Graph 3, in contrast to the dc-dc regulator design flow, the man-hour breakoutby hours for the PSiP/MicroModule/PwrSoC design is much more concentrated. As stated

earlier, the percentage of time that goes into the prototype testing step makes up over 44.0% of

the design process. In fact, according to the respondents, the last three steps system scope

creep, PCB design and prototype testing make up over 78.0% of the total design process.


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Mean

1. Review Regulator Specification vs. Requirement -

2. Select DC-DC Regulator device -

3. Solution Analysis -

4. Select Inductors -

5. Select Capacitor ( Input/Output) -

6. Simulate Power Stage/Input/Output Filter -

7. Analyze Control Design - compensation network selection 2.08. Verify Time Domain Analysis/Simulation 2.0

9. Schematic Finalized 1.3

10. Custom PCB Layout & Bill of Material -

11. Final BOM: Component Optimization & Trade-offs -

12. System Scope Creep; Requirement Change 1.0

13. PCB Design (Gerbers, untested?) 2.0

14. Prototype Testing 2.7

Most of the respondents stated that the removal of steps 4 thru 11 from the dc-dc regulator

design reduces the amount of time until completion considerably. This causes the man-hour

percentages for the steps in the PSiP/MicroModule/PwrSoC design flow to increase becausethere are now fewer steps to complete.

Design Flow Iteration Process

Each of the participants in the survey was presented with an illustration of Table 7 (without the

Column mean) and asked which of the steps listed do they typically face multiple iterations inthe design process, and of those steps, where does it happen most often. Table 7 and Table 8

identify the steps where repeated design flow iterations are expected to occur in both the dc-dc

regulator design and PSiP/MicroModule/PwrSoC design. The lines to the left of each of thefollowing tables indicate how far back in the design process each step needs to go if it has to be

repeated.

Table 7

Typical DC-DC RegulatorDesign Flow Iterations

The responses to this question varied among the participants and like many of the answers in thesurvey, most respondents provided a range of answers which depended on a number of factors

specific to each design. For the dc-dc regulators, it was generally accepted that step 14, prototype

testing, had to be repeated most often, because at this stage of the design process, everything isbeing tested for. The average number of repetitions for this step was 2.7 times, however more

than one engineer questioned in this survey stated that after repeating a process 3 times you are

done and you have to re-start the entire design process over. If there are any changes requiredbeyond this number of iterations, you have to go back and change some of the specifications.


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Mean

1. Review PSiP/MicroModule/PwrSoC Design Flow -

2. Device Selection -

3. Look up Components -

4. System Scope Creep; Requirement Change 1.05. PCB Design using standard/tested design files 1.2

6. Prototype Testing 1.5

The same answer was given for step 6 prototype testing in the PSiP/MicroModule/PwrSoC

design flow process. As illustrated in Table 8, the prototype testing step for this design flow

recorded a mean average of 1.5, the largest in this design flow. Again, this step along with thepre-validated steps 4 through 11, which were removed, contributed to the overall reduction in the

design time compared to the discrete regulators. Step 5, PCB design, recorded a mean average of

1.2 in the PSiP/MicroModule/PwrSoC design flow process.

Table 8Typical PSiP/MicroModule/PwrSoC

Design Flow Iterations

A comparison of Table 7 and Table 8 clearly indicates that the dc-dc regulator design flow notonly requires more steps to completion, the process also includes several more steps that may

need to be repeated. In fact, a number of engineers stated that although there are often some

designs that fit the first time out of the gate, there are often complexities in designs that mayrequire a number of steps to be repeated throughout various stages of the process. For the dc-dc

regulator design flow, this can be seen in Table 7, which shows multiple potential design

iterations occurring at step 7 analyze control design, step 8 verify time domainanalysis/simulation and step 9 where the schematic is finalized.

According to most of the participants, this part of the survey process identified the key

advantages of using a PSiP/MicroModule/PwrSoC design flow over a dc-dc regulator. Asillustrated in Table 1, presented earlier in this report, it has 57.0% fewer gross steps and as a

result, does not require as many design changes and repeated steps. In comparison to the number

of repeated steps necessary for the dc-dc regulator design flow, respondents to this surveyestimated that the number of repeated design iterations for the PSiP/MicroModule/PwrSoC

design flow to be considerably less, depending on the complexity of the design, which

contributes substantially to a lower time to completion.


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Typical DC-DC Regulator Design Flow Iterations Steps PSiP/MicroModule/PwrSoC Design Flow Iterations Steps1. Review Regulator Specification vs. Requirement 1 1. Review PSiP/MicroModule/PwrSoC Design Flow 1

2. Select DC-DC Regulator device 1 2. Device Selection 1

3. Solution Analysis 1 3. Look up Components 1

4. Select Inductors 1 Pre-validated -

5. Select Capacitor ( Input/Output) 1 Pre-validated -

6. Simulate Power Stage/Input/Output Filter 1 Pre-validated -

7. Analyze Control Design - compensation network selection 2.0 Pre-validated -

8. Verify Time Domain Analysis/Simulation 2.0 Pre-validated -

9. Schematic Finalized 1.3 Pre-validated -

10. Custom PCB Layout & Bill of Material 1 Pre-validated -

11. Final BOM: Component Optimization & Trade-offs 1 Pre-validated -

12. System Scope Creep; Requirement Change 1.0 4. System Scope Creep; Requirement Change 1.0

13. PCB Design (Gerbers, untested?) 2 5. PCB Design using standard/tested design files 1.2

14. Prototype Testing 2.7 6. Prototype Testing 1.5

Total 19.0 Total 6.7

Table 9

Actual Steps inc lud ing Design Flow IterationsTypical DC-DC Regulator vs.

Typical PSiP/MicroModule/PwrSoC

The total number of estimated actual steps needed, including design iterations, for both a typicaldc-dc regulator design flow and the PSiP/MicroModule/PwrSoC design flow are presented in

Table 9. It shows that the dc-dc regulator design flow requires 2.8 times as many steps to

complete as the PSiP/MicroModule/PwrSoC design flow does.

Design Flow Issues

The respondents to this survey were asked how often they faced unexpected design issues such

as noise, parasitics, load change, stability and EMI. They were then asked to rank each of these

issues from 1 to 10, with 1 being least concerned about the specific design issue and 10 beingvery concerned. The rankings presented in this section are qualitative rankings and based on

the perceptions of the respondents. Overall, the concerns expressed for both technologies was the

same. However, the higher rankings assigned to the PSiP/MicroModule/PwrSoC design flowwas a result of an un-familiarity with the technology.

The results for this are presented in Tables 9 and 10. Participants stated that unexpected designissues come up quite often and many times its due to things that they dont necessarily control

such as timing issues or ramp rates or voltage levels. Overall, the responses received concludedthat the concerns were relatively moderate for both design flows.

According to the survey, participants were the least concerned about EMI due to the low voltage.

Participants stated that EMI was not much of an issue because the filtering kept it pretty well

contained and controlled. Conductive noise, which all the participants agreed could creep in,ranks the lowest in concern for the dc-dc regulator design flow. Participants agreed that noise

occurred in both design flows and it is more related to the control loop. (Several engineers


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observed that if the layout was not designed as well as it could be, the controller loop can be

impacted by noise.) Noise ranked much higher for the PSiP/MicroModule/PwrSoC design due to

the smaller size and proximity to the other components.

Table 10

Typical DC-DC RegulatorDesign Flow Issues

Mean

Noise 3.7

Parasitics 5.0

Load Change 2.7

Stability 4.0

EMI 3.7

Table 11PSiP/MicroModule/PwrSoC

Design Flow Issues

Mean

Noise 5.3

Parasitics 6.0

Load Change 5.3

Stability 4.0

EMI 5.0

For the PSiP/MicroModule/PwrSoC design flow, parasitics caused the most concern with aranking of 6.0. In fact, parasitics ranked as the highest level of concern for both design flows.

The ranking in load change between the two design flows was where the largest difference was

observed. As illustrated in Graphs 4 and 5, for the dc-dc regulator design, load change recordedjust a 2.7 in concern, while for the PSiP/MicroModule/PwrSoC, design flow load change ranked

a 5.3, the second-highest mean average ranking recorded in this section

Engineers in this survey were concerned specifically about highly-dynamic loads and transient

conditions. As a result of their lack of experience with PSiP/MicroModule/PwrSoC solutions

they were less confident in the dynamic stability of those converters. They expressed greater

confidence (resulting from personal experience) in designing a DC-DC Regulator solution whendealing with highly-dynamic loads and transient conditions. The respondents expect that these

perceptions between the two design flows will persist until a body of experience has been

gathered relative to the newer PSiP/MicroModule/PwrSoC solutions. This concern relative toPSiP/MicroModule/PwrSoC solutions had the impact of increasing the time estimates (the

estimates were called more conservative) for the PSiP/MicroModule/PwrSoC solution design

flow.


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Web-Based Tools

Each of the participants was asked how helpful web-based tools were in providing a schematic

layout that works efficiently. All of the responses regarding the use of these tools were positive,

with a number of individuals stating that the use of the available web-based tools help speed up

the design. Although they all stated that the tools allowed them to reduce the amount of actualtesting, they were quick to point out that although the simulation tools are good, they cannot do

everything, and using it will not necessarily give you the same results as you got from testing

your prototype. The need for web-based tools can be seen in a comparison of actual steps, whichinclude design flow iterations between a dc-dc regulator and a PSiP/MicroModule/PwrSoC

design flow, presented in Table 9. As stated earlier, the dc-dc dc regulator design requires 2.8

times as many actual steps when design iterations are included and despite the use of web-basedtools, the number of actual design steps adds to the complexity of the process in this design. This

is an area where the PSiP MicroModule/PwrSoC design flow has a big advantage. It has fewer

steps and the areas that require the use of web-based tools in the dc-dc design flow have already

been pre-validated thus already completed.

Conclusions

All of the participants in the study examined the side-by-side design flow presented inTable 1 and concluded that the exclusion of steps 4 through 11 from the dc-dc regulatordesign flow resulted in a substantial decrease in both steps and man hours for a PSiP/

MicroModule/PwrSoC based design.

The survey found that the total man-hours (155.2 ) required to complete step 14 prototypetesting in the dc-dc regulator design flow exceeded the man-hours (112.8) in step 6

prototype testing for the PSiP/MicroModule/PwrSoC design flow by 38.0%.

The findings suggest that when comparing the dc-dc regulator to thePSiP/MicroModule/PwrSoC design flow, most of the time saved using the latter design

flow is a result of two factors: removing steps 4 through 11 of the dc-dc regulator design

and the reduction in prototype testing.

For the dc-dc regulators, it was generally accepted that step 14, prototype testing, had tobe repeated most often, because at this stage of the design process, everything is being

tested for. The average number of repetitions for this step was 2.7 times. While for thePSiP/MicroModule/PwrSoC design flow it was 1.5 times.

Overall, the concerns expressed for design issues in both technologies was the same.However, the higher rankings assigned to the PSiP/MicroModule/PwrSoC design flow

was a result of an un-familiarity with the technology.


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All of the respondents stated that price was the first concern since PSiPs are at aperceived premium to dc-dc regulators. So in terms of just price, the choice will always

default to the discrete regulators. If an existing inventory cannot accommodate a specific

design for whatever reason, a PSiP/MicroModule/PwrSoC design is an option.


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Warranty Disclaimer:All information used in the preparation of this report was obtained from

sources believed to be reliable at the time the information was collected. Darnell Group, its

employees, its agents, and assignees have exercised their best efforts in preparing this report.Darnell Group extends no warranties with respect to this information and shall bear no liability

whatsoever to the report recipient or to any other party as a result of the use of this report or the

information contained herein.

Documents

Ease of Design Comparison