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Institute for Communication Technologies and Embedded Systems
Easy Multicore Programming
using MAPS
Jeronimo Castrillon, Maximilian Odendahl Multicore Challenge Conference 2012
September 24th, 2012
© J. Castrillon. Multicore Challenge 2012 2
Outline
Motivation
MAPS Highlights
Demo Introduction
Summary
© J. Castrillon. Multicore Challenge 2012 3
MPSoCs and the Productivity Gap
Multi-Processor Systems on Chip are a reality
Increased HW and SW complexity
The productivity gap: Requirements double every 10
months, HW/SW productivity every 2 years (Ecker, Mueller,
Doemer, 2008)
Need better support for SW development in the MPSoC era
SoC Consumer Portable Design
Complexity Trends (ITRS 2007)
Fujitsu, MPSOC 2009
© J. Castrillon. Multicore Challenge 2012
Programming: Uni-processor vs. MPSoC
4
Uni-processor ARM7
Sequential
C Program
ARM C Compiler
Debugging
- Simulator
- Hardware
MPSoC
Sequential
C Program
Task Partitioning
Mapping/Scheduling
Code Generation
Debugging
- Virtual Platform and/or Hardware
- Low Visibility
- Parallel Debugging
Time
Processor
SW
Develo
pm
en
t C
ycle
Memory
Interconnect
© J. Castrillon. Multicore Challenge 2012
Compilers and Software Productivity
Lack of “the compiler” in the programming flow for
MPSoCs largely contributes to the productivity loss
New tasks exposed to programmer, e.g., mapping and
scheduling, with non-functional constraints, e.g., real time
5
Applications,
Programming
Models
APIs, OS,
ISA,
µ-architectures
Compilers
Applications,
Programming
Models?
APIs, OS,
ISA,
µ-architectures
APIs, OS,
ISA,
µ-architectures
APIs, OS,
ISA,
µ-architectures …
Manual
Process
© J. Castrillon. Multicore Challenge 2012 6
Outline
Motivation
MAPS Highlights
Demo Introduction
Summary
© J. Castrillon. Multicore Challenge 2012
Overview of MAPS – a Multicore Compiler
Features/Highlights
Compilation framework for multi-core systems (heterogeneous
or homogeneous) for SW developers
Light-weight C extension for parallel programming
C-based source-to-source translation to leverage the existing
C compiler technology for multi-core processing elements
Retargetability towards different multi-core platforms
Sequential C partitioning facilities
Advanced scheduling and mapping of single and multiple
parallel applications
Collaborative in working with state-of-the-art ESL (Electronic
System Level) design tools and other silicon vendor SW tools
7
© J. Castrillon. Multicore Challenge 2012
Programming Models
Parallel Programming Models have
evolved for long. Yet there is no winner.
Thoughts on Programming Model
Needs to be leveraged by compiler for
code generation (correctness).
Needs to have good properties for
optimizations such as parallelism
extraction and intelligent
mapping/scheduling (efficiency).
Practical considerations
Domain-specific: embedded
systems (wireless, multimedia, etc.)
C dominance is unchallenged.
(not addressed in this talk)
8
Programming
Model
© J. Castrillon. Multicore Challenge 2012
Parallel Dataflow Programming
Process Networks (PN)
Processes
Independent threads of execution
Communication via channels
Channels
Unidirectional first-in first-out
Kahn Process Networks (KPN)
Blocking read semantics
9
Example: Run Length En/Decoding (RLE/D)
RLE is a simple data compression technique used
in e.g. fax machines. Data are encoded as {count,
data_value}. RLD is the inverse.
RLE example: AAAABBCCCCCDDD 4A2B5C3D
PN KPN
STOP
RLD
{4, A} {A, A, A, A}
{B, B} {2, B}
SDF
© J. Castrillon. Multicore Challenge 2012
Mapping and Scheduling Flow
Architecture model for
retargetability
Tracing to handle KPN
expressiveness
Heuristics for mapping
both computation and
communication (real-time
aware)
Code generation for
productivity boost
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Application Arch. Model Constraints &
Config
Parsing, profiling, tracing, sequential
performance estimation
M&S heuristics & Trace replay
Code Generation
RISC1 DSP2 DSP1
RISC2 DSP3 HW
© J. Castrillon. Multicore Challenge 2012
Mapping and Scheduling Process
Application tracing:
Graph representation & DAG mapping algorithms
([IEEE Trans. Industrial Informatics 2011, DAC 2012])
11
To PEx
To MEMy
© J. Castrillon. Multicore Challenge 2012
MAPS Backends
12
Applications,
Programming
Models?
APIs, OS,
ISA,
µ-architectures
APIs, OS,
ISA,
µ-architectures
APIs, OS,
ISA,
µ-architectures …
Manual
Process
Application spec.
C/CPN
MAPS Compiler
SW Functional Verification:
(Pthreads, Synopsys MCO) Virtual Platforms:
(Synopsys PA + Debug
scripts)
Actual HW:
(TI OMAP/Multi-core
DSP families and other
MPSoCs)
Compiler infrastructure:
Source-to-Source based on Clang: Retain original
code structure
Transformations at the AST level (Abstract Syntax
Tree): Flexible, extensible, retagetable
Configuration files (scripts, makefiles): Ready to
deploy solution to the target platform
© J. Castrillon. Multicore Challenge 2012 13
Outline
Motivation
MAPS Highlights
Demo Introduction
Summary
© J. Castrillon. Multicore Challenge 2012
MAPS Tool Demonstration
Presentation of MAPS IDE
Analysis and mapping of a radar application for the TI-
C6678 platform (Keystone architecture)
14
KPN Profiling (computation and communication)
KPN Mapping and Scheduling (iterative, manual/automatic, constrained)
© J. Castrillon. Multicore Challenge 2012 15
Outline
Motivation
MAPS Highlights
Demo Introduction
Summary
© J. Castrillon. Multicore Challenge 2012 16
Summary
Today’s software and hardware complexity requires
powerful new tools
Example: Single-processor compilers
MAPS: An MPSoC compiler
C + Abstract programming model
Automatic mapping and scheduling flow
Robust code generation for state-of-the-art MPSoCs
Looking forwards to seeing you during the
demo session!
Institute for Communication Technologies and Embedded Systems
Thank you
17