EC4101

Tutorials

EC4101 DIGITAL ELECTRONICSModule 1 :

1. Define (a) Product -of- sums (POS) form (b) Sum-of-products(SOP) form.

2. Express F = AB + CD as POS & SOP expressions.

3. What is the difference between canonical form and standard form? Which form is obtained from a truth table?

4. Define minterms and maxterms for (i) three variables and (ii) four variables.

5. Consider a 3-bit binary no. X3 X2 X1 where X1 is LSB. Design a circuit that will determine whenever the binary is greater than 4.

6. Explain Karnaugh map (K-map) and its applications.

7. Simplify the following Boolean functions to minimum number of literals.

(a)ABC+ABC+ABC

(b)ABC+ABC+ABC+ABC

(c) (XY)+X+(Y+Z)

8. Find the complement of the expression

Y=ABC+ABC+ABC+ABC

9. Show how NAND gates can be used to build the logic circuit for

(i)Y = A + BC

(ii)Y = AB + CD

10. Repeat Q. 9 for NOR gates.

11. Convert the following to other canonical form

(i)F = ( (1, 5, 6 )

(ii)F = ( (1, 5, 7, 8, 14, 15)

12.(i) Prove that the sum of all minterms of a Boolean function of 3 variables is 1.

(ii) Prove that the product of all minterms of a Boolean function of 3 variables is 0.

13. Minimize the following switching functions using Karnaugh Map. List all prime implicants and essential prime implicants (nonredundant group).

(i) F = ( (1, 3, 5, 6, 7)

(ii) F = ( (0, 1, 3, 6, 14, 15)

(iii) F = ( (0, 1, 2, 5, 7, 10, 12)

(iv) F = ( (2, 7, 8, 10, 15)

(v) F = ( (2, 7, 9, 14, 15) + (d (0, 3, (10)

(vi) F = ( (5, 7, 9, 10, 15) + (d (1, 3, 11, 14)

14.Simplify the following noncanonical expressions using K map.

(i) F = V.W + V.W.Y + V.W.Z

(ii) F = Y.Z + W.X.Y + W.X.Y + X.Y.Z

15.Simplify the following Boolean functions by Quine McCluskey Method.

(i) F = ( (1, 3, 5, 8, 10, 14)

(ii) F = ( (1, 9, 10, 16, 20) + (d (14, 29, 30)

(iii) F = ( (2, 8, 9, 19, 25, 27) + (d (28, 30).

(iv) F = ((0, 8, 14, 19, 31)

16. Simplify the following Boolean function in SOP from by means of a

four variable map. Draw the logic diagram with

(a) OR-AND gates; (b) NOR gates.

F(w, x, y,z) =(2,3.4,5,6,7,11,14,15)

17. Simplify the following Boolean function in SOP from by means of four variables map. Draw the logic diagram with (a) AND-OR gates;(b)NAND gates .

F(w, x, y,z) =(0,2,8,9,10,11,14,15)

18. Develop SOP & POS expressions for F1, F2, & F3 in Table Q.17 and draw the Karnaugh maps.

InputsOutputs

XYZF1F2F3

000001

001011

010111

011110

100100

101010

110111

111101

19. Design a combinational logic circuit that has 10 inputs, numbered 0 through to 9, and one output. The output is required to go HIGH whenever any one, or more, of the inputs numbered 2, 5, 6 or 7 go HIGH. The circuit should be free of static hazards.

20. Solve using a 3-variable map:

a) f = ABC +ABCD+ABCD+ABC+ABC

b) f = m(0,1,3,5,7,11,12,15)

Module 2 :

1 Give logical design of 2x4 decoder. Use the same to realize half adder.

2 Show how a full adder can be converted to a full subtractor with the addition of one inverter circuit.

3 One full adder can be realized from two half adder and OR gate. Verify

from 1st principle.

4 Repeat Q. 22 for one full subtractor.

5 What are the drawbacks of conventional full adder? How these are minimized in carry look ahead adder?

6 Give logical design of decoders as below:

(i)3 x 8,

(ii)4 x 10

(iii)5 x 32

7 Give logical design of following encoders.

(i)4 x 2

(ii)10 x 4

(iii)16 x 4

8 Design a 4-line to 2-line priority encoder.

9 Realize the following Boolean functions using appropriate multiplexer.

F = ( (0, 1, 4, 5, 7)

F = ( (0, 1, 3, 6, 15, 21, 25)

10 Design a binary to Gray code converter for 4-bit operation.

11 Design BCD to excess-3 converter using

(a)Logic gates (b)binary adder

12 Design a 1x40 demultiplexer using BCD to decimal decoders.

13 Explain with diagram

a)Decimal adder(b)Decimal subtractor

14 Use BCD adders for n digit decimal number.

15 Repeat Q. 33 for BCD subtraction.

16 Design 7 segment display & explain its operation. Give logical design of special decoder used.

17 Design 3-bit parity bit generator and checker for even and odd parity.

18 What are uses of Binary Codes?

19 (i)Convert to Binary if Gray code is 11101.

(ii) Convert to Gray if Binary is 1001

20 How True complement/zero one device is realized?

21 Give logical design

1s complement generator

2s complement generator

22 Repeat Q.35 using Binary adders.

23 How excess 3 is converted to BCD by the use of logic gates.

24 Repeat Q.37. by use of Binary adders.

25 Represent decimal numbers +29 and 37 by following methods

(i) Signed Magnitude

(ii) Signed 1s complement

(iii) Signed 2s complement

25.Add following by signed Magnitude Method

(i) +28 and 19

(ii) +29 and +23

(iii) +22 and 30

26.Repeat Q.44 by method of

(i) Signed 1s complement

(ii) Signal 2s complement

27.Add by BCD method

(i) +297 and +359

(ii) 467 and +376

(iii) +487 and 359

Module 3 :

1Explain the parameters used to characterise logic families.

2Describe the differences between saturated & unsaturated logic.

3Explain the operation of TTL NAND and NOR gates.

4Give two advantages and one disadvantage of totem-pole output arrangement.

5Explain why an open TTL input acts as a HIGH.

6What is meant by multiemitter transistor?

7 The propagation delay time for a TTL gate is td = 5 ns, tf = 10 ns, ts = 15 ns and tr = 7 ns. Draw the output waveform when the device is turned OFF and ON

9 Define each of the following: VOH , VIL, IOL, IIH, tPLH, tPHL, ICCL, ICCH.

10 Prove that the two open- collector TTL inverters when connected together produce the NOR function.

11 Show the circuit of a 4 input NAND gate using CMOS transistors.

12 Explain all 2-input basic gates using standard CMOS logic.

13 Which CMOS series is pin-compatible with TTL?

14 Which CMOS series is electrically compatible with TTL?

15 Which CMOS series is functionally equivalent to TTL?

16. Let all inputs in the open collector TTL gate of figure shown be in the HIGH state of 3 V

a Determine the voltage in the base, collector and emitter of all transistors

b Determine the minimum hfe of Q2 that ensures that this transistor saturates

c Calculate the base current of Q3

d Assume that the minimum hfe of Q3 is 6.18. what is the maximum current that can be tolerated in the collector to ensure saturation of Q3?

e What is the minimum value of RL that can be tolerated to ensure saturation of Q3?

17. What logic family combines the best features of CMOS and bipolar logic?

18. What factors determine CMOS fan-out?

19. Describe the operation of a CMOS bilateral switch (transmission gate).20. What are the various ways to interface TTL to high-voltage CMOS?21. Discuss advantages & disadvantages of TG logic over conventional CMOS design.

22. (a) Realize XOR & XNOR logic using TG.

(b) Realize using TG.

23. Design a 4 x 1 MUX using CMOS TG.

24. Explain pass transistor logic & complementary pass transistor logic.

25. Implement all basic 2- input gates using NMOS pass transistors only.

26. Implement NAND & XOR gate using CPL design.

27. Compare static versus dynamic CMOS gates.

28. How dynamic CMOS gates provide smaller propagation delay & lesser chip area?

29. Implement the function by dynamic CMOS design.

30. Discuss Ratioed logic & use it to implement the function .

31. Explain precharge evaluate logic.

32. Explain Domino CMOS logic & use it to realize the function Y = A + (B + C).

33. Discuss Differential CMOS design & use it to implement the XOR gate.

Module-4:

1 What are the differences between combinational and sequential logic circuits?

2 Explain following with diagram:

(i)Clocked SR F/F (ii)Clocked J.K. F/F

(iii)Clocked D F/f(iv)Clocked T F/F

3 Repeat Q.52 to positive and negative edge triggering.

4 Explain the role of present and clear in FLIP-FLOPS.

5 Construct the excitation table and write the characteristic equations for the following FLIP-FLOPS:

(i)S-R F/F(ii)J-K F/F(iii)T F/F

6 What is race ground condition in J-K F/F? Show how it can be overcome in Master-Slave J-K F/F.

7 Convert an S-R F/F to a J-K F/F waning excitation table.

8 Explain what you understand by a register. What is buffer register?

9 Explain the working of a serial-in-serial out shift register with J-K F/F.

10 Repeat Q.59 for parallel-in-parallel out shift register.

11 Explain with waveform the operation of shift left and shift right register.

12 Explain with diagram the working of ripple counter.

13 Describe a 3-bit asynchronous up counter using J-K F/Fs.

14 Repeat Q.63 for down counter.

15 Design asynchronous decade up/down counter.

16 Design asynchronous mod-4 up counter with skipping state 3.

17 Draw a logic diagram for a ring counter and explain its working with the help of waveforms of input and output.

18 Design synchronous mode-8 up counter.

19 Repeat Q.68 for down counter.

20 Design synchronous counter with J-K F/F with state diagrams given below:

(i)0(1(2(3(0

(ii)3(2(1(3

(iii) 1(2(3(1

21 For the state diagram given below, obtain the state table and design the cuit using J-K F/Fs.

22Repeat Q.21 for the following state diagram.

1/1

23.Design a decade counter to count in the Excess-3 code sequence using J-K F/Fs.

Module- 5:

1 Draw the circuit of a collector coupled monostable multivibrator (Explain its operation). Show that the pulse width is given by T = ( ln 2 = 0.69 RC.

2 Draw the waveform at each base & collector for the collector coupled monostable multivibrator and obtain the expressions for

stable state and quasi-stable state for voltages and currents.

3 Compute the voltage levels for the waveforms in part (a) for the circuit shown in figure 1. Silicon transistors are used with Rb = 200 ohm and hFE = 30. Also calculate the pulse width.

4 Draw a circuit using CMOS NOR gates for monostable multivibrator, with the help of waveforms explain its operation. Write the expression for the pulse width T. Repeat part (a) using CMOS NAND gates.

5 Draw a circuit for CMOS NOR astable multivibrator. Using the idealized waveforms explain its operation and write the expression for total time period T = T1 + T2.

(b) Repeat part (a) using CMOS NAND gates.

6 (a) Using 555 timer chip, draw the circuit for the astable multivibrator. With the help of the waveforms explain its operation. Derive the expressions for the time period T = T1 + T2 and the duty cycle.

(b) Argue that the time period is independent of VCC.

7 Design a monostable multivibrator using 555 timer chip for pulse width equal to 500 (sec. (Hint: Find practical values of R & C).

(b) For astable multivibrator using 555, if Ra = 10K and Rb = 20K. Calculate the charge (T1), and discharge (T2), times and the frequency of the AMV. Calculate the duty cycle of the output waveform.

8 Using n-p-n transistors draw the circuit for an emitter coupled Binary or Schmitt trigger. Explain the operation along with the possible states of Q1 and Q2; the condition on loop gain; the voltages V1 and V2 and the transfer characteristic. How does it differ from the Eccles-Jordan bistable multivibrator

9 Explain the hysteresis loop and hysteresis range associated with the Schmitt trigger. How can the hysteresis voltage VH be reduced in the emitter coupled Schmitt trigger? Obtain the expressions for V1 and V2.

10 Explain how an Schmitt trigger can be used (i) as a comparator (ii) as a squaring circuit, (iii) as a flip-flop

11 Explain the behaviour of commutating capacitor in bistable multivibrator?

12 Determine the period and frequency of oscillation for an astable multivibrator with component values R1 = 2K Ohms and R2 = 10K Ohms, C1 = 0.01 F and C2 = 0.05 F.

13 Determine the value of capacitor to be used in an astable multivibrator to provide a train of pulse 2 sec wide edge at a repetition of 100K Hz if R1 = R2 = 20K Ohms. Use above figure.

14 How is Schmitt Trigger different from a multivibrator? Explain lower and upper triggering voltages in a Schmitt Trigger.

Module 6 :

1 What is PROM? Describe various methods, which can be used to erase a PROM.

2 Explain the working of a static MOS RAM and describe the major difference between static and dynamic RAM.

3 Using logic diagrams explain the differences between a PLA and a PAL.

4 Realize the following Boolean equation with a PLA.

i. A = xyz + xyz,B = x + yz

5 Explain the following:

i. (a)EPLD

(b)FPGA

6 Implement the logic function f=ABC+ABC on a 34 PAL.

7 Implement the logical functions F1= AB+BC and F2=AC+ABC using a PAL.

8 Implement a full-adder using a PLA.

9 Draw a PAL that provides the exclusive-OR function.

10 List some advantages gained by using a PLD to implement a digital design rather than a no. of SSI/MSI devices.

Module 7 :

1 Explain the differences between :

a Static & Dynamic memories

b Volatile and Non Volatile memories

c Bipolar & MOS memories

d Random access and read only memories

e Semiconductor and magnetic memories

2 Explain briefly the different type of ROMs

3 Explain different types of fuse technologies that are used in PROM

4 Explain why and EPROM is or is not a volatile memory

5 What are the advantages of an EEPROM oven an EPROM

6 What is a RAM? Draw and explain he circuit of a typical cell of bipolarRAM

7 Describe the input conditions needed to read a word from a specific RAM address location

8 How does a static RAM cell differ from a dynamic RAM? What are the advantages of dynamic RAM over static RAM

9 A certain memory has a capacity of 16 K x 32. How many words does it store? What is the number of bits per word? How many memory cells does it contain?

10 How many 16 K x 1 RAMs are required to achieve a memory word capacity of 16 K and a word length of 8 bits?

11 To expand the 16 K x 8 memory to a 32 K x 8 organisation, how many more 16 K x 1 RAMs are required?

12 What is the hex address range for 4 K x 8 ROM with hex addresses starting from 6000H

13 How many memory locations are there for address values from C000 to C3FF?

14 A certain memory stores 8K sixteen bit words. How many data input and data output lines does it have? How many address lines does it have? What is its capacity in bytes?

15 A ROM has 11 address lines and 8 data lines. Calculate

a The number of bits stored

b The organisation of the memory

16 Figure below shows the basic block diagram of 1024 x 1 RAM. Draw a diagram to show how four such RAMs could be connected to give a 1024 x 4 memory.

17 a) A ROM has 12 address lines. Calculate the number of memory locations

b) A ROM is organized as 8 K x 8. List the function of the necessary IC

pins. What is the minimum number of pins required?

c) A 64 bit square memory matrix is addressed by the binary number

110100. In which row and in which column is the wanted location?

18 a) A RAM has 4096 addressable locations. How many address pins does

it have? If there are four date input/ output pins what is the organization

of the RAM? What other pins are also required?

b)Explain the functions of the CS and R / W pins on a RAM chip.

Why does a ROM not have an R / W pin? Why is a decoder employed

in the addressing of a location in both a RAM and a ROM?19 Draw a ROM to implement the Boolean functions

F = ABCD + ABCD + ABCD + ABCD

G = AB + AB

Where letters in bold denotes complement

20 A DRAM has inputs CS (chip select), OE (output enable), WE (write enable). Write down the truth table showing the functions of the device

21 Briefly state the differences between

(a)SRAM, DRAM, EDO DRAM, BEDODRAM, VRAM, NOVRAM, and FRAM.

(b) ROM, PROM, EPROM, EEPROM, and flash ROM

21 Draw figures to show how

a) Four 1K x 1 DRAMs can be connected together to form a 1K x 4

memory

b) Four 1K x 8 DRAMs can be connected to form a 4K x 8 memory

22 A ROM has 15 address pins

a) How many words can it store?

b) A ROM can store 128K words. How many addresses must it have?

23 A number of 32 K x 4 DRAMs are available. How many must be interconnected to form (a)A 512 K x 16 memory. (b) A 1M x 8 memory?

24 (a) A memory is organized as 1M x 4. Calculate

(i) The number of locations in the memory

(ii) the total umber of bits stored.

(b) Repeat for 64K x 16 memory

25 a) express in hexadecimal the lowest and the highest addresses of a (i) 32 x 4 EEPROM and (ii) a 1M x 4 DRAM

b) Calculate the size of each address

26 Design a 64 x 16 memory using 64K x 4 ICs. The start address is 0H

27 Implement the Boolean functions

F1 = ABCD + ABCD + ABCD,

F2 = ABCD + ABCD

F3 = ABCD + ABCD + ABCD + ABCD, using a ROM

The letters in bold indicates complement

Q1

C2

0

1

000

1

0

010

11

11

0

0

1

10

0

0/0

0/0

1/0

001

0/0

1/1

101

010

011

0/0

1/0

0/0

1/0

100

12V

Fig. 1

VBB =--15V

Vc2

20 K(

10 K(

R2

0.1 (F

RC

RC

Q2

Q1

1 K(

Vc1

1 K(

12V

Q2

RC2

RC1

C1

R2

R1

RAM

Data in

Data out

10 address lines

Read/ write

CS

Vcc= 5V

A

B

C

4 K(

1.6 K(

RL

Q2

Q1

1 K(

Q3

Y

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