ECE 2C, notes set 5: Fundamentals of Transistor Amplifiers ... · class notes, M. Rodwell, copyrighted 2013 Comment (1): DC bias design in real circuits. Bias structures in real ICs

class notes, M. Rodwell, copyrighted 2013

ECE 2C, notes set 5: Fundamentals of Transistor Amplifiers (part II)

Mark Rodwell

University of California, Santa Barbara

[email protected] 805-893-3244, 805-893-3262 fax


Goals:

...) junction, tunnel tube,Vacuum (diode,

elementcircuit nonlinear any or *

circuits *r transistoof analysis signal-small AC Practice

circuits *r transistoof analysis bias DC Practice


Comment (1): DC bias design in real circuits.

shown as :ICs realin structures Bias

now.for OKBut real.not Clearly

battery. a with biasinput DC provided have we

study,amplifier simpleour developingIn amplifier Tutiorial

biasing RC

style s1950'style) (IC coupledDirect

style IC-RF

tuned)(and biased LC


Comment (2): bias design: DC-coupling.

ECE137AB

stages all of tsrequiremen bias DCer fit togeth tocreativity& skill Need

next. theof ageinput volt DC stage oneon tageoutput vol DC

:designs ICamplifier/ Coupled-Direct


Comment (3): bias design: AC/RC-coupling.

ECE137ABin study detailed more Again,

analysis. reponsefrequency in exercisean as...mostly

circuitssuch study *briefly* willWe

.amplified.not are signalsfrequency -lowVery

stages.between levels DC isolate capacitors Blocking

resistorsby set conditions bias DC

:amplifiers Coupled-AC


Current Mirrors: First Treatment

operation basiconly consider now We

later) (discuss load activean as

currents. bias DC set) (to provide to

:circuits coupled DCin Used


Current mirror DC bias analysis (1)

.k 8.18

mA) 1.0/()V616.0V5.2(/)(

V.616.0

V 316.0mA/V 1mA 1.0)V3.0(

) neglected term()V3.0)(mA/V 1(mA 1.0

)1())(2/(

:Analysis

mA. 1.0set usLet

1

2

22

2

1

1

ref

DgsDDref

gs

gs

DSgs

DSthgsggoxD

D

R

IVVR

V

V

VV

VVVLWcI

I

V10/1

V 3.0

mA/V1)2/(

:Q1 FET

2

th

ggox

V

LWc

:Parameters Example

k 0.1

V 5.2

Circuit

L

dd

R

V

analysis. signal small

in the term)1( theignorenot Do

.accuratelyfairly yet quickly thiscalculate

to trickssomelearn willECE137A weIn

error.t significan some causes thisDoing

analysis. bias in the

term)1( theignoringagain are we*

DS

DS

V

V

V10/1

V 3.0

mA/V2)2/(

:Q1 FET

2

th

ggox

V

LWc


Current mirror DC bias analysis (2)

V 3.2

).k1)(mA 2.0(V5.2

mA 2.0

) neglected term()V3.0V613.0)(mA/V 2(

)1())(2/(

:Analysis

branch.ouput in thecurrent thefind Now

2

22

2

22

2

2

2

D

LDDDD

D

DSD

DSthgsggoxD

V

RIVV

I

VI

VVVLWcI

V10/1

V 3.0

mA/V1)2/(

:Q1 FET

2

th

ggox

V

LWc

:Parameters Example

k 0.1

V 5.2

Circuit

L

dd

R

V

analysis. signal small

in the term)1( theignorenot Do

.accuratelyfairly yet quickly thiscalculate

to trickssomelearn willECE137A weIn

error.t significan some causes thisDoing

analysis. bias in the

term)1( theignoringagain are we*

DS

DS

V

V

V10/1

V 3.0

mA/V2)2/(

:Q1 FET

2

th

ggox

V

LWc

sourcecurrent -constant

. of value theof regardless load the1mA to provide willand

voltageknee than themore be willQ2 of large,not is If

L

DSL

R

VR


Current Mirrors: Constant-Current Source

voltages.of range wideaover i.e.

s,resistance load of range wideaover

currentconstant nearly providesmirror

small, is term)(1 theIf DSV

varied.is

)resistance load (or the

tageoutput vol theas

current load of

nt variatiosignifican a

causes term)(1 The DSV


Differential Amplifiers

source.current DC ideal

and asit treat :Here

mirror.current atypically

:sourceCurrent

used. Widely easier.design

IC coupled-DC makes Also

. and agesinput volt two

between difference theAmplifies

inin VV


Differential Amplifier: DC bias analysis

V5.0)k8)(mA 25.0(V5.2

V80.0V80.0V0

V80.0)mA/V 1()mA25.0()V3.0(

) neglected term()V3.0)(mA/V 1(mA25.0

)1())(2/(

mA 25.02/ :symmetry From

2

22

2

2

21

LDDDD

gsgs

gsgs

DSgs

DSthgsggoxD

SSDD

RIVV

VVV

VV

VV

VVVLWcI

III

V10/1

V 3.0

mA/V1)2/(

:, FETs

2

21

th

ggox

V

LWc

QQ

mA 2/1

k 8

V 5.2

Circuit

SS

L

dd

I

R

V


Differential Amplifier: FET Small Signal Parameters

40k

1S 25

10V

mA 25.01

mS 13.1

)V/10V3.11)(V3.0V8.0)(mA/V2(

)1)()(/(

)1())(2/(

2

2

D

ds

ds

DSthgsggoxm

DSthgsggoxD

IR

G

VVVLWcg

VVVLWcI

V10/1

V 3.0

mA/V1)2/(

:, FETs

2

21

th

ggox

V

LWc

QQ

V 8.0

mA 4/1

gs

D

V

I

parameters signal-small FET thecalculate to

conditions bias DC theusemust weagain, Once


Differential Amplifier: Small Signal Equivalent Circuit

signals mode-common and aldifferenti

simpler.it make uslet

problem, thisanalyze weBefore


Differential and Common-Mode Signals: Input

2

,

,

din

cminin

VVV

2

,

,

din

cminin

VVV

cminV , cminV ,

2

,dinV

2

,dinV

2/)( ageinput volt (average) mode-common

ageinput volt aldifferenti

,

,

ininCMin

ininDin

VVV

VVV

2/

2/

2/)(

,,

,,

,

,

dincminin

dincminin

inincmin

inindin

VVV

VVV

VVV

VVV


Differential and Common-Mode Signals: Output

2

,

,

dout

cmoutout

VVV

2/)( tageoutput vol (average) mode-common

tageoutput vol aldifferenti

,

,

outoutcmout

outoutdout

VVV

VVV

2/

2/

2/)(

,,

,,

,

,

doutcmoutout

doutcmoutout

outoutcmout

outoutdout

VVV

VVV

VVV

VVV

2

,

,

dout

cmoutout

VVV


Analysis: Use the principle of superposition

inV

inV

cminV , cminV ,2

,dinV

2

,dinV

/2 , /2

using and find you want) (if

,get gain to mode-common by the multiply

,get gain to aldifferenti by the multiply

, and of sum asinput thewrite, and find To

gain. *mode-common* and *aldifferenti*for circuit theanalyze , So

. and ofion superposit a as written be alwayscan inputs ),( The

,,,,

,,

,,

,,

doutcmoutoutdoutcmoutout

outout

cmoutcmin

doutdin

cmindinoutout

cmdinin

VVVVVV

VV

VV

VV

VVVV

VVVV


Differential gain

zero. bemust point at this voltagesignal-small thesymmetry, From

ground. virtuala called is This point. thisground weif difference no makesit So,


Differential gain

!away sideright thecan throw weSo,

left on the thoseof negatives are sideright on the voltages theall symmetry, From

circuit theof sides 2 ebetween th connection broken the has ground virtual the..and,


Differential gain: analysis

7.53 ofgain aldifferenti a hascircuit The

53.7

:so ,2/ and 2/But

53.7)k .666mS)(13.1(

gain Voltage

k 666.6

k8||k40||

resistance load Equivalent

,

,

,,

,

Leqm

in

out

Din

Dout

D

Doutoutdinin

Leqm

in

out

DSLeqL

RgV

V

V

VA

VVVV

RgV

V

RRR

k40

mS 13.1

:FET

DS

m

R

g

:Parameters

8k

Circuit

LR

2/ become has ,2/ become has

:however careful, Be

stage. source-common a as same thenow iscircuit The

doutdin VVVV


Common-mode gain

zero. bemust wirein thiscurrent signal-small thesymmetry, From

open. virtuala called be) (should This wire.cut this weif difference no makesit So,


Common-mode gain

!away sideright thecan throw weagain, So,

left on the those* as same the* are sideright on the voltages theall symmetry, From

circuit theof sides 2 ebetween th connection broken the hasopen virtual the..and,


Common-mode: analysis

ECE137ABin thisanalayze willWe

zero.not but small, be gain will mode-common the

sourcecurrent the toresistanceoutput finite aWith

gain. mode-common zeroin results This

infinite. is soucecurrent theof

impedance signal-small that theassumed have We

analysis. idealizedextremely an is This

:Note

0

zero. is tageoutput vol mode-common the

zero. iscurrent drain the

zero. iscurrent source the

connection no has source FET The

,

,

cmin

cmout

cmV

VA


Differential Amplifiers: Recap

2/

2/

2/)(

,,

,,

,

,

doutcmoutout

doutcmoutout

outoutcmout

outoutdout

VVV

VVV

VVV

VVV

2

,

,

din

cminin

VVV

2

,

,

din

cminin

VVV

2/

2/

2/)(

,,

,,

,

,

dincminin

dincminin

inincmin

inindin

VVV

VVV

VVV

VVV

2

,

,

dout

cmoutout

VVV

2

,

,

dout

cmoutout

VVV

high is impedance source-current theif 0 where

where

,,

,,

cmcmincmcmout

Leqmddinddout

AVAV

RgAVAV


Differential Amlifiers: Applications

example. simple oneat Look

stages. coupled-DC ofdesign of ease :napplicatioAnother

stages.input amp-opin ation,instrumentprecision in seen

voltageswobetween t difference theamplifying :napplicatio One


Example: Two-Stage Differential Amplifier

output. andinput at DC voltszero with and

coupling DCwith amplifier an design easy toit make

n,alternatio NFET/PFET theand design, aldifferenti The

stages. aldifferenti cascaded ofpair A


Two-stage differential amplifier: DC bias analysis

V0.0)k10)(mA 25.0(V5.2

V30.1V80.0V5.0

so source, than the*negative more* is gate The

V80.0)mA/V 1()mA25.0()V3.0(

) neglected term()V3.0)(mA/V 1(mA25.0

)1())(2/(

mA 25.02/ :symmetry From

conditions bias stage Second

2

22

2

2

243

LDSSD

gsgs

gsgs

DSgs

DSthgsggoxD

SSDD

RIVV

VVV

VV

VV

VVVLWcI

III

V10/1

V 3.0||

mA/V1)2/(

FETs All

2

th

ggox

V

LWc

mA 2/1

k 8

V 5.2

Circuit

1

2,1

SS

L

dd

I

R

V

mA 2/1

k 10

V 5.2

2

4,3

SS

L

ss

I

R

V

conditions bias DC same

example.prior thefrom taken is stage 1 The st


Two-stage differential amplifier: s.s. parameters

40k

1S 25

1

mS 13.1

. and )2/(for values

same thehave FETs all and example, previous theof

those toidentical are nscalculatio The

ds

ds

m

ggox

RG

g

LWc


Two-stage differential amplifier: s.s. analysis

grounds. virtual toconnectedcan so and

voltagesAC zero have

points indicated theinput, aldifferenti aFor

.convention a is This

models. signal-smalltheir

by replacedbeen yet not have rs transistobut the

circuits,-openby replacedbeen have currentssupply the

circuits,-shortby replacedbeen have tagessupply vol the

left,at diagram signal small In the



stages. source-common cascade with twous leaves This

circuit. thehalf delete to

us allow grounds virtual theAgain,

circit equivalent signal small AC

models signal-small with symbolsr transistoReplace



53.7

)k mS)(6.6613.1(

gain Voltage

k 666.6

k8||k40||


before) (as stageFirst

11

1

111,

Leqm

stagein

out

DSLeqL

RgV

V

RRR

04.9

)k mS)(8.013.1(

gain Voltage

k 0.8

k10||k40||


stage Second

22

2

222,

Leqm

stagein

out

DSLeqL

RgV

V

RRR

1.68

.04)9)(53.7(

gain Voltage Overall

amplfier stage-2

21

2

vv

stagesin

out AAV

V

Documents

ECE 2C, notes set 5: Fundamentals of Transistor Amplifiers ... · class notes, M. Rodwell, copyrighted 2013 Comment (1): DC bias design in real circuits. Bias structures in real ICs