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ECE 429 – Introduction to VLSI DesignLecture 06 CMOS Layout with Stick Diagrams
Professor Jia WangDepartment of Electrical and Computer Engineering
Illinois Institute of Technology
January 25, 2018
ECE 429 – Introduction to VLSI Design Spring 2018 1/13
Reading Assignment
I This lecture: 1.5
I Next lecture: 4.1 – 4.3
ECE 429 – Introduction to VLSI Design Spring 2018 2/13
Outline
CMOS Layout Design
ECE 429 – Introduction to VLSI Design Spring 2018 3/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Elements
I Layouts are consisting of rectangles at different layers.I Silicon surface
I active: diffusion regionsI nimplant (n-select): the n+ diffusion regionsI pimplant (p-select): the p+ diffusion regionsI nwell: for pMOS transistorsI pwell: for nMOS transistors in a twin-well process like
FreePDK45
I poly: one layer usually used for gate
I metal1. . .metalN: for interconnects
I Rectangles abutting each other in the same layer areconnected.
I Rectangles on different layers may overlap. They areconnected by
I contact: connect metal1 to diffusion/poly/well/substrateI via1. . .viaN: connect metals on different layers
ECE 429 – Introduction to VLSI Design Spring 2018 4/13
Layout Design Rules
I To ensure proper manufacturing of devices, we must followlayout design rules to draw layouts.
I Scalable (λ) design RulesI λ: unit length, usually half of the feature sizeI Simple but conservative: dimensions must be multiples of λI Over-conservative for processes under 180nm
I Industrial design rulesI Use finer grids (a few nm) to optimize for small feature sizes
and specific processesI Complicated, need extensive design rule check (DRC) during
the layout process to ensure correctness
I Our hybrid approachI For simplicity, use λ design rules in lectures/homeworks/exams.I For realistic design experience, use an industrial-like 45nm
design rule (FreePDK45) for labs and projects.
ECE 429 – Introduction to VLSI Design Spring 2018 5/13
Layout Design Rules
I To ensure proper manufacturing of devices, we must followlayout design rules to draw layouts.
I Scalable (λ) design RulesI λ: unit length, usually half of the feature sizeI Simple but conservative: dimensions must be multiples of λI Over-conservative for processes under 180nm
I Industrial design rulesI Use finer grids (a few nm) to optimize for small feature sizes
and specific processesI Complicated, need extensive design rule check (DRC) during
the layout process to ensure correctness
I Our hybrid approachI For simplicity, use λ design rules in lectures/homeworks/exams.I For realistic design experience, use an industrial-like 45nm
design rule (FreePDK45) for labs and projects.
ECE 429 – Introduction to VLSI Design Spring 2018 5/13
Layout Design Rules
I To ensure proper manufacturing of devices, we must followlayout design rules to draw layouts.
I Scalable (λ) design RulesI λ: unit length, usually half of the feature sizeI Simple but conservative: dimensions must be multiples of λI Over-conservative for processes under 180nm
I Industrial design rulesI Use finer grids (a few nm) to optimize for small feature sizes
and specific processesI Complicated, need extensive design rule check (DRC) during
the layout process to ensure correctness
I Our hybrid approachI For simplicity, use λ design rules in lectures/homeworks/exams.I For realistic design experience, use an industrial-like 45nm
design rule (FreePDK45) for labs and projects.
ECE 429 – Introduction to VLSI Design Spring 2018 5/13
Layout Design Rules
I To ensure proper manufacturing of devices, we must followlayout design rules to draw layouts.
I Scalable (λ) design RulesI λ: unit length, usually half of the feature sizeI Simple but conservative: dimensions must be multiples of λI Over-conservative for processes under 180nm
I Industrial design rulesI Use finer grids (a few nm) to optimize for small feature sizes
and specific processesI Complicated, need extensive design rule check (DRC) during
the layout process to ensure correctness
I Our hybrid approachI For simplicity, use λ design rules in lectures/homeworks/exams.I For realistic design experience, use an industrial-like 45nm
design rule (FreePDK45) for labs and projects.
ECE 429 – Introduction to VLSI Design Spring 2018 5/13
Scalable (λ) Design Rules Illustrated
(Weste and Harris)
I Recall process variation may result in quite different shapesthan rectangles after fabrication
I Most rules are used to ensure connection, e.g. minimumwidth, and isolation, e.g. minimum spacing.
ECE 429 – Introduction to VLSI Design Spring 2018 6/13
Scalable (λ) Design Rules Illustrated
(Weste and Harris)
I Recall process variation may result in quite different shapesthan rectangles after fabrication
I Most rules are used to ensure connection, e.g. minimumwidth, and isolation, e.g. minimum spacing.
ECE 429 – Introduction to VLSI Design Spring 2018 6/13
Layout Validation and Parasitic Extraction
I Information from layoutI Compute diffusions/gates/transistors from masksI Extract devices and interconnects from masksI Extract geometric information to estimate capacitances,
resistances, etc
I ApplicationsI Design Rule Checking (DRC): verify that the layout design
rules are not violatedI Layout vs. Schematic (LVS): verify that the layout matches
the schematicI Parasitic Extraction: obtain “real” resistances and
capacitances for accurate simulation and analysis
ECE 429 – Introduction to VLSI Design Spring 2018 7/13
Layout Validation and Parasitic Extraction
I Information from layoutI Compute diffusions/gates/transistors from masksI Extract devices and interconnects from masksI Extract geometric information to estimate capacitances,
resistances, etc
I ApplicationsI Design Rule Checking (DRC): verify that the layout design
rules are not violatedI Layout vs. Schematic (LVS): verify that the layout matches
the schematicI Parasitic Extraction: obtain “real” resistances and
capacitances for accurate simulation and analysis
ECE 429 – Introduction to VLSI Design Spring 2018 7/13
Stick Diagrams
I We can use 1-D lines to sketch layouts
I VDD/GND rail, pMOS/nMOS diffusions: horizontal lines
I Gates: vertical lines
I Make connections and add contacts
ECE 429 – Introduction to VLSI Design Spring 2018 8/13
Stick Diagrams
I We can use 1-D lines to sketch layouts
I VDD/GND rail, pMOS/nMOS diffusions: horizontal lines
I Gates: vertical lines
I Make connections and add contacts
ECE 429 – Introduction to VLSI Design Spring 2018 8/13
Stick Diagrams
I We can use 1-D lines to sketch layouts
I VDD/GND rail, pMOS/nMOS diffusions: horizontal lines
I Gates: vertical lines
I Make connections and add contacts
ECE 429 – Introduction to VLSI Design Spring 2018 8/13
Stick Diagrams
I We can use 1-D lines to sketch layouts
I VDD/GND rail, pMOS/nMOS diffusions: horizontal lines
I Gates: vertical lines
I Make connections and add contacts
ECE 429 – Introduction to VLSI Design Spring 2018 8/13
Stick Diagram for F = ABC
ECE 429 – Introduction to VLSI Design Spring 2018 9/13
Stick Diagram for F = AB + CD
ECE 429 – Introduction to VLSI Design Spring 2018 10/13
Hints for Stick Diagrams
I ElementsI metal1I polyI diffusionI contact
I Name all the nodes in your transistor schematic and use themto guide the stick diagram
I There is exact one layer for each of metal1/poly/diffusionI If one metal1 line intersect with another metal1 line, they are
connectedI If one poly line intersect another poly line, they are connectedI Same for diffusions
I Use contact to connect diffusion/poly to metal1
ECE 429 – Introduction to VLSI Design Spring 2018 11/13
Hints for Stick Diagrams
I ElementsI metal1I polyI diffusionI contact
I Name all the nodes in your transistor schematic and use themto guide the stick diagram
I There is exact one layer for each of metal1/poly/diffusionI If one metal1 line intersect with another metal1 line, they are
connectedI If one poly line intersect another poly line, they are connectedI Same for diffusions
I Use contact to connect diffusion/poly to metal1
ECE 429 – Introduction to VLSI Design Spring 2018 11/13
Hints for Stick Diagrams
I ElementsI metal1I polyI diffusionI contact
I Name all the nodes in your transistor schematic and use themto guide the stick diagram
I There is exact one layer for each of metal1/poly/diffusionI If one metal1 line intersect with another metal1 line, they are
connectedI If one poly line intersect another poly line, they are connectedI Same for diffusions
I Use contact to connect diffusion/poly to metal1
ECE 429 – Introduction to VLSI Design Spring 2018 11/13
Hints for Stick Diagrams
I ElementsI metal1I polyI diffusionI contact
I Name all the nodes in your transistor schematic and use themto guide the stick diagram
I There is exact one layer for each of metal1/poly/diffusionI If one metal1 line intersect with another metal1 line, they are
connectedI If one poly line intersect another poly line, they are connectedI Same for diffusions
I Use contact to connect diffusion/poly to metal1
ECE 429 – Introduction to VLSI Design Spring 2018 11/13
From Stick Diagrams to Layouts
I Decide gate length (L) and width (W)I Gate length (channel length) is the same as poly width, usually
at minimumI Gate width is the length of the overlapped area of poly and
diffusion
I Follow layout design rules to expand lines into rectangles
ECE 429 – Introduction to VLSI Design Spring 2018 12/13
From Stick Diagrams to Layouts
I Decide gate length (L) and width (W)I Gate length (channel length) is the same as poly width, usually
at minimumI Gate width is the length of the overlapped area of poly and
diffusion
I Follow layout design rules to expand lines into rectangles
ECE 429 – Introduction to VLSI Design Spring 2018 12/13
Summary
I CMOS layout with stick diagrams
ECE 429 – Introduction to VLSI Design Spring 2018 13/13
