ECE 449: Computer Design Lab

Coordinator: Kris Gaj

TAs:

Tuesday session: Pawel Chodowiec

Thursday session: Nghi Nguyen

Tasks of the course

Advancedcourse on digital

system designwith VHDL

Introduction toFPGA

technology

Testing equipment

- writing VHDL code for synthesis- RTL VHDL- state machines- test benches

- hardware: Xilinx FPGAs

- software: Aldec simulator Xilinx ISE

- oscilloscope- logic analyzer

Subset of VHDL used in ECE 449

VHDL model

behavioralstructural

data flow algorithmic

• Registers• State machines• Test benches

Required

Not required

Concurrent statements Sequential statements

Structural VHDL

• component instantiation (port map)• component instantiation with generic (generic map, port map)• generate scheme for component instantiations (for-generate)

Major instructions

Data-flow VHDL

• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)

Major instructions

Concurrent statements

Algorithmic VHDL (subset)

• process statement (process)• sequential signal assignment ()

Major instructions

Sequential statementsGeneral

Registers

• if-then-else statement

State machines

• case-when statement

Testbenches

• loops (for-loop, while-loop)

Digital system design technologies

Microprocessors ASICsFPGAs

ECE 445ECE 442ECE 447

ECE 586

ECE 680ECE 681ECE 645

ECE 681ECE 645

ECE 449

ECE 511ECE 611

ECE 431

Computer Organization

Digital Computer Design & Interfacing

Single ChipMicrocomputers

Computer Design Lab

Digital Circuit Design

Microprocessors

Advanced Microprocessors VLSI Design

Automation

Computer Arithmetic

Digital Integrated Circuits

Physical VLSIDesign

FPGAs vs. ASICs

ASICs FPGAs

High performanceOff-the-shelf

Short time to the market

Low development costs

Reconfigurability

Low power

Low cost (but only in high volumes)