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All Digital Phase-Locked Loop. Why design All Digital PLL?. By Selvakkumaran S. ECE1352F – Topic Presentation - ADPLL. Up. D Q CK. A. B. CK D Q. Dn. What is an All Digital Phase-Locked Loop (ADPLL)?. Some Analog PLLs have utilized pure digital components before - PowerPoint PPT Presentation
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ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL By Selvakkumaran S
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• Some Analog PLLs have utilized pure digital components beforee.g: Charge-pump PLLs utilized Phase Frequency Detector consisting of 3-state finite state machine with two flip-flops
D Q
CK
CK
D Q
A
B
Up
Dn
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Digital Phase
Detector
Digital LoopFilter
DigitalVCO
inout
• All Digital PLLs consist only of digital components
• The first All Digital PLL was reported by Drogni [1967]
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Why All Digital PLL?Why All Digital PLL?
*Progress in increasing • Performance• Speed• Reliability
*Progress in reducing
• Size• Cost
Improvements in digital designs
* Portability/ Reusability
* Programmability
* TestabilityECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Why All Digital PLL?Why All Digital PLL?
Solves Problems Related to Analog PLLs(APLL)
• Sensitivity to DC Drifts• Component Saturations• Difficulties building higher order loops• Initial calibration and periodic adjustments
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Issues of ADPLLs versus APLLsIssues of ADPLLs versus APLLs
• Limitation on operating speed
• Chip area
• Power Consumption
• Worse jitter performance due to D/A converter resolution limitation
* Note: The above issues need further exploration[7] as some papers have reported better ADPLL performance.
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Example ADPLL Loop FilterExample ADPLL Loop Filter
• Up/Down control from the Phase Detector Controls the Counter value or the Digital Phase difference – Transfer Function ~ 1/sTi
Up/Down Counter
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Example Digital VCO (DCO)Example Digital VCO (DCO)
• Up/Down Counter Value or the Phase Error is utilized to create the clock
%N Counter
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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ADPLL Design AnalysisADPLL Design Analysis
Z-transform technique[5,6]
• z domain transfer function
• Solutions within the unit circle ensures stability
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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ADPLL Design Example 1ADPLL Design Example 1[2][2]
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Results Results [2][2]
Process 0.35 0.25 0.60 0.60 0.50
Approach AD Cell Based
Analog
(1.9V)
Semi-digital
AD Cell Based
All-Digital
Area(mm2) 0.71 0.09 0.83 2.75 0.71
Power(mW) 100@500MHz
25 105@400MHz
315@800MHz
39.6@100MHz
Max.lock Time(cycles)
<46 <720 <16 <25 <50
Range
MHz
45-510 8.5-660 300-800 360-800 50-550
Output Jitter
70ps 80ps 149ps 60ps 125ps
3.3V Supply
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ResultsResults[2][2]
• Shorter Locking in time
• Better Jitter Performance
• Better Portability (cell-based design)
• Reduced circuit complexity
• Reduced Design Time
• Note: Some other papers have reported ADPLLs area and power statistics better than APLLs
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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ADPLL Design ADPLL Design Example 2Example 2[6][6]
A Second order ADPLL
H(z)=C2(Z-1)+C1
(Z-1)2+C2(Z-1)+C1
H(S)=2nS + n
2
S2 + 2nS + n2
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Acquisition BehaviourAcquisition Behaviour[6][6]
*ADPLL shows a better performance in terms of the acquisition time
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Phase JitterPhase Jitter BehaviourBehaviour[6[6]]
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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ResultsResults[6[6]]
• Larger lock-in range (~4.5 x APLL)
• Larger Hold-in Range than APLL
• Smaller RMS Phase Jitter
• Digital approach to design
• Software configurability/ programmability
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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• No need for off-chip components• Technology portability• Testability• Programmability
• Fast Acquisition Time• Large hold-in range• Large lock-in range• Better phase jitter performance
• Simpler design and faster simulation
• Stability
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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Future of ADPLL
• Digital IP (Intellectual Property) vendors are already creating ADPLL products
• As technology progress happens skew problems will require ADPLLs within the design components to synchronize the clock signal between various blocks
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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1. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
2. Ching-Che Chung and Chen-Yi Lee, “An All-Digital Phase-Locked Loop for High Speed Clock Generation, IEEE J. Solid-State Circuits, vol 38, No.2, pp347-351, February 2003
3. Thomas Olsson and Peter Nilsson, “A Digitally Controlled PLL Using a Standard Cell Library”, Lund University, Sweden, www.es.lth.se/home/ton
4. Roland E. Best, Phase-Locked Loops, Design, Simulation and Applications, 4th Ed, McGraw-Hill, 1999 (Chapter 4, pp177-228)
5. Venceslav F, Kroupa, Phase Lock Loops and Frequency Synthesis, Wiley, 2003, (Chapter 10, pp231-254)
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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6. Y.R.Shayan, T.Le-Ngoc, “All Digital phase-locked loop: concepts, design and applications”, IEE Procedings, Vol.136, Pt. F. No.1, pp53-56, February 1989
7. Dao-Long Chen, “A Power and Area Efficient CMOS Clock/Data Recovery Circuit for High-Speed Serial Interfaces, IEEE J. of Solid-state Circuits, Vol. 31, No8, pp1170-1176, August 1996
ECE1352F – Topic Presentation - ADPLLECE1352F – Topic Presentation - ADPLL
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