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Ching-Yuan Yang
National Chung-Hsing UniversityDepartment of Electrical Engineering
Basic Operational Amplifier Design
類 比 積 體 電 路 實 驗 室
學前訓練專題
1 Ching-Yuan Yang / EE, NCHUAIC Lab.
設計規格
Design a two-stage CMOS Op Amp: (CL = 1pF) VDD = −VSS = 1.5V Small signal gain Av ≥ 60dBGainbandwidth GB ≥ 10MHzSR ≥ 20 V/µs phase margin ≥ 65o
−0.7V ≤ ICMR ≤ 0.7V Pdiss ≤ 3mW Setting timeCMRRPSRROutput swingOutput resistanceOffsetNoiseLayout area
2 Ching-Yuan Yang / EE, NCHUAIC Lab.
Block Diagram of a Two-Stage Opamp
First gain stage: a differential-input single-ended output stage.Second gain stage: a CS stage with an active load.
CC is included to ensure stability when the opamp is used with feedback.Miller capacitance
Output buffer: (In this work, not be included)
A1Vin −A2
CC
1 Vout
Differentialinput stage
Secondgain stage
Outputbuffer
3 Ching-Yuan Yang / EE, NCHUAIC Lab.
- A CMOS realization of a two-stage amplifier (unbuffer)
M10
M11
M14 M12
M13M15
RB
M5
M1 M2
M4M3 M7
Vin− Vin+
M16
CC
M6
VDD
Vout
Bias circuitry Differential-inputfirst stage
Common-sourcesecond stage
CL
4 Ching-Yuan Yang / EE, NCHUAIC Lab.
- Opamp gain
The gain of the 1st stage: Av1 = gm1(rds2 // rds4)where
The gain of the 2nd stage: CS gain stage
Av2 = −gm7(rds6 // rds7)
The gain of the 3rd stage: CD buffer stage
1 11 1
2 22
biasm p ox D p ox
idsi DGi ti
Di
IW Wg C I CL L
Lr V VI
µ µ
α
= =
≈ +
83
8 8 9
mv
L m ds ds
gAG g g g
≈+ + +
5 Ching-Yuan Yang / EE, NCHUAIC Lab.
- Frequency response
Miller’s theorem: Ceq = CC(1 + A2) ≈ CCA2
1st stage gain:
The overall gain:
11 1 1 1 2 1
1 1m out out ds ds
in eq eq
vA g Z Z r rv sC sC
= = − = ≈where
≡ = ≈ 12 1 2
2( ) out m
vin C
v gA s A A Av sC A
1( ) mv
C
gA ssC
= unit gain freq. 1mu
C
gC
ω =
M5
M1 M2
M4M3
VDD
Vbias
−A2
CC
Vout
V1 V2
i = gm1vin
+Vin−
6 Ching-Yuan Yang / EE, NCHUAIC Lab.
Slew Rate
Vin
Vout
Vin
Vout
t
tSR
Exponential
M1 M2
M4M3 M7
Vin− Vin+
M6
VDD
Vout
Vbias
CC
ISS
Ix C2
Io2
Log(SR)
Log(C2)
SRint
SRext
7 Ching-Yuan Yang / EE, NCHUAIC Lab.
- Slew rate
The slew rate is the maximum rate at which the output changes when input signals are large.The internal slew rate is generally limited by the current available to charge and discharge CC from input stage.
Since ISS = 2ID1, we have
The only way of improving the slew rate for the two-stage opamp is to increase VOD1, ωu , or both.
,max
max
CCout SS
C C
Idv ISRdt C C
= = =
12 D
C
ISRC
= unit gain freq. 1mu
C
gC
ω =
= = =
=
1 11
11
1
11
1
2 2
2
2
D u Du OD u
mp ox D
DOD
p ox
I ISR Vg WC I
LIV WC
L
ω ω ωµ
µwhere
8 Ching-Yuan Yang / EE, NCHUAIC Lab.
The external slew rate is limited by the current available to charge and discharge C2 .
6 ,max2 6ext
2 2 2
D xo D SSI II I ISRC C C
− −= = =
M1 M2
M4M3 M7
Vin− Vin+
M6
VDD
Vout2
Vbias
CC
ISS
IxC2
Io2
9 Ching-Yuan Yang / EE, NCHUAIC Lab.
Systematic Offset Voltage
The systematic input referred dc offset can be expressed as
The systematic offset voltage is caused by asymmetry in the dc biasing of V1 and V2.
−
−
= +
= =
∆ = − = −
∆ = − = −
2
1 2 3 4
1 2 1 2 1 2 1
3 4 3 4 3 1 2
1 (1 )2
( )2
( )2
D OD DS
SSD D
SSD D
I KV V
II I I V V
II I I V V
λ
λ λ λ λ
λ
λ
−− −− = ⋅ ∆ − ∆ = ⋅ + −,1 2
, 1 2 3 4 1 3 2 11
1 ( ) ( )( )2
ODOS s
m
VV I I V V
gλ λ
M5
M1 M2
M4M3 M7
Vin− Vin+
M6
VDD
Vout2
Vbias
Vos
V1CCV2
ISS
10 Ching-Yuan Yang / EE, NCHUAIC Lab.
To ensure that no systematic input-offset voltage exists, when the differential input voltage is zero (ie., when Vin+ = Vin−), the output voltage of the first stage, VGS7, should be that which is required to make ID7 equal to its bias current, ID6.
Since , we see that
Further, to minimize process induced variations choose L3 = L4 = L7.
However, this constraint may conflict with frequency response and noise constraints.
67
7
2( / )
DGS tn
n ox
IV VC W Lµ
= +
47 3 4 4
4
2( / )
DGS DS GS GS tn
n ox
IV V V V VC W Lµ
= = = +and
+ = + =6 64 4
4 7 4 7
22( / ) ( / ) ( / ) ( / )
D DD Dtn tn
n ox n ox
I II IV VC W L C W L W L W Lµ µ
6 6 6
4 5 5
( / )/2 ( / ) /2
D D
D D
I I W LI I W L
= = 67
4 5
( / )( / ) 2( / ) ( / )
W LW LW L W L
=
11 Ching-Yuan Yang / EE, NCHUAIC Lab.
n-channel or p-channel Input Stage in Two-Stage Opamp
Comparing the nMOST-input opamps, the pMOST-input opamps haveSimilar dc voltage gain.Smaller gm1 and larger gm7.Larger unity-gain frequency since ωu ≈ ωp2 and ωp2 = gm7 /C2.Better slew rate since both VOD1 and ωu is larger.
N-channel source-follower output stage is preferable because of less of a voltage drop.Better 1/f noise performance.Poor thermal noise performance.
= >1 , ,( )OD u OD p OD nSR V V Vω
12 Ching-Yuan Yang / EE, NCHUAIC Lab.
Compensation the Two-Stage Opamp
= =1616 16
1( / )Z ds
n ox effR r
C W L Vµ
M5
M1 M2
M4M3 M7
Vin− Vin+
M6
VDD
Vout2
Vbias1
M16
CC
Vbias2
13 Ching-Yuan Yang / EE, NCHUAIC Lab.
- A small-signal model of the two-stage opamp for compensation analysis
=
= + +
=
= + +
1 4 2
1 2 4 7
2 6 7
2 7 6 2
ds ds
db db gs
ds ds
db db L
R r rC C C CR r rC C C C
−
=+ +
1 7 1 27
21 2
1
1
Cm m
mout
in
sCg g R RgV
V b s b swhere
= + + + +
= + +1 1 1 2 2 7 1 2
2 1 2 1 2 1 2
( ) ( )( )
C C m C
C C
b R C C R C C g R R Cb R R C C C C C C
= 0ZR
gm1VinR1 C1
CC
gm7V1R2 C2
Vout
v1 v2RZ
14 Ching-Yuan Yang / EE, NCHUAIC Lab.
Using dominant-pole approximation, ie., ωp1 << ωp2,
If gm7R2 >> 1, R1 ~ R2, and C1 ~ C2 ~ CC , then
= + + = + + ≈ + +
22
1 21 2 1 1 2
( ) 1 1 1 1p p p p p
s s s sD s b s b sω ω ω ω ω
≈ =+ + + +
+ + + +≈ =
+ +
−=
11 1 1 2 2 7 1 2
1 1 2 2 7 1 212
2 1 2 1 2 1 2
7
1 1( ) ( )( ) ( )
( )
pC C m C
C C m Cp
C C
mz
C
b R C C R C C g R R CR C C R C C g R R Cb
b R R C C C C C CgC
ω
ω
ω
≈ = ⋅
≈ ≈+ + +
11
7 1 2 0
7 72
1 2 1 2 1 2
1 1mp
m C C
m C mp
C C
gg R R C C A
g C gC C C C C C C C
ω
ω
15 Ching-Yuan Yang / EE, NCHUAIC Lab.
Load Compensation
RZ = 1/gm7, eliminate the right-half-plane zero together.RZ > 1/gm7, and move the right-half-plane zero to the left-half-plane to cancel the nondominant pole, ωp2.
Unfortunately, C2 is often not know, especially when no output stage is present.Choose RZ even larger to move the left-half-plane to a frequency slightly greater than ωt .
−=
−7
1(1/ )z
C m ZC g Rω
+= +
1 2
7
1 1Zm C
C CRg C
≈ = = =11
1
1 1 1' 1.2 1.21.2
mz u Z
Z C Z C C m
g RR C R C C g
ω ω
16 Ching-Yuan Yang / EE, NCHUAIC Lab.
Making Compensation Independent of Process and Temperature
= =
=
1616 16
7 7 7
1( / )
( / )
Z dsn ox OD
m n ox OD
R rC W L V
g C W L Vµ
µ
= =7 77
16 16
( / ) constant( / )
ODZ m
OD
W L VR gW L V
How to make compensation independent of process and temperature?
Make Va = Vb, ie., VOD13 = VOD7.
= 137
7 13
22( / ) ( / )
DD
n ox n ox
IIC W L C W Lµ µ
= = 67 7
13 13 11
( / )( / )( / ) ( / )
D
D
W LI W LI W L W L
=6 11
7 13
( / ) ( / )( / ) ( / )W L W LW L W L
VOD12 = VOD16
= =7 13 12
16 12 13
( / )( / )
OD OD
OD OD
V V W LV V W L
= 1277
16 13
( / )( / )( / ) ( / )Z m
W LW LR gW L W L
M11
M12
M13 M7
M16
CC
M6Vbias1
VbVa
17 Ching-Yuan Yang / EE, NCHUAIC Lab.
Biasing on Opamp to Have Stable Transconductances
ID15 = ID13 VGS13 = VGS15 + ID15RBVOD13 = VOD15 + ID15RB
= +13 1515
13 15
2 2( / ) ( / )
D DD B
n ox n ox
I I I RC W L C W Lµ µ
= +13 1313
13 15
2 2( / ) ( / )
D DD B
n ox n ox
I I I RC W L C W Lµ µ
− =
⋅ 13
1513 13
( / )2 1( / )2 ( / ) B
n ox D
W L RW LC W L Iµ
−
=
13
1513
( / )2 1( / )
mB
W LW L
gR
gm13 is determined by geometric ratios only, independent of power-supply voltages, process parameters, temperature, or any other parameters with large variability.
M10 M11
M14 M12
M13M15
RB
VDD
18 Ching-Yuan Yang / EE, NCHUAIC Lab.
For the special case of (W/L)15 = 4(W/L)13, we have
=131
mB
gR
gm13, and all other transconductances are stabilized since all transistor currents are derived from the same biasing network, and, therefore, the ratios of the currents are mainly dependent on geometry.
For all n-channel transistors,
For all p-channel transistors,
Note that this bias network needs start-up circuitry.
= × 1313 13
( / )( / )p i Di
mi mn D
W L Ig g
W L Iµµ
= × 1313 13
( / )( / )
i Dimi m
D
W L Ig gW L I
M10 M11
M14 M12
M13M15
RB
VDD
19 Ching-Yuan Yang / EE, NCHUAIC Lab.
Technique to Make gm Dependent on a Resistor
Assuming λ = 0, then Iout = IREF and VGS1 = VGS2 + ID2RS
Neglecting body effect, we have
That is,
It is often desirable to bias the transistors such that their transconductance does not depend on the temperature, process, or supply voltage.
Any transistor with VGS = VGS1 will have a current flow that makes the transconductance
equal , independent of the supply voltage and MOS
device parameters. In reality, the value of RS does vary with temperature and process.
SoutTHNoxn
outTH
Noxn
out RIVLWKC
IVLWC
I++=+ 21 )/(
2)/(
2µµ
SoutNoxn
out RIKLWC
I=
−
11)/(
2µ
2
2111
)/(2
−⋅=
KRLWCI
Snoxnout µ
The current is independent of the supply voltage (but still a function of process and temperature).
−=
=
KRI
LWCg
SD
Noxnm
1122 11 µ
VDDM3M4
M1 M2RS
IoutIREF
PLW
PLW
NLW
NLWK
20 Ching-Yuan Yang / EE, NCHUAIC Lab.
Technique to Make gm Dependent on a Resistor
Addition of RS to define the currents (assuming λ ≠ 0). Determine ∆Iout/∆VDD.
R1 = ro1 || (1/gm1), R3 = ro3 || (1/gm3)
143
4 RVgRI
rVV X
mouto
XDD =+−
The equivalent transconductance of M2 and RS is 2222
222 )( oSmbmoS
om
X
outm rRggrR
rgVIG
+++==
Thus, ( )
1
341424
11−
−= Rg
RrGrVI
momoDD
out → 0, if ro4 = ∞.
21 Ching-Yuan Yang / EE, NCHUAIC Lab.
Technique to Make gm Dependent on a ResistorAddition of RS to define the currents
Addition of start-up device
An important issue in supply-independent biasing is the
existence of “degenerate” bias points. For example, if all the
transistors carry zero current when the supply is turned on,
they may remain off indefinitely because the loop can support
a zero current in both branches.
In other words, the circuit can settle in one of two different
operating condition.
The diode-connected device M5 provides a current path
from VDD through M3 and M1 to ground upon start-up.
This technique is practical on if VTH1 +VTH5 + |VTH3| < VDDand VGS1 +VTH5 + |VGS3| > VDD, the latter to ensure M5
remains off after start-up.
22 Ching-Yuan Yang / EE, NCHUAIC Lab.
TWO-STAGE OP AMP DESIGN
23 Ching-Yuan Yang / EE, NCHUAIC Lab.
Unbuffered, Two-Stage CMOS Op Amp
Notation:
of the ith transistorLWLWS
i
ii /==
24 Ching-Yuan Yang / EE, NCHUAIC Lab.
DC Balance Conditions for the Two-Stage Op AmpFor best performance, keep all transistors in saturation. M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages. Therefore, we develop conditions to force M4 to be in saturation.
1) First assume that VSG4 = VSG6. This will cause “proper mirroring”in the M3-M4 mirror. Also, the gate and drain of M4 are at the same potential so that M4 is “guaranteed” to be in saturation.
2) If VSG4 = VSG6, then
3) However,
44
66 I
SSI
=
)2( 45
75
5
77 I
SSI
SSI
=
=
4) For balance, I6 must equal I7 which is called the “balance conditions”.
5) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
5
7
4
6 2SS
SS
=
25 Ching-Yuan Yang / EE, NCHUAIC Lab.
Design Relationships for the Two-Stage Op AmpSlew rate (Assuming I7 >> I5 and CL > Cc)
First-stage gain
Second-stage gain
Gain-bandwidth
Output pole
RHP zero
60° phase margin requires that if all other roots are ≥ 10GB.
Positive ICMR
Negative ICMR
Saturation voltage
It is assumed that all transistors are in saturation for the above relationships.
cCISR 5=
)(2
425
1
42
11 λλ +
=+
=I
ggg
gA m
dsds
mv
)( 766
6
76
62 λλ +
=+
=I
ggg
gA m
dsds
mv
c
m
CgGB 1=
L
m
Cgp 6
2−
=
c
m
Cgz 6
1 =
=
c
Lmm C
Cgg 26 2.2
(min)1(max)033
5(max) TTDDin VVIVV +−−=
β
)(5(max)11
5(min) satDSTSSin VVIVV +++=
β
βDS
satDSIV 2
)( =
26 Ching-Yuan Yang / EE, NCHUAIC Lab.
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters are given.
1. Gain at dc, Av(0)
2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, CL
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, Pdiss
27 Ching-Yuan Yang / EE, NCHUAIC Lab.
Unbuffered Op Amp Design ProcedureThis design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input common mode range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR), settling time (Ts), output voltage swing (Vout(max) and Vout(min)), and power dissipation (Pdiss) are given. Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60o phase margin we use the following relationship. This assumes that z ≥ 10GB.
Cc > 0.22CL2. Determine the minimum value for the “tail current” (I5) from the largest of the two values.
I5 = SR⋅Cc or
3. Design for S3 from the maximum input voltage specification.
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (= 0.67W3L3Cox) will not be dominant by assuming it to be greater than 10 GB.
5. Design for S1 (S2) to achieve the desired GB.
⋅+
≈s
SSDD
TVV
I2
105
2(min)1(max)03(max)3
33 ]['
2TTinDD VVVVK
IS+−−
=
GBCg
gs
m 102 3
3 >
51
1211 '
IK
gSSCGBg mcm ==⋅=
28 Ching-Yuan Yang / EE, NCHUAIC Lab.
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that VSG4 = VSG6.
8. Calculate I6 from
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6 /I5)S5 (Check the minimum output voltage requirements)10. Check gain and power dissipation specifications.
11. If the gain specification is not met, then the currents, I5 and I6, can be decreased or the W/L ratios of M2 and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the power dissipation is too high, then one can only reduce the currents I5 and I6. Reduction of currents will probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.
2)(55
55(max)1
1
5(min))(5 )('
2 mV100satDS
TSSinsatDS VKISVIVVV =≥−−−=
β
6
44626 2.2
m
m
c
Lmm g
gSSCCgg =
=
66
26
6 '2 SKgI m=
))(( )()(
265
766325
62SSDDdiss
mmv VVIIP
IIggA ++=
++=
λλλλ
29 Ching-Yuan Yang / EE, NCHUAIC Lab.
Example 6.3-1 - Design of a Two-Stage Op Amp
Using the material and device parameters given in Tables 3.1-2 and 3.2-1, design an amplifier similar to that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1µm.
A v > 5000V/V VDD = 2.5V VSS = -2.5V 60o phase marginGB = 5MHz CL = 10pF SR > 10V/µsVout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW
Solution1.) The first step is to calculate the minimum value of the compensation capacitor Cc, which is
Cc > (2.2/10)(10 pF) = 2.2 pF2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10 x 106) = 30 µA3.) Next calculate (W/L)3 using ICMR requirements.
4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB.Assume the Cox = 0.4fF/µm2. The mirror pole can be found as
or 448 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
15)/()/( 15]55.085.025.2[1050
1030)/( 4326
6
3 ===+−−⋅×
×= −
−
LWLWLW
(rads/sec) 1081.2)667.0(2'2
29
33
33
3
33 ×==
−≈
ox
p
gs
m
CLWISK
Cgp
30 Ching-Yuan Yang / EE, NCHUAIC Lab.
5.) The next step in the design is to calculate gm1 to getgm1 = (5x106)(2π)(3x10-12) = 94.25µS
Therefore, (W/L)1 is
6.) Next calculate VDS5,
Using VDS5 calculate (W/L)5 from the saturation relationship.
7.) For 60o phase margin, we know thatgm1 ≥ 10gm1 ≥ 942.5µS
Assuming that gm6 = 942.5µS and knowing that gm4 = 150µS, we calculate (W/L)6 as
3)/()/( 379.2151102)25.94(
'2)/()/( 21
2
1
21
21 ==≈=⋅⋅
=== LWLWIK
gLWLWN
m
35.085.0310110
1030)5.2()1( 6
6
5 =−⋅×
×−−−−= −
−
DSV
5.4)/( 5.449.4)35.0(10110
)1030(2)/( 526
6
5 =≈=⋅×
×= −
−
LWLW
9425.9410150
)105.942(15)/( 6
6
6 ≈=××
= −
−
LW
31 Ching-Yuan Yang / EE, NCHUAIC Lab.
8) Calculate I6 using the small-signal gm expression:
If we calculate (W/L)6 based on Vout(max), the value is approximately 15. Since 94 exceeds the specification and maintains better phase margin, we will stay with (W/L)6= 94 and I6 = 95µA.With I6 = 95µA the power dissipation is Pdiss = 5V·(30µA+95µA) = 0.625mW.
9) Finally, calculate (W/L)7
Let us check the Vout(min) specification although the W/L of M7 is so large that this is probably not necessary. The value of Vout(min) is
which is less than required. At this point, the first-cut design is complete.10.) Now check to see that the gain specification has been met
which meets specifications. An easy way to increase the gain would be to increase the W and L values by a factor of two which because of the decreased value of λwould multiply the above gain by a factor of 20.
A 95A5.949410502)105.942(
6
26
6 µµ ≈=⋅×⋅
×= −
−
I
14)/( 1425.14103010955.4)/( 76
6
7 =≈=
××
= −
−
LWLW
V351.014110
952)(7(min) =
⋅⋅
== satDSout VV
V/V 696,7)05.004.0(1095)05.004.0(1015
)1025.94)(1025.94(66
66
=+×⋅+×
××= −−
−−
vA
32 Ching-Yuan Yang / EE, NCHUAIC Lab.
The final step in the hand design is to establish true electrical widths and lengths based upon ∆L and ∆W variations. In this example ∆L will be due to lateral diffusion only. Unless otherwise noted, ∆W will not be taken into account. All dimensions will be rounded to integer values. Assume that ∆L = 0.2µm. Therefore, we have
W1 = W2 = 3(1 − 0.4) = 1.8µm ≈ 2µm W3 = W4 = 15(1 − 0.4) = 9µm W5 = 4.5(1 − 0.4) = 2.7µm ≈ 3µm W6 = 94(1 − 0.4) = 56.4µm ≈ 56µm W7 = 14(1 − 0.4) = 8.4µm ≈ 8µm
The figure below shows the results of the first-cut design. The W/L ratios shown do not account for the lateral diffusion discussed above. The next phase requires simulation.
33 Ching-Yuan Yang / EE, NCHUAIC Lab.
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op AmpCircuit:
We saw earlier that the roots were:
where Av = gm1gm6RIRII. (Note that p4 is the pole resulting from the nullingresistor compensation technique.)
61 /
1mccz gCCR
z−−
=
cv
m
cv
m
CAg
CAgp 22
1 −=−=
IzCRp 1
4 −=
L
m
Cgp 6
2 −=
34 Ching-Yuan Yang / EE, NCHUAIC Lab.
Design of the Nulling Resistor (M8)
In order to place the zero on top of the second pole (p2), the following relationship must hold
The resistor, Rz, is realized by the transistor M8 which is operating in the active region because the dc current through it is zero. Therefore, Rz, can be written as
The bias circuit is designed so that voltage VA is equal to VB.
∴ |VGS10| − |VT| = |VGS8| − |VT| VSG11 = VSG6
In the saturation region
Equating the two expressions for Rz gives
666 '211
ISKCCC
CCC
gR
pc
cL
c
cL
mz
+=
+=
( )TPSGpD
DSz VVSKdi
dvRDSV −
=== 888
8
'1
08
=
6
6
6
10
11
11
LW
II
LW
10
10
810
10
8
81010
1010
'21
2'
'1
)/('2
IKS
SISK
SKR
VVLWK
IVV
P
P
Pz
TGSP
TGS
==
−==−
∴
10
6610
8
8
IISS
CCC
LW
cL
c
+
=
35 Ching-Yuan Yang / EE, NCHUAIC Lab.
Example 6.3-2 - RHP Zero Compensation
Use results of Ex. 6.3-1 and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p2. Use device data given in Ex. 6.3-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I10. The first step in this design is to establish the bias components. In order to set VA equal to VB, then VSG11 must equal VSG6. Therefore,
S11 = (I11 /I6)S6
Choose I11 = I10 = I9 = 15µA which gives S11 = (15µA/95µA)94 = 14.8 ≈ 15.
The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1. There must be sufficient supply voltage to support the sum of VSG11, VSG10, and VDS9. The ratio of I10 / I5 determines the (W/L) of M9. This ratio is
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(4.5) = 2.25 ≈ 2
Now (W/L)8 is determined to be
663.5µA15
µA95941pF10pF3
pF3)/( 8 ≈=⋅⋅
+
=LW
36 Ching-Yuan Yang / EE, NCHUAIC Lab.
It is worthwhile to check that the RHP zero has been moved on top of p2. To do this, first calculate the value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
Next determine Rz
The location of z1 is calculated as
The output pole, p2, is
Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved from the RHP to the LHP.
The results of this design are summarized below.W8 = 6 µm W9 = 2 µm W10 = 1 µm W11 = 15 µm
V474.17.0150
152)/('
21010
1010 =+
⋅⋅
=+= TPP
GS VLWK
IV
( ) Ω=−⋅
=−
= k590.4)7.0474.1(63.550
1'
1108 TPSGP
z VVSKR
rad/sec 1046.94/
1 6
61 ×−=
−−
=mccz gCCR
z
rad/sec 1025.94 662 ×−=−=
L
m
Cgp
37 Ching-Yuan Yang / EE, NCHUAIC Lab.
An Alternate Form of Nulling Resistor
To cancel p2,z1 = p2
Which gives
In the previous example,gm6 = 942.5µS, Cc = 3pF and CL = 10pF.
Choose I6B = 10µA to get
or
Bmcm
Lcz gCg
CCR66
1=
+=
+
=Lc
cmBm CC
Cgg 66
6
66
6
6666
22 L
IWKCC
CL
IWKCCCgg DP
Lc
c
B
BDBP
Lc
cmBm
+
=+
=
m48 6.47941095
133
6
2
6
6
6
62
6
6 µ==⋅
=
+
= BA
A
BLc
c
B
B WLW
II
CCC
LW
38 Ching-Yuan Yang / EE, NCHUAIC Lab.
Programmability of the Two-Stage Op AmpThe following relationships depend on the bias current, IBias, in the following manner and allow for programmability after fabrication.
Illustration of the Ibias dependence
BiasIIImIImIv I
RRggA 1 )0( ∝=
Biasc
mI ICgGB ∝=
( )( ) BiasBiasSSDDdiss IIKKVVP ∝+++= 1 21
Biasc
Bias ICIKSR ∝= 1
BiasBiasout IIK
R 12
1
2
∝=λ
5.12
1 1Bias
Bias
Bias
cIIImII
II
ICRRg
p ∝∝=
Biasc
mII ICgz ∝=
39 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation of the Electrical Design
Area of source or drain = AS = AD = W[L1 + L2 + L3]where
L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5µm)L2 = Width of a minimum size contact (5µm)L3 = Minimum allowable distance from the contact in S/D to the edge of the S/D (5µm)∴ AS = AD = Wx15µm
Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3)∴ PD = PS = 2W + 30µm
Illustration:
40 Ching-Yuan Yang / EE, NCHUAIC Lab.
5-to-1 Current Mirror with Different Physical Performances
41 Ching-Yuan Yang / EE, NCHUAIC Lab.
1-to-1.5 Transistor Matching
The layout of two transistors with a 1.5 to 1 matching using centroidgeometry to improve matching.
42 Ching-Yuan Yang / EE, NCHUAIC Lab.
Reduction of Parasitics
The major objective of good layout is to minimize the parasitics that influence the design.Typical parasitics include:
Capacitors to ac groundSeries resistance
Capacitive parasitics is minimized by minimizing area and maximizing the distance between the conductor and ac ground.Resistance parasitics are minimized by using wide busses and keeping the bus length short.For example:
At 2mΩ /square, a metal run of 1000µm and 2µm wide will have 1Ω of resistance.At 1 mA this amounts to a 1 mV drop which could easily be greater than the least significant bit of an analog-digital converter. (For example, a 10 bit ADC with VREF = 1V has an LSB of 1mV)
43 Ching-Yuan Yang / EE, NCHUAIC Lab.
Technique for Reducing the Overlap Capacitance
Square Donut Transistor:
Note: Can get more W/L in less area with the above geometry.
Reduction of Cgd by a donut shaped transistor.
44 Ching-Yuan Yang / EE, NCHUAIC Lab.
Chip Voltage Bias Distribution Scheme
Generation of a reference voltage which is distributed on the chip as a current to slave bias circuits.
45 Ching-Yuan Yang / EE, NCHUAIC Lab.
SIMULATION AND MEASUREMENT OF OP AMPS
46 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation and Measurement Considerations
Objectives:
The objective of simulation is to verify and optimize the design.
The objective of measurement is to experimentally confirm the specifications.
Similarity Between Simulation and Measurement:
Same goals
Same approach or technique
Differences Between Simulation and Measurement:
Simulation can idealize a circuit
Measurement must consider all nonidealities
47 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulating or Measuring the Open-Loop Transfer Function of the Op AmpCircuit (Darkened op amp identifies the op amp under test):
Simulation:This circuit will give the voltage transfer function curve. This curve should identify:1) The linear range of operation2) The gain in the linear range3) The output limits4) The systematic input offset voltage5) DC operating conditions, power dissipation6) When biased in the linear range, the small-signal frequency response can be
obtained.7) From the open-loop frequency response, the phase margin can be obtained (F = 1).
Measurement:This circuit probably will not work unless the op amp gain is very low.
48 Ching-Yuan Yang / EE, NCHUAIC Lab.
A More Robust Method of Measuring the Open-Loop Frequency ResponseCircuit:
Resulting Closed-Loop Frequency Response:
Make the RC product as large as possible.
49 Ching-Yuan Yang / EE, NCHUAIC Lab.
Example 6.6-1 – Measurement of the Op Amp Open-Loop GainDevelop the closed-loop frequency response for op amp circuit shown which is used to measure the open-loop frequency response. Sketch the closed-loop frequency response of the magnitude of Vout/Vin if the low frequency gain is 4000 V/V, the GB = 1MHz, R = 10MΩ, and C = 10µF. (Ignore RL and CL)SolutionThe open-loop transfer function of the op amp is
The closed-loop transfer function of the op amp can be expressed as
Substituting, Av(s) gives,
The magnitude of the closed-loop frequency response is plotted above.
( ) ππ
500102
)0(/)(
6
+×
=+
=sAGBs
GBsAv
v
[ ] [ ]01.0
)(01.0
)01.0(
/1)(
)/1()/1(
/)()/1()()/1(
)/1(/1)(
)/1(/1)(
+++−
=++
+−=
+++−
=
+
+−
=
+
+−
=
sAs
s
RCsARCs
RCsRCsARCssARCs
vv
vvRCs
RCsAvvsCR
sCsAv
vv
v
v
IN
OUT
INOUTvINOUTvOUT
)72.1529)(04.41()01.0(102
102)500)(01.0(102102
6
4
46
+++×−
=
×+++×−×−
=
sss
sss
vv
IN
OUT
π
ππππ
50 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation and Measurement of Open-Loop Frequency Response with Moderate Gain Op Amps
Make R as large and measure vout and vi to get the open loop gain.
51 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation or Measurement of the Input Offset Voltage of an Op Amp
Types of offset voltages:1) Systematic offset - due to mismatches in current mirrors, exists even with
ideally matched transistors.2) Mismatch offset - due to mismatches in transistors (normally not available in
simulation except through Monte Carlo methods).
52 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation of the Common-Mode Voltage Gain
Make sure that the output voltage of the op amp is in the linear region.
53 Ching-Yuan Yang / EE, NCHUAIC Lab.
Measurement of CMRR and PSRRConfiguration:
Note that vI ≈ vOS / 1000 or vOS ≈ 1000vI
How Does this Circuit Work?CMRR: PSRR:1.) Set VDD’ = VDD + 1V 1.) Set VDD’ = VDD + 1V
VSS’ = VSS + 1V VSS’ = VSS
vOUT’ = vOUT + 1V vOUT’ = 0V2.) Measure vOS called vOS1 2.) Measure vOS called vOS3
3.) Set VDD’ = VDD − 1V 3.) Set VDD’ = VDD − 1VVSS’ = VSS − 1V VSS’ = VSS
vOUT’ = vOUT − 1V vOUT’ = 0V4.) Measure vOS called vOS2 4.) Measure vOS called vOS4
5.) 5.)
Note:PSRR− can be measured similar to PSRR+ by changing only VSS.
The ±1V perturbation can be replaced by a sinusoid to measure CMRR or PSRR as follows:
12
2000OSOS vv
CMRR−
=34
2000OSOS vv
PSRR−
=+
.1000M and ,1000 ,1000
os
cm
os
dd
os
dd
vvRRC
vvPSRR
vvPSRR ⋅
=⋅
=⋅
= ++
I
PS
ps
out
id
out
I
CM
icm
out
id
out
cm
vd
vv
vvvv
PSRR
vv
vvvv
AACMRR
∆∆
=
=
∆∆
=
==
54 Ching-Yuan Yang / EE, NCHUAIC Lab.
How Does the Previous Idea Work?
A circuit is shown which is used to measure the CMRR and PSRR of an op amp. Prove that the CMRR can be given as
SolutionThe definition of the common-mode rejection ratio is
However, in the above circuit the value of vout is the same so that we get .But vid = vi and vos ≈ 1000 vi = 1000 vid vid = vos / 1000 .Substituting in the previous expression gives,
os
icm
vvCMRR 1000
=
==
icm
out
id
out
cm
vd
vvvv
AACMRR
id
icm
vvCMRR =
os
icm
os
icm
vv
vvCMRR 10001000/
==
55 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation of CMRR of an Op Amp
None of the above methods are really suitable for simulation of CMRR.Consider the following:
cmv
cmcm
v
cmout
cmcmoutvcmvout
VAAV
AAV
VAVAVVAVVAV
±≈
+±
=
±−=
+
±−=
1
2)( 21
21
out
cm
cm
v
VV
AACMRR ==∴
56 Ching-Yuan Yang / EE, NCHUAIC Lab.
CMRR of Ex. 6.3-1 using the Above Method of Simulation
57 Ching-Yuan Yang / EE, NCHUAIC Lab.
Direct Simulation of PSRR
Circuit:
ddv
dddd
v
ddout
ddddoutvddddvout
VAAV
AAV
VAVAVAVVAV±
≈+±
=
±−=±−=
1
)( 21
out
dd
dd
v
VV
AAPSRR ==+∴ and
out
ss
ss
v
VV
AAPSRR ==−
Works well as long as CMRR is much greater than 1.
58 Ching-Yuan Yang / EE, NCHUAIC Lab.
Simulation or Measurement of ICMR
Initial jump in sweep is due to the turn-on of M5.Should also plot the current in the input stage (or the power supply current).
59 Ching-Yuan Yang / EE, NCHUAIC Lab.
Measurement or Simulation of the Open-Loop Output Resistance
Method 1:
Method 2:
−= 1
02
01
VVRR Lout or vary RL until VO2 = 0.5VO1 Rout = RL
v
o
o
v
oout A
RR
ARR
R 100100100
111
≈
++=
−
60 Ching-Yuan Yang / EE, NCHUAIC Lab.
Measurement or Simulation of Slew Rate and Settling Time
If the slew rate influences the small signal response, then make the input step size small enough to avoid slew rate (i.e. less than 0.5V for MOS).
61 Ching-Yuan Yang / EE, NCHUAIC Lab.
Measurement of Phase Margin from Overshoot
It can be shown (Appendix C) that:
For example, a 5% overshoot corresponds to a phase margin of approximately 64°.
[ ]
−−
=
−+=
2
241-
1100exp
21457.2958cos
ζπζ
ζζ
(%) Overshoot
(Degree) Margin Phase
62 Ching-Yuan Yang / EE, NCHUAIC Lab.
Example 6.6-2: Simulation of the CMOS Op Amp of Ex. 6.3-1.
The op amp designed in Example 6.3-1 and shown in Fig. 6.3-3 is to be analyzed by SPICE to determine if the specifications are met. The device parameters to be used are those of Tables 3.1-2 and 3.2-1. In addition to verifying the specifications of Example 6.3-1, we will simulate PSRR+ and PSRR−.
Solution/SimulationThe op amp will be treated as a subcircuit in order to simplify the repeated analyses. Table 6.6-1 gives the SPICE subcircuit description of Fig. 6.3-3. While the values of AD, AS, PD, and PS could be calculated if the physical layout was complete, we will make an educated estimate of these values by using the following approximations.
AS = AD ≈ W[L1 + L2 + L3]PS = PD ≈ 2W + 2[L1 + L2 + L3]
63 Ching-Yuan Yang / EE, NCHUAIC Lab.
where L1 is the minimum allowable distance between the polysilicon and a contact in the moat (Rule 5C of Table 2.6-1), L2 is the length of a minimum-size square contact to moat (Rule 5A of Table 2.6-1), and L3 is the minimum allowable distance between a contact to moat and the edge of the moat (Rule 5D of Table 2.6-1).
Op Amp Subcircuit:
.SUBCKT OPAMP 1 2 6 8 9M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18UM2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18UM3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42UM4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42UM5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21UM6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200UM7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40UM8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21UCC 5 6 3.0P.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P+LD=0.016U TOX=14N.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14NIBIAS 8 7 30U.ENDS
64 Ching-Yuan Yang / EE, NCHUAIC Lab.
PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 6.6-2 OPEN LOOP CONFIGURATION.OPTION LIMPTS=1000VIN+ 1 0 DC 0 AC 1.0VDD 4 0 DC 2.5VSS 0 5 DC 2.5VIN - 2 0 DC 0CL 3 0 10PX1 1 2 3 4 5 OPAMP
…(Subcircuit of previous slide)
….OP.TF V(3) VIN+.DC VIN+ -0.005 0.005 100U.PRINT DC V(3).AC DEC 10 1 10MEG.PRINT AC VDB(3) VP(3).PROBE (This entry is unique to PSPICE).END
65 Ching-Yuan Yang / EE, NCHUAIC Lab.
Open-loop transfer characteristic of Example 6.6-2:
66 Ching-Yuan Yang / EE, NCHUAIC Lab.
Open-loop transfer frequency response of Example 6.3-1:
67 Ching-Yuan Yang / EE, NCHUAIC Lab.
Input common mode range of Example 6.3-1:
EXAMPLE 6.6-2 UNITY GAIN CONFIGURATION..OPTION LIMPTS=501VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U + -2 4.01U -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)VDD 4 0 DC 2.5 AC 1.0VSS 0 5 DC 2.5CL 3 0 20PX1 1 3 3 4 5 OPAMP
…(Subcircuit of Table 6.6-1)
….DC VIN+ -2.5 2.5 0.1.PRINT DC V(3).TRAN 0.05U 10U 0 10N.PRINT TRAN V(3) V(1).AC DEC 10 1 10MEG.PRINT AC VDB(3) VP(3).PROBE.END
68 Ching-Yuan Yang / EE, NCHUAIC Lab.
Positive PSRR of Example 6.3-1:
69 Ching-Yuan Yang / EE, NCHUAIC Lab.
Negative PSRR of Example 6.3-1:
70 Ching-Yuan Yang / EE, NCHUAIC Lab.
Large-signal and small-signal transient response of Example 6.3-1:
Why the negative overshoot on the slew rate?If the current sink, M7, cannot sink sufficient current then the output stage is slewing and it can only respond to changes at the output via the external feedback path to the input of the amplifier which involves a delay.Note that –dvout/dt ≈ − 2V/0.3µs = − 6.67V/µs. For a 10pF capacitor this requires 66.7µA and only 95µA − 66.7µA = 28µA is available for Cc.For the positive slew rate, M6 can provide whatever current is required by the capacitors and can immediately respond to changes at the output.
71 Ching-Yuan Yang / EE, NCHUAIC Lab.
Comparison of the Simulation Results with the Specifications of Example 6.3-1:
Specification(Power supply = 2.5V)
Design(Ex. 6.3-1)
Simulation(Ex. 6.6-2)
Open Loop Gain >5000 10,000
GB (MHz) 5 MHz 5 MHz
Input CMR (Volts) -1V to 2V -1.2 V to 2.4 V
Slew Rate (V/µsec) >10 (V/µsec) +10, -7 (V/µsec)
Pdiss (mW) < 2mW 0.625mW
Vout range (V) 2V +2.3V, -2.2V
PSRR+ (0) (dB) - 87
PSRR- (0) (dB) 106-
Phase margin (degrees) 60o 65o
Output Resistance (kΩ) 122.5kΩ-
72 Ching-Yuan Yang / EE, NCHUAIC Lab.
Why is the negative-going overshoot larger than the positive-going overshoot on the small-signal transient response of Example 6.6-2 (right-hand figure of page 6.6-24)?SolutionConsider the following circuit and waveform:
During the rise time, iCL = CL(dvout / dt) = 10pF(0.2V/0.1µs) = 20µA and iCc = 3pF(2V/µs) = 6µA ∴ i6 = 95µA + 20µA + 6µA = 121µA gm6 = 1066µS (nominal was 942.5µS)During the fall time, iCL = CL(−dvout / dt) = 10pF(−0.2V/0.1µs) = −20µA and iCc = −3pF(2V/µs) = −6µA ∴ i6 = 95µA − 20µA − 6µA = 69µA gm6 = 805µSThe dominant pole is p1 ≈ (RI gm6 RII Cc)−1 where RI = 0.649MΩ, RII = 122.5kΩ, and Cc = 3pF. ∴ p1(95µA) = 4,160 rad/sec, p1(121µA) = 3,678 rad/sec, and p1(69µA) = 4,870 rad/sec .Thus, the phase margin is less during the fall time than the rise time.
73 Ching-Yuan Yang / EE, NCHUAIC Lab.
Analog Cells/Macros Layout
74 Ching-Yuan Yang / EE, NCHUAIC Lab.
Two-Stage OTA
75 Ching-Yuan Yang / EE, NCHUAIC Lab.
76 Ching-Yuan Yang / EE, NCHUAIC Lab.
77 Ching-Yuan Yang / EE, NCHUAIC Lab.
Layout of Differential Pair OP Amplifier Example
78 Ching-Yuan Yang / EE, NCHUAIC Lab.
Layout of Differential Pair OP Amplifier Example
Case1 Case2
Case3
79 Ching-Yuan Yang / EE, NCHUAIC Lab.
Layout of Differential Pair
Input stage M1&M2, common centroid to reduce offset, don’t use minimum size for process variation.M3&M4, symmetric, same orientation.No signal crossing allowed between M1&M3, M2&M4.Node N2 can only use metal wire as short as possible, avoid crossing.Capacitor layout in Well connected to independent power line not sharing with OP power line independent well to M5 and M7 to avoid noise.Substrate of M1&M2 connected to N1 ( triple well required ), notthe power line.Keep input and output nodes away, put the capacitor between them.Put the capacitor between M6 and M7 ( case3 ), to avoid latch up.
80 Ching-Yuan Yang / EE, NCHUAIC Lab.
Output node connected to capacitor bottom plate to avoid the substrate noise coupled to input stage and be amplified.Don’t cross input and output wire to avoid feedback oscillation.Keep drain nodes of MOS as small as possible to reduce the output capacitance.Divide the compensation capacitor into multiple units to avoid antenna effect.
81 Ching-Yuan Yang / EE, NCHUAIC Lab.
A one-stage circuit for low-frequency applications
82 Ching-Yuan Yang / EE, NCHUAIC Lab.
A conventional two-stage circuits
83 Ching-Yuan Yang / EE, NCHUAIC Lab.
84 Ching-Yuan Yang / EE, NCHUAIC Lab.
85 Ching-Yuan Yang / EE, NCHUAIC Lab.
Current Mirror
Layout of current mirror without ∆W correction techniques.
Layout of current mirror with ∆W correction techniques.