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Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
ECEN620: Network TheoryBroadband Circuit Design
Fall 2020
Lecture 3: Phase-Locked Loop Systems
Announcements
2
• HW1 due Sept 10
Reading/References
3
• Chapter 2, 3, 5, & 12 of Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005. • https://onlinelibrary.wiley.com/doi/book/10.1002/0471732699
• Chapter 1-3.4 of “Low-Power Low-Jitter On-Chip Clock Generation,” M. Mansuri, Ph.D. thesis, UCLA, 2003.• Posted on website
• Other references• M. Perrott, High Speed Communication Circuits and Systems Course, MIT
Open Courseware• Chapter 2 of Phase-Locked Loops, 3rd Ed., R. Best, McGraw-Hill, 1997.• Chapter 4 of Phase-Locked Loops for Wireless Communications, D. Stephens,
Kluwer, 2002.
Agenda
4
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
PLL Block Diagram
5
[Perrott]
• A phase-locked loop (PLL) is a negative feedback system where an oscillator-generated signal is phase AND frequency locked to a reference signal
PLL Applications• PLLs applications
• Frequency synthesis• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation• Phase aligning an internal clock to an I/O clock
• Clock recovery• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation• Wireless systems• Spread-spectrum clocking
6
Forward Clock I/O Circuits
7
• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit• DLL/PI• Injection-Locked Oscillator
Embedded Clock I/O Circuits
8
• TX PLL
• TX Clock Distribution
• CDR• Per-channel PLL-based• Dual-loop w/ Global PLL &
• Local DLL/PI• Local Phase-Rotator PLLs• Global PLL requires RX
clock distribution to individual channels
Xilinx 0.5-32Gb/s Transceiver Clocking
9
• LC-PLL with 2 LC-VCOs used to cover high data rates (8-32Gb/s)
• Ring-PLL used for lower data rates• CML clock distribution with active inductive loads used
for low jitter
Active Inductor based Clock Distribution
Frac-N LC PLL1, 2
Ring PLL
DCCIQ CAL
Receiver
DCCTransmitter
Channels 1-4
I/Q1, I/Q2
∑
VCOLB
PPF
VCOHB
2PI (D,X,S)
Technology CMOS 16nm FinFET Power Supply (Vavcc, Vavtt, Vaux) 0.9 V, 1. 2V, 1.8 V
Frequency range 500 Mb/s – 32.75 Gb/s Transceiver Quad area 2.625 mm × 2.218 mm
LC PLL range 8-16.375 GHz Ring PLL range 2-6.25 GHz
TX PRBS7 jitter at 32.75Gb/s TJ: 5.39 ps, RJ: 190 fs 32.75Gb/s RX JTOL @ 30MHz
@ 100MHz 0.45 UI 0.6 UI
Channel loss at 32.75Gb/s 30 dB Measured BER at 32.75Gb/s < 10-15
Power at 32.75Gb/s with DFE 577mW/ch (17.6pJ/b)
[Upadhyaya VLSI 2016]
Agenda
10
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
Linear PLL Model
11
• Phase is generally the key variable of interest• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)• Input phase deviation amplitude is small enough to maintain operation in
lock range
Phase Detector
• Detects phase difference between feedback clock and reference clock• The loop filter will filter the phase detector output, thus to characterize
phase detector gain, extract average output voltage (or current for charge-pump PLLs)
12
ref
fb
e
Loop Filter
• Lowpass filter extracts average of phase detector error pulses
13
I
I
VCO ControlVoltage
C1
R
C2
Charging
Discharging
VDD
VSSF(s)
Voltage-Controlled Oscillator
• Time-domain phase relationship
14
VDDVDD/20
0 1KVCO
tvKtt cVCOoutout 00
dtdt tvKtt cVCOoutout Laplace Domain Model
out(t)
Loop Divider
• Time-domain model
15
tN
t outfb 1
tN
tN
t outoutfb 1dt1
[Perrott]
out(t) fb(t)
Phase & Frequency Relationships
16
• Phase Step
t
o
t
tdt
d
td
phase of time) vschange of (rate derivativefirst theisFrequency Angular
ttu
tu
111
111
tsint
phase and tfrequency angular with t sinusoid aConsider
frequencyin change No
sin 11
1
tuttu
tut
[Best]
Phase & Frequency Relationships
17
• Frequency Step
phasein ramp a produces stepfrequency A
where
sinsin
1
1001
01
tt
tttttu
t
[Best]
tt 1
phasein change quadratic a produces rampfrequency A
2 where
sin2
sinsin
21
102
00
01
01
tt
ttttdtu
tt
t
Phase & Frequency Relationships
18
[Best]
• Frequency Ramp
0 t
0
21 2
tt
Understanding PLL Frequency Response• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)• Input phase deviation amplitude is small enough to maintain operation in
lock range• Frequency domain analysis can tell us how well the PLL tracks the input
phase as it changes at a certain frequency• PLL transfer function is different depending on which point in the loop
the output is responding to
19
Input phase response VCO output response
[Fischette]
Open-Loop PLL Transfer Function
20
• Open-loop response generally decreases with frequency
Forward Path Gain: 𝐺 𝑠
Open-Loop Response:
Closed-Loop PLL Transfer Function
21
NsFKKs
sFKK
NsG
sGsssH
VCOPD
VCOPD
ref
out
1
NsG
NsG
NsG
sNsFKKl
sG
VCOPD
101t Determinan System
101t DeterminanPath Forward
Gain Loop
GainPath Forward
1
1
• Low-pass response whose overall order is set by F(s)
PLL Error Transfer Function
22
NsFKKs
s
NsGs
ssEVCOPDref
e
1
1
NsG
NsG
NsG
sNsFKKl VCOPD
101t Determinan System
101t DeterminanPath Forward
Gain Loop
1GainPath Forward
1
1
• Ideally, we want this to be zero• Phase error generally increases with
frequency due to this high-pass response
PLL Order and Type• The PLL order refers to the number of poles in the
closed-loop transfer function• This is typically one greater than the number of loop
filter poles
• The PLL type refers to the number of integrators within the loop• A PLL is always at lease Type 1 due to the VCO
integrator
• Note, the order can never be less than the type
23
First-Order PLL
• Simple first-order low-pass transfer function
• Closed-loop bandwidth is equal to the DC loop gain magnitude
24
DCdBVCOPD
DCVCOPD
dB
DC
DC
dB
dB
VCOPD
VCOPD
VCOPDs
DC
DCVCOPD
Kss
ss
NKKKs
ssE
KN
KKK
KsNK
sN
NKKKs
KKKsH
NKKK
NssGK
sNK
sKKKsG
KsF
31
13
3
3
1
1
10
1
1
:FunctionError
:Bandwidth Loop-Closed
:FunctionTransfer
lim :MagnitudeGain Loop DC
:GainPath Forward
• Note, the “DC Loop Gain Magnitude” is not simply the PLL open-loop gain evaluated at s=0. It is
.lim0 N
ssGKs
DC
• This expression cancels the VCO DC pole and allows a comparison between PLLs of different orders and types. It is useful to predict the steady-state phase error. See Gardner 2.2.3 and 5.1.1.
First-Order PLL Tracking Response• The PLL’s tracking behavior, or how the phase error responds to an input
phase change, varies with the PLL type
25
• Phase Step Response
frequencyin change No
sin 11
1
tuttu
tut
[Best]
• The final value theorem can be used to find the steady-state phase error
0limlim00
DC
ss KssssE
s
• All PLLs should have no steady-state phase error with a phase step error• Note, this assumes that the frequency of operation is the same as the VCO
center frequency (Vctrl=0). Working at a frequency other than the VCO center frequency is considered having a frequency offset (step).
First-Order PLL Tracking Response• Frequency Offset (Step)
26
• The final value theorem can be used to find the steady-state phase error
DCDC
ss KKsssE
s
020limlim
• With a frequency offset (step), a first-order PLL will lock with a steady-state phase error that is inversely proportional to the loop gain
phasein ramp a produces stepfrequency A
where
sinsin
1
1001
01
tt
tttttu
t
[Best]
First-Order PLL Issues• The DC loop gain directly sets the PLL bandwidth
• No degrees of freedom
• In order to have low phase error, a large loop gain is necessary, which implies a wide bandwidth• This may not be desired in applications where we would like to filter
input reference clock phase noise
• First-order PLLs offer no filtering of the phase detector output• Without this filtering, the PD may not be well approximated by a
simple KPD factor• Multiplier PDs have a “second-harmonic” term• Digital PDs output square pulses that need to be filtered
27
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter
28
CRCR
sssF
2211
21
2
11
Passive Lag-Lead Loop Filter [Allen]
29
CRCR
sssF
2211
21
2
11
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter
22
2
2
21
2121
22
221
2
22
2
2121
22
221
2
0
21
221
2
21
2
2 :FunctionError
2 :Factor Damping
:Frequency Natural
1
1
2
2
1
1
:FunctionTransfer
lim :MagnitudeGain Loop DC
1
1
11 :GainPath Forward
nn
VCOPD
n
VCOPD
n
VCOPDn
DCDC
DC
nn
nVCOPD
nn
VCOPDVCOPD
VCOPD
VCOPDs
DC
DCVCOPD
ss
KKNss
sE
KKN
NKK
KsKs
sKN
ss
sKK
N
N
NKKsNKKs
sKK
sH
NKK
NssGK
ss
sNK
sssKKsG
Q21 :Note
30
• Phase Step Response
step phase a with zero be shoulderror phase Again,
02
limlim 22
2
00
nn
VCOPD
n
ss ssKK
NssssE
s
• A second-order type-1 PLL will still lock with a phase error if there is a frequency offset!
Second-Order Type-1 PLL Tracking Response
• Frequency Offset (Step)
DCnn
VCOPD
n
ss KssKK
NsssE
s
22
2
020 2limlim
Second-Order Type-1 PLL Properties• While the second-order type-1 PLL will still lock
with a phase error with a frequency offset, it is much more useful than a first-order PLL
• There are sufficient design parameters (degrees of freedom) to independently set n, , and KDC
• The loop filter conditions the phase detector output for proper VCO control
• Loop stability needs to be considered for the second-order system
31
• Note, this type of loop filter is typically used with a charge-pump driving it. Thus, the filter transfer function is equal to the impedance.
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter
32
s
RCsR
sF
1
Passive Series-RC Loop Filter
33
22
2
222
0
2
2 :FunctionError
2 :Factor Damping
:Frequency Natural
22
21
:FunctionTransfer
lim :MagnitudeGain Loop DC
1
:GainPath Forward
nn
n
VCOPDn
nn
nn
VCOPDVCOPD
VCOPD
sDC
VCOPD
ssssE
RC
NCKK
ss
sN
NCKKs
NRKKs
RCsRKK
sH
NssGK
sRC
sRKKsG
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter
s
RCsR
sF
1
34
• Phase Step Response
step phase a with zero be shoulderror phase Again,
02
limlim 22
2
00
nn
ss sssssE
s
• A second-order type-2 PLL will lock with no phase error with a frequency offset!
Second-Order Type-2 PLL Tracking Response
• Frequency Offset (Step)
02
limlim 22020
nn
ss sssssE
s
Second-Order Type-2 PLL Properties• A big advantage of the type-2 PLL is that it has
zero phase error even with a frequency offset• This is why type-2 PLLs are very popular
• A type-2 PLL requires a zero in the loop filter for stability.• Note, this is not required in a type-1 PLL
• This zero can cause extra peaking in the frequency response• Important to minimize this in some applications, such
as cascaded CDR systems
35
Agenda
36
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
Feedback Configuration
37
ACL(s)
Here f = feedback factor
[Karsilayan]
fpaf
Aa pCL 100 10 :large is If
𝑎 𝑠𝑉𝑉 𝑠
𝑎
1 𝑠𝑝
𝐴 𝑠𝑉𝑉 𝑠
𝑎 𝑠1 𝑎 𝑠 𝑓
𝑎1 𝑎 𝑓
1 𝑠1 𝑎 𝑓 𝑝
38
[Karsilayan]Note: a(s) can have higher-order poles
39
[Karsilayan]
40
[Karsilayan]
First-Order PLL
41
DCdBVCOPD
DCVCOPD
dB
DC
DC
dB
dB
VCOPD
VCOPD
VCOPDs
DC
DCVCOPD
Kss
ss
NKKKs
ssE
KN
KKK
KsNK
sN
NKKKs
KKKsH
NKKK
NssGK
sNK
sKKKsG
KsF
31
13
3
3
1
1
10
1
1
:FunctionError
:Bandwidth Loop-Closed
:FunctionTransfer
lim :MagnitudeGain Loop DC
:GainPath Forward
First-Order PLL Stability• Open-loop Bode
plots are useful for checking stability via the phase margin
• A first-order PLL is inherently stable and always has 90phase margin
42
(dB) log20 10 NjG
s
NKs
KKKsG DCVCOPD 1
43
22
2
2
21
2121
22
221
2
22
2
2121
22
221
2
0
21
221
2
21
2
2 :FunctionError
2 :Factor Damping
:Frequency Natural
1
1
2
2
1
1
:FunctionTransfer
lim :MagnitudeGain Loop DC
1
1
11 :GainPath Forward
nn
VCOPD
n
VCOPD
n
VCOPDn
DCDC
DC
nn
nVCOPD
nn
VCOPDVCOPD
VCOPD
VCOPDs
DC
DCVCOPD
ss
KKNss
sE
KKN
NKK
KsKs
sKN
ss
sKK
N
N
NKKsNKKs
sKK
sH
NKK
NssGK
ss
sNK
sssKKsG
CRCR
sssF
2211
21
2
11
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter
Second-Order Type-1 PLL w/ Lag-Lead Filter Stability
44
Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7
• Assuming a decade spacing between filter pole and zero
Normalizing KDC for =1
• A larger KDC provide a more stable system
21
221
2
1
1
ss
sNKsG
DC (dB) log20 10 NjG
Second-Order Type-1 PLL w/ Lag-Lead Filter Output Response w/ Phase Step
45
Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7
• Note, time axis is scaled by sqrt(KDC) in order to view the phase step plots on one graph
Root Locus• A Root-Locus Plot is a plot of the closed-loop poles in the
complex s-plane as the loop gain changes from zero to very large
• Useful in visualizing system stability and sensitivity to variations in loop gain
• For stability, all poles should lie within the left-half plane, i.e no poles should be in the right-half plane
• A good design ensures that the poles have sufficient margin from the imaginary axis for proper stability, damping, and acceptable gain peaking
46
47
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Root Locus
2121
22
221
2
21
221
2
1
1
:Loop-Closed 1
1
N:Loop-Open
DCDC
DCDC
KsKs
sKNsH
ss
sKsG
2=1, 1=9• Initial pole values with
zero loop gain are the open-loop poles
1.01 021
21
pp
• Final pole values with infinite loop gain are the open-loop zeros
22
1 1 1 pp
48
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Root Locus
2121
22
221
2
21
221
2
1
1
:Loop-Closed 1
1
N:Loop-Open
DCDC
DCDC
KsKs
sKNsH
ss
sKsG
2=1, 1=9
K1 for =10.1*K1 =0.38
10*K1 =3.09
For ≤1
49
Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Closed-Loop Response
2121
22
221
2
21
221
2
1
1
:Loop-Closed 1
1
N:Loop-Open
DCDC
DCDC
KsKs
sKNsH
ss
sKsG
20*log10|H(j)|
/n t*sqrt(KDC)
Normalized Phase Step Response
Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7
• A larger KDC provide a more stable system and wider loop bandwidth
50
22
2
222
2
22
2 :FunctionError
21
2 :Factor Damping
:Frequency Natural
1
22
21
:FunctionTransfer
11
:GainPath Forward
factor gain loop a Define
nn
n
VCOPDn
nn
nn
VCOPDVCOPD
VCOPD
VCOPD
VCOPD
ssssE
KRCRC
RCK
NCKK
RCKKss
RCsNK
ss
sN
NCKKs
NRKKs
RCsRKK
sH
sRC
sNK
sRC
sRKKsG
NRKKK
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter
s
RCsR
sF
1
51
R=1, C=1• Initial pole values with
zero loop gain are the open-loop poles
0 0 21 pp
• Final pole values with infinite loop gain are the open-loop zeros
21 1 1 pRC
p
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Root Locus
RCKKss
RCsNK
sHs
RCsK
sG
2
2
1
:Loop-Closed
1
N :Loop-Open
52
R=1, C=1
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Root Locus
RCKKss
RCsNK
sHs
RCsK
sG
2
2
1
:Loop-Closed
1
N :Loop-Open
K1 for =10.1*K1 =0.38
10*K1 =3.09
53
Normalizing K for =1
• A larger K provide a more stable system
(dB) log20 10 NjG
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Stability
2
1
sRC
sNKsG
Norm. KDC Zeta PM0.1 0.38 351 1 76.210 3.09 88.6
54
20*log10|H(j)|
/n t*sqrt(KDC)
Normalized Phase Step Response
• A larger KDC provide a more stable system and wider loop bandwidth
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Closed-Loop Response
RCKKss
RCsNK
sHs
RCsK
sG
2
2
1
:Loop-Closed
1
N :Loop-Open
Norm. KDC Zeta PM0.1 0.38 351 1 76.210 3.09 88.6
Typical Charge-Pump PLL Loop Filter
• A secondary capacitor C2 is often added for additional filtering to reduce reference spurs
• This introduces an extra pole and potential stability concerns
55
I
I
VCO ControlVoltage
C1
R
C2
Charging
Discharging
VDD
VSSF(s)
sRC
sRsF
1
1
21
21
12
11
CRCCCss
RCs
CsF
w/o C2
w/ C2
56
11
11
1
2
1
2132
21
2122
212
2
21
213
21
212
1
2
1
2132
1
212
2
21
213
12
21
2122
1
21
212
12
21
2 :Factor Damping
:Frequency Natural
withsystemorder -second a as eapproximatcan frequency,high aat is pole- third theIf
:FunctionError
111
:FunctionTransfer
111
:GainPath Forward
factor gain loop a Define
KRCRC
RCK
NCKK
RCKKss
CCCsRC
CRCCCssRC
CNRCKKs
NCKKs
CRCCCs
CRCCCss
sE
RCKKss
CCCsRC
RCsNK
CNRCKKs
NCKKs
CRCCCs
RCs
CKK
sH
CRCCCssRC
RCsNK
CRCCCss
RCs
CKK
sG
NRKKK
n
VCOPDn
VCOPDVCOPD
VCOPDVCOPD
VCOPD
VCOPD
VCOPD
Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole
21
21
12
11
CRCCCss
RCs
CsF
57
R=1, C1=1, C2=0.1• Initial pole values with
zero loop gain are the open-loop poles
11 0 021
21321
CRCCCppp
• Final pole values with infinite loop gain
jpRC
p 5 1 13,21
Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Root Locus
Open Loop: 𝐺 𝑠
N
𝐾 𝑠 1𝑅𝐶
𝑅𝐶 𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
Closed Loop: 𝐻 𝑠𝑁𝐾 𝑠 1
𝑅𝐶
𝑅𝐶 𝑠 𝐶 𝐶𝐶 𝑠 𝐾𝑠 𝐾
𝑅𝐶
58
R=1, C1=1, C2=0.1
Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Root Locus
K1 for =10.1*K1 =0.38
*A third-order system doesn’t formally have a value. Here we are using the same loop parameter values as the second-order type-2 PLL for a given .
Open Loop: 𝐺 𝑠
N
𝐾 𝑠 1𝑅𝐶
𝑅𝐶 𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
Closed Loop: 𝐻 𝑠𝑁𝐾 𝑠 1
𝑅𝐶
𝑅𝐶 𝑠 𝐶 𝐶𝐶 𝑠 𝐾𝑠 𝐾
𝑅𝐶
59
Normalizing K for =1
• A larger K provide a more stable system
(dB) log20 10 NjG
Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Stability
2
1
sRC
sNKsG
Norm. K Zeta PM0.1 0.38 351 1 76.210 3.09 88.6
60
Normalizing K for =1
• A larger K may not provide a more stable system
(dB) log20 10 NjG
Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Stability
21
2122
1
1
CRCCCssRC
RCsNK
sG
Norm. K Zeta* PM0.1 0.38 301 1 5510 3.09 27
*A third-order system doesn’t formally have a value. Here we are using the same loop parameter values as the second-order type-2 PLL for a given .
61
20*log10|H(j)|
/n t*sqrt(KDC)
Normalized Phase Step Response
• If K is increased too high frequency peaking and transient ringing occurs!
Third-Order Type-2 PLL Closed-Loop Response
Norm. K Zeta* PM0.1 0.38 301 1 5510 3.09 27
Open Loop: 𝐺 𝑠
N
𝐾 𝑠 1𝑅𝐶
𝑅𝐶 𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
Closed Loop: 𝐻 𝑠𝑁𝐾 𝑠 1
𝑅𝐶
𝑅𝐶 𝑠 𝐶 𝐶𝐶 𝑠 𝐾𝑠 𝐾
𝑅𝐶
Instability and the Nyquist Criterion
62
N1factor feedback by the multiplied gain forward theis PLL aFor
NsGsT
sGsT
[Karsilayan]
63
Frequency Sweep of Loop Gain, T(s)[Karsilayan]
: PLL aFor NsGsT
Agenda
64
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)
65
Phase Detector
• Detects phase difference between feedback clock and reference clock
• The loop filter will filter the phase detector output, thus to characterize phase detector gain, extract average output voltage
• The KPD factor can change depending on the specific phase detector circuit
66V/rad are units
:filter loop less-dimension w/ PLL
PDK
Dimension-Less Loop Filter
• Lowpass filter extracts average of phase detector signal
• No units for the dimension-less loop filter67
CRCR
sssF
2211
21
2
11
Example: Passive Lag-Lead Loop Filter[Allen]
Voltage-Controlled Oscillator
• Time-domain phase relationship
68
VDDVDD/20
0 1KVCO
tvKtt cVCOoutout 00
dtdt tvKtt cVCOoutout Laplace Domain Model
out(t)
Vsrad102
VMHz12
Vsrad are units
6
VCOK
Loop Divider
• Time-domain model
69
tN
t outfb 1
tN
tN
t outoutfb 1dt1
[Perrott]
out(t) fb(t)
• The loop divider is dimension-less in the PLL linear model
PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)
70less-unit isDivider Loop
Vsrad are units
less-unit isFilter LoopV/rad are units
VCO
PD
K
K
71
[Mansuri]
PLL Units w/ Impedance Filter (Charge-Pump PLL)
2CP
PDDIKK
Phase Frequency Detector (PFD)• Phase Frequency Detector allows for wide
frequency locking range, potentially entire VCO tuning range
• 3-stage operation with UP and DOWN outputs• Net difference in pulse width represents phase error• UP longer = Positive • DN longer = Negative
• Edge-triggered results in duty cycle insensitivity
72
• The un-averaged PFD gain (ratio of net output pulse time width with input phase error time) is typically “1” and dimension-less
Averaged PFD Transfer Characteristic
• Constant slope and polarity asymmetry about zero phase allows for wide frequency range operation
• The averaged PFD gain is typically “1/(2*pi)” with units of rad-1
73
UP=1 & DN=-1
[Perrott]
Charge Pump• Converts PFD output
signals to charge
• Charge is proportional to PFD pulse widths
74
used isdetector phasedifferent a ifcan vary gain Thisrad
Amps 2
Gain Pump-Charge & PFD Total
radAmps
2 Gain Pump-Charge Averaged
Amps Gain Pump-Charge Averaged-Un
CP
CP
CP
I
II
Loop Filter
• Lowpass filter extracts average of phase detector error pulses
• The units of the filter are ohms75
I
I
VCO ControlVoltage
C1
R
C2
Charging
Discharging
VDD
VSSF(s)
sRC
sRsF
1
1
21
21
12
11
CRCCCss
RCs
CsF
w/o C2
w/ C2
76
[Mansuri]
PLL Units w/ Impedance Filter (Charge-Pump PLL)
2CP
PDDIKK
less-unit isdivider Loop
Vsrad are units , of units hasFilter Loop
radA of units hasgain combined Pump-Charge &Detector Phase Total
averaged if radA averaged,-un ifA are unitsGain Pump Charge
averaged if rad of units averaged,-un if less-unit is 1-
VCO
PD
K
KOnly Average
Once
Agenda
77
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
PLL Noise Transfer Function
78
[Mansuri]
Input Noise Transfer Function
79
222 2
221
nn
nn
n
outn ss
sN
RCKKss
RCsNK
sHIN
IN
RCKKsss
RCsNKK
sK
vsT
oo
n
out
n
outn
ININ
IN2
1
sKo
Input Phase Noise:
Voltage Noise on Input Clock Source:
[Mansuri]
)1 (assumes 2
:factorgain loop aw/ PDVCOCP KN
RKIK
Input Noise Transfer Function
80
222 2
221
nn
nn
n
outn ss
sN
RCKKss
RCsNK
sHIN
IN
RCKKsss
RCsNKK
sK
vsT
oo
n
out
n
outn
ININ
IN2
1
Input Phase Noise:
Voltage Noise on Input Clock Source:
VCO0
VCOn
,10 ,12
26.1 ,253
1N ,12 ,rad 2
10
10*2 ,1 ,1*2
Parameters Simulation
bufdelay
VCOPD
VpsK
VMHzK
kRpFC
VGHzKAK
GHzMHz
VCO Noise Transfer Function
81
22
2
2
2
2 nnn
outn ss
s
RCKKss
ssHVCO
VCO
RCKKss
sKs
Kv
sT VCOVCO
n
out
n
outn
VCOVCO
VCO
2
VCO Phase Noise:
Voltage Noise on VCO Inputs:
KVCO is different if the input is at the Vcntrl input (KVCO) or supply (KVdd)
[Mansuri]
VCO Noise Transfer Function
82
22
2
2
2
2 nnn
outn ss
s
RCKKss
ssHVCO
VCO
RCKKss
sKs
Kv
sT VCOVCO
n
out
n
outn
VCOVCO
VCO
2
VCO Phase Noise:
Voltage Noise on VCO Inputs:
VCO0
VCOn
,10 ,12
26.1 ,253
1N ,12 ,rad 2
10
10*2 ,1 ,1*2
Parameters Simulation
bufdelay
VCOPD
VpsK
VMHzK
kRpFC
VGHzKAK
GHzMHz
Clock Buffer Noise Transfer Function
83
22
2
2
2
2 nnn
outn ss
s
RCKKss
ssHbuf
buf
RCKKss
sK
RCKKss
ss
Ks
Kv
sT VCOdelay
buf
VCOdelay
buf
VCOdelay
n
out
n
outn
bufbuf
buf
2
2
2
2
11
Output Phase Noise:
Voltage Noise on Buffer Inputs:
Kdelay units = (s/V)
[Mansuri]
1buf
VCOdelays
K
Clock Buffer Noise Transfer Function
84
22
2
2
2
2 nnn
outn ss
s
RCKKss
ssHbuf
buf
RCKKss
sK
RCKKss
ss
Ks
Kv
sT VCOdelay
buf
VCOdelay
buf
VCOdelay
n
out
n
outn
bufbuf
buf
2
2
2
2
11
Output Phase Noise:
Voltage Noise on Buffer Inputs:
VCO0
VCOn
,10 ,12
26.1 ,253
1N ,12 ,rad 2
10
10*2 ,1 ,1*2
Parameters Simulation
bufdelay
VCOPD
VpsK
VMHzK
kRpFC
VGHzKAK
GHzMHz
28GHz PLL Phase Noise Example
85
• Charge pump noise dominates at low frequencies• VCO noise at mid-band and high frequencies• Output buffers outside loop dominate at high frequencies
With ~100fs target, no single dominant source -every component contributes
Phas
e No
ise (d
Bc/H
z)
Frequency Offset (Hz) [Turker ISSCC 2019]
PLL Noise Transfer Function Take-Away Points
• The way a PLL shapes phase noise depends on where the noise is introduced in the loop
• Optimizing the loop bandwidth for one noise source may enhance other noise sources
• Generally, the PLL low-pass shapes input phase noise, band-pass shapes VCO input voltage noise, and high-pass shapes VCO/clock buffer output phase noise
86
Agenda
87
• PLL Overview• PLL Linear Model• PLL Stability• PLL Units• PLL Noise Transfer Functions• PLL Transient Behavior
Linear PLL Model
88
• If the phase input amplitude is small, then the linear model can be used to predict the transient response
NsFKKs
s
NsGs
ssEVCOPDref
e
1
1
• Ideally, we want this to be zero• Phase error generally increases with
frequency due to this high-pass response
89
• Phase Step Response
step decayingly exponentiaan is ResponseTransient
:ResponseTransient
step phase a with zero be shoulderror Phase
0limlim :Theorem Value Final theUsing
1
2
00
tK
DC
DCss
DCeKss
s
KsssssE
s
L
First-Order PLL Tracking Response
NKKKK
ss
NKKKs
ssEKsF VCOPDdBDC
dBVCOPD
13
311 , ,
90
• Frequency Offset (Step) Response
step risingly exponentiaan is ResponseTransient
1 :ResponseTransient
offsetfrequency again with loop the tonalproporitioinversely iserror phase The
limlim :Theorem Value Final theUsing
21
2
2
020
tK
DCDC
DCDCss
DCeKKs
ss
KKsssssE
s
L
First-Order PLL Tracking Response
NKKKK
ss
NKKKs
ssEKsF VCOPDdBDC
dBVCOPD
13
311 , ,
91
• Frequency Ramp Response
1 :ResponseTransient
finite is ifinfinity togrow error will phase The
limlim :Theorem Value Final theUsing
2
rad/sec of rate aat ith timelinearly w changing isfrequency input that theAssume
231
3
2
030
2
2
tKDC
DCDC
DC
DCss
ref
DCetKKKs
ss
K
KsssssE
s
tt
L
First-Order PLL Tracking Response
NKKKK
ss
NKKKs
ssEKsF VCOPDdBDC
dBVCOPD
13
311 , ,
NKKK
KsKs
ss
ssKK
NsssE
sssF VCOPD
DCDCDCnn
VCOPD
n
,
1
1
2 ,
11
2121
22
2122
2
21
2
92
• Phase Step Response
yourself thiscompute Try to
1
1
:ResponseTransient
step phase a with zero be shoulderror Phase
01
1
limlim :Theorem Value Final theUsing
2121
22
211
2121
22
21
2
00
DCDC
DCDCss
KsKs
ss
s
KsKss
ssssE
s
L
Second-Order Type-1 PLL Tracking Response
NKKK
KsKs
ss
ssKK
NsssE
sssF VCOPD
DCDCDCnn
VCOPD
n
,
1
1
2 ,
11
2121
22
2122
2
21
2
93
• Frequency Offset (Step) Response
yourself thiscompute Try to
1
1
:ResponseTransient
offsetfrequency again with loop the tonalproporitioinversely iserror phase The
1
1
limlim :Theorem Value Final theUsing
2121
22
212
1
2121
222
21
2
020
DCDC
DCDCDCss
KsKs
ss
s
KKsKss
ssssE
s
L
Second-Order Type-1 PLL Tracking Response
NKKK
KsKs
ss
ssKK
NsssE
sssF VCOPD
DCDCDCnn
VCOPD
n
,
1
1
2 ,
11
2121
22
2122
2
21
2
94
• Frequency Ramp Response
yourself thiscompute Try to
1
1
:ResponseTransient
finite is ifinfinity togrow error will phase The
1
1
limlim :Theorem Value Final theUsing
2121
22
213
1
2121
223
21
2
030
DCDC
DC
DCDCss
KsKs
ss
s
K
KsKss
ssssE
s
L
Second-Order Type-1 PLL Tracking Response
95
• Phase Step Response
RCKKss
ss
RCKKsss
sssEs ss
2
21
2
3
00
:ResponseTransient
step phase a with zero be shoulderror Phase
0limlim :Theorem Value Final theUsing
L
Second-Order Type-2 PLL Tracking Response
N
RKKK
RCKKss
sss
ssEs
RCsR
sF VCOPD
nn
,2
,
1
2
2
22
2
96
RCKKss
ss 2
21 :ResponseTransient L
Second-Order Type-2 PLL Phase Step Response
KRCRCn
21
2
97
• Frequency Offset (Step) Response
RCKKss
ss
RCKKsss
sssEs ss
2
2
21
22
3
020
:ResponseTransient
PLL 2-Type a with zero togoeserror phase The
0limlim :Theorem Value Final theUsing
L
Second-Order Type-2 PLL Tracking Response
N
RKKK
RCKKss
sss
ssEs
RCsR
sF VCOPD
nn
,2
,
1
2
2
22
2
98
Second-Order Type-2 PLL Frequency Step Response
KRCRCn
21
2
RCKKss
ss 2
2
21 :ResponseTransient L
99
• Frequency Ramp Response
RCKKss
ss
RCKKsss
sssEs n
ss
2
2
31
223
3
030
:ResponseTransient
lag phase dynamic a with rampfrequency acan track PLL 2-order type-secondA
limlim :Theorem Value Final theUsing
L
Second-Order Type-2 PLL Tracking Response
N
RKKK
RCKKss
sss
ssEs
RCsR
sF VCOPD
nn
,2
,
1
2
2
22
2
100
Second-Order Type-2 PLL Frequency Ramp Response
KRCRCn
21
2
RCKKss
ss 2
2
31 :ResponseTransient L
Ideal Phase Detector
• An ideal phase detector has the same gain (slope) over a 2 range
• This allows the linear PLL model to be used for all phase relationships
101
Real Phase Detectors• Many phase detectors
are nonlinear and do not display the same gain for a given phase relationship
• This implies that the PLL cannot be described by the linear model for large input phase deviations
102
PLL Frequency Step Response:Linear vs Behavioral Model
103
ref(s)=Frequency Step Input: s2 = Mrad/sec
32s2
No Cycle Slips Observedwith Linear Model
Cycle Slips
• Due to non-linearities in loop components (primarily the PD), a real PLL’s response can vary significantly from the linear model
PLL Hold Range (Sinusoidal PD)• A PLL Hold Range is the input frequency range over which the PLL can
maintain static lock
104
rad/sec :Range Hold
todconstraine isfrequency lock the,1 exceedcannot sine Since
sin
iserror phase thedetector, phase sinusoidal aWith
:2-TypeOrder -Second
:1-TypeOrder -Second
:Order-First
isError Phase State-Steady theModelLinear w/
1
DCH
DC
DCe
DC
VCOPDDC
VCOPDDC
DCe
K
K
K
K
NKKK
NKKKK
K
• The hold range is finite for a type-1 PLL, and theoretically infinite for a type-2 PLL. However in practice it will be limited by another PLL block, such as the VCO tuning range.
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
105
orefref
o
ePD
cVCOo
t
K
tvK
KsF
and is phaseinput
thesuch that , fromdifferent frequency aat is signalinput theAssume
sin :OutputDetector Phase Sinusoidal
:Frequency ousInstantane VCO
1
PD sinusoidal a with PLLorder -first simple a Assuming
1
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
106
PDVCOee
out
t
oePDVCOorefoutrefe
out
t
oePDVCOoout
t
ocVCOoout
KKKtKdt
t
dKKt
dKKtdvKtt
wheresind
equation aldifferentinonlinear following theyields time w.r.t. thisatingDifferenti
0sin
iserror phase PLL The
0sin0
is phaseoutput PLL The
107
First-Order PLL Hold Range (Sinusoidal PD)
K
K
Kdt
t
e
ee
todconstraine isfrequency lock the,1 exceedcannot sine Since
sin
0sind
locked, is PLL theIf
rad/sec :Range Hold KH
108
First-Order PLL Phaselock Acquisition (Sinusoidal PD)
ee
KK sin
Kby equation aldifferenti PLLorder -first thegNormalizin
unstable are nulls slope-positive while
points,lock stable are nulls slope-Negative
0 wherenulls 2 are thereplot, plane-phase In the dtd e
• Every cycle (2 interval) contains a stable null, thus ecannot change by more than one cycle before locking
• There is no cycle slipping in the locking process• A cycle slip occurs when the phase error changes by more
than 2 without locking
Ke
Error,Frequency Normalized
e Error, Phase
109
First-Order PLL Phaselock Acquisition Time (Sinusoidal PD)
tlysignifican increasecan andion approximatlinear thisfrom
deviate willresponse thelarge, is 0 if However,
0
response step phase modellinear theissolution eapproximat the
,sinsuch that small, is 0 and zero is If
0sin
solveformally toneed we time,acquistionphaselock thefind order toIn
e
Ktoute
eee
out
t
oePDVCOe
et
dKKtt
• If the frequency offset exceeds the PLL hold range, the phase error will oscillate asymmetrically as the PLL undergoes cycle slips
110
First-Order PLL Lock Failure (Sinusoidal PD)First-Order PLL VCO Control Voltage
rad/sec :Range Hold KH
Second-Order Type-2 PLL PhaselockAcquisition (Sinusoidal PD)
111
0sin1sin0
is phaseoutput PLL The
sin1sin1
as expressed becan domain - timein the responsefilter The
11
PD sinusoidal a with PLL 2-order type-second a Assuming
0 010 1
2
011
2
011
2
11
2
1
2
out
t t
e
t
ePDVCOoout
t
ocVCOoout
t
ePDePD
t
eec
dddKKtdvKtt
dKKdvtvtv
ssssF
Second-Order Type-2 PLL PhaselockAcquisition (Sinusoidal PD)
112
eeePDVCOe
out
t t
e
t
ePDVCOorefoutrefe
KK
dddKKt
sin1cos
equation aldifferentinonlinear following theyields time w.r.t. twice thisatingDifferenti
0sin1sin
iserror phase PLL The
11
2
0 010 1
2
Second-Order Type-2 PLL PhaselockAcquisition (Sinusoidal PD)
113
0sincos2
following theyieldsequation aldifferentinonlinear theinto thisngSubstituti
4 ,
arefactor damping andfrequency natural thePLL, 2-TypeOrder -Second For this
2
1
22
1
2
eneene
VCOPDVCOPDn
KKKK
• No closed form solution exists, and numerical techniques are required to solve
Second-Order Type-2 PLL PhaselockAcquisition (Sinusoidal PD)
114
0sincos2 2
eneene
Acquisition with a phase error
time vs and
ee ee vs :Plot Plane Phase
% of cycle
rads
Second-Order PLL Phase Plane Plots (Sinusoidal PD)
115
0sincos2 2
eneene
• An unstable singularity is called a Saddle Point
• A trajectory that terminates on a saddle point is called a “Separatrix”
• If a trajectory lies between the 2 separatrices, it will lock without cycle slipping
• If a trajectory lies outside the 2 separatrices, it will cycle slippling one or more times before locking (if at all)
Second-Order PLL Pull-Out Range and Lock Time (Sinusoidal PD)
116
(Hz) 41
2
,11 Assuming
(Hz)
bandwidth noise PLL theis Here,
10% than lesserror phasefor
2.44
as edapproximat becan timeacquistion PLL therange,out -pull than theless is stepfrequency a If
1.4 and 0.5between for
18.1
11
2
1
2
0
2
3
2
nL
L
L
Lnfreqphaseacq
nPO
B
ssssF
dffHB
B
Bfttt
• The Pull-Out Range is the maximum frequency step that can occur before the loop locks without cycle slipping
Second-Order PLL Locking Outside of the Pull-Out Range (Sinusoidal PD)
117
• Multiple cycle slips are observed before the loop locks
Next Time• Phase Detector Circuits
118