ECO Timing Optimization Using Spare Cells2

7/29/2019 ECO Timing Optimization Using Spare Cells2

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ECO Timing Optimization

Using Spare Cells

Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang

ICCAD2007, Pages 530-535


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Outline Introduction

Problem Formulation

The Spare-Cell Selection Algorithm Experimental Results

Conclusions


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Problem Formulation


Conclusions


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Introduction Spare cells are often used to perform ECO

(Engineering Change Order) after the

placement stage to change/fix a design.

They are often evenly placed on the chip

layout; the type and number of spare cells

vary from different chip designs and are

usually determined by designers

empirically.


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Introduction

Using spare cells is an efficient way to do

netlist changes.

Save time and effort of re-placing the netlist

Save production cost of masks


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Problem Formulation


Conclusions


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Problem Formulation

A timing path is defined as(1) A path from a primary input to a primary output

(2) A path from a primary input to a flip-flop input

(3) A path from a flip-flop output to a primary output(4) A path between a flip-flop output and a flip-flop input

An ECO path is a timing path that violates

the timing constraint.


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Problem Formulation

A buffering operation is to insert a buffer-typespare cell gS(i) into a net nE(j) along an ECOpath.

A gate sizing operation is to exchange a sparecell gS(i) with a gate gE(j) along an ECO path byrewiring.


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Problem Formulation


Conclusions


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Timing Model and Properties

Synopsys Liberty library format Use lookup table to calculate gate delays.

The gate delay and the output transition time are functions

of the output loading and the input transition time.


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Loading dominance The effect of its output capacitance to the gate

delay is much larger than that of the input

transition time .(28x vs 1x) Shielding effect

Change of the netlist effects delay of neighbor

gates only.


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Algorithm Overview


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Buffer Insertion

We keep the solution if

d(gE(M1))+d(gS(j)) < d(gE(M1)) , M: size of GE


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Gate Sizing


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Spare-Cell Selection inside a

Bounding Polygon Let the width of the square bounding box ofgE(i)

centered at gE(i) be

Let the width of the square bounding box of g(j) (g(j) G(j)) centered at g(j) be

: the capacitance per unit wirelengthCEO(i) : the output pin capacitance of gate gE(i).

FO(gE(i)) : the set of fan-out gates of gE(i)G(j) : the fan-outs of the gate gE(i) to be sized


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Bounding Polygon


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Bounding Polygon


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Bounding Polygon Let the width of the square bounding box ofg(k)

(g(k) G(k)) centered at g(k) be

Let the width of the square bounding box ofg(j)(g(j) G(j)) centered at g(j) be

G(k) : the fan-ins of the gate gE(i) to be sized

G(j) : the fan-outs of the gate gE(i) to be sized


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Solution Control

For each set of solutions, we keep at most

ksolutions. (kis a user-defined parameter) Discard non-dominant solutions.

Classify these solutions by the number of usedbuffers.

Keep the best K solutions for each class.


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Problem Formulation


Conclusions


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Shielding Effect


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Shielding Effect


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Problem Formulation


Conclusions


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Conclusions

This paper present the firstwork for this problem

of ECO timing optimization using spare-cell

rewiring.

They didnt solve the competition for using a

spare cell among multiple paths.

They cant insert multiple buffers in a single net.


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Thanks


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Output loading consists of input pin capacitance

output pin capacitance

wire loading

c : is the capacitance per unit wirelength,

FO(g(i)) : the set of fan-out gates ofg(i)

CO(i) : output pin capacitance of gate g(i)

CI (j) : input pin capacitance of the fan-outs of the gate g(i)


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Gate Sizing and Buffer Insertion

Buffering on the net nE(i) changes the delay of the

driving gate and driven gates ofnE(i), while other gates

are little or not affected. Thus the impact of buffering on

the timing of the ECO path is the delay change ofgE(i),

gE(i+ 1), and the delay increase of the inserted buffer.

Sizing the gate gE(i) changes the delay of the fan-in/fan-

out gates ofgE(i), while other gates are little or not

affected. Thus the impact of sizing gE(i) on the timing ofthe ECO path is the delay change ofgE(i 1), gE(i+ 1),

and the sized gate.


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Gate Sizing

We keep the solution if

d(gE(M 2))+d(gS(j)) < d(gE(M 2))+d(gE(M 1)),and

d(gE(M 2)) < d(gE(M 2)),


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Bounding Polygon

Theorem 1: Given a net nE(i) with the

source gE(i) and the sinks in G(j) to be

buffered, inserting any buffer-type spare

cell, whose output transition time is notsmaller than gE(i) and with the same

output loading, outside the bounding

polygon (i) into the net increases the pathdelay.

Documents

ECO Timing Optimization Using Spare Cells2