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GATE Questions on Diodes

Diode - 1 includes Diode under open circuit, built in potential barrier, electric field,width of potential barrier etc.

1. In a uniformly doped abrupt PN junction, the doping level of the N-side is four times the

doping level of the P-side. The ratio of the depletion layer widths is[G90]

a. 0.25

b. 0.50

c. 1.0

d. 2.0

2. The built in potential (Diffusion Potential) in a PN junction [G93]

a. Is equal to the difference in the Fermi level of the two sides, expressed in volts.

b. Increases with the increase in the doping levels of the two sides

c. Increases with the increase in temperatured. Is equal to the average of the Fermi levels of the two sides

3. In a P+N junction diode under reverse bias, the magnitude of electric field is maximum

at [G07]

a. The edge of the depletion region on the p sideb. The edge of the depletion region on the n-side

c. The P+N junction

d. The centre of the depletion region on the n-side

4. Consider a silicon P-N junction at room temperature having the following parameters : [G09]

Doping on the n-side = 1 x 1017 cm-3

Depletion width on the n-side = 0.1 umDepletion width on the p-side = 1.0 um

Intrinsic carrier concentration = 1.4 x 1010 cm-3Thermal voltage = 26 mV

Permittivity of free space = 8.85 x 10-14 F.cm-1Dielectric constant of silicon = 12

The built in potential of the junction is

(A) 0.70 V (B) 0.76 V (C) 0.82 V (D) cannot be estimated from the given data

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The peak electric field in the device is

(A) 0.15 MV . cm-1, directed from p-region to n-region

(B) 0.15 MV . cm-1, directed from n-region to p-region

(C) 1.80 MV . cm-1, directed from p-region to n-region(D) 1.80 MV . cm-1, directed from n-region to p-region

5. In a Forward Biased PN junction diode, the sequence of events that best

describes the mechanism of current flow is [G13]

a. Injection and subsequent diffusion and recombination of minority carriersb. Injection and subsequent drift and generation of minority carriers

c. Extraction and subsequent diffusion and generation of minority carriers

d.

Extraction and subsequent drift and recombination of minority carriers

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Diode - 2 includes forward bias, reverse bias, V-I characteristics, static

and dynamic resistance, effect of temperature on Io and diode

voltage.

1. (a) Two ideal and identical (ideality factor = 1) junction diodes are connected in series

as shown in figure. [GATE'90]

Show that

exp (eV1/KT) + exp (-eV2/KT) = 2

where V1and V2are the voltage drops across the diodes D1 and D2.

(b)Assuming that the current through the reverse biased diode is saturated at Io,

calculate the Voltage drop across the forward biased diode. Assume KT = 26meV.

2. Consider the circuit shown in figure (a). If the diode used here has the V-I characteristicas in figure (b), then the output waveform VOis [G93]

http://2.bp.blogspot.com/-KTlDrqqAgjc/Uj1RtzlA0YI/AAAAAAAAAw4/TeQ4orrtEtE/s1600/Previous+GATE+Questions.jpg

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3. Two identical silicon junction diodes, D1 and D2 are connected back to back as shown

figure. The reverse saturation current , ISof each diode is 10-8

amps and the breakdown

voltage is 50 volts. Evaluate the voltage VD1and VD2across the diode D1 and D2 by

assuming KT/q to be 25mV.[GATE95]

4. The static characteristic of an adequately forward biased PN junction is a straight line, if

the plot is of [GATE98]

a. Log I vs. log V

b. Log I vs. V

c. I vs. log Vd. I vs. V

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8.In abrupt PN junction, the doping concentrations on the p-side and n-side are NA = 9 x 1016

/cm3and ND = 1 x 10

16/cm

3respectively. The PN junction is reverse biased and the total

depletion width is 3 m. The depletion width on the p-side is[GATE04]

a. 2.7 m

b. 0.3 m

c. 2.25 md. 0.75 m

9. A silicon PN junction at a temperature of 20oC has a reverse saturation current of 10

pico Amp. The reverse saturation current at 40oC for the same bias is approximately

[GATE05]

a. 30 pico Amp

b. 40 pico Ampc. 50 pico Amp

d. 60 pico Amp

10. A P+N junction has a built in potential of 0.8 volts. The depletion layer width at a reverse

bias of 1.2 volts is 2 m. For a reverse bias of 7.2 volts , the depletion layer width will be : [GATE07]

a. 4 m

b. 4.9 m

c. 8 m

d. 12 m

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11. A silicon PN junction is forward biased with a constant current at room temperature.

When the temperature is increased by 10oC, the forward bias voltage across the PN

junction [GATE11]

a. Increases by 60 mV

b. decreases by 60 mVc. Increases by 25 mV

d. decreases by 25 mV

12. The forward dynamic resistance of a junction diode varies __________________ as the forward

current. [GATE'94]

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This set of questions include Ideal diode model, Simplified diode model,

and piece wise linear diode model.

1. In the circuit shown, the current IDflowing through the ideal diode equal to [GATE97]

2. For the circuit shown in figure, the voltage Vois [GATE00]

a. 2 volts

b.

1 voltsc. -1 volts

d. None of the above

3. In the circuit below, the diode is ideal. The voltage V is given by[GATE09]

(A) Min (Vi,1) (B) max (Vi,1) (C) min(-Vi,1) (D) max (-

Vi,1)

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4. The i -vcharacteristics of the diode in the circuit given below are [GATE'12]

The current in the circuit isA. 10mA B. 9.3 mA C. 6.67 mA D. 6.2 mA

5. The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across thediode D1 is[GATE12]

a. Cos(wt) - 1b. Sin(wt)

c. 1cos(wt)

d. 1sin(wt)

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Previous GATE Questions on Diode Capacitances (Diffusion and Transition

Capacitance)

1. In a junction diode [GATE'90]

a. The depletion capacitance increases with increase in the reverse bias

b. The depletion capacitance increases with decrease in the reverse biasc. The diffusion capacitance increases with increase in the forward bias

d. The diffusion capacitance is much higher than the depletion capacitance, when its is forward

biased

2. The small signal capacitance of an abrupt P

+

N junction is 1 nF/cm

2

at zero bias. If thebuilt in voltage is 1 volt, the capacitance at a reverse bias voltage of 99 volts is equal to .. [GATE91]

3. The depletion capacitance, CJ, of an abrupt PN junction with constant doping on eitherside varies with reverse bias, VRas [GATE'95]

a. CJVR

b. CJ VR-1

c. CJ VR

-1/2

d. CJ VR-1/3

4. Consider an abrupt PN junction. Let Vbibe the built in potential of this junction and VR

be the applied reverse bias. If the junction capacitance (Cj) is 1 pF for Vbi+ VR= 1 volt,

then for Vbi+ VR= 4 volts, Cjwill be[GATE04]

a. 4 pF

b. 2 pF

c.

0.25 pFd. 0.5 pF

5. A silicon PN junction diode under reverse bias has depletion region of width 10m. the

relative permittivity of silicon ris 11.7 and the permittivity of free space o= 8.85x10-12

F/m. the depletion capacitance of the diode per square meter is[GATE05]

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a. 100 F

b. 10 F

c. 1 Fd. 20 F

6. Which of the following is NOT associated with a P-N junction ?[GATE'08]

(A) Junction capacitance (B) Charge Storage Capacitance(C) Depletion Capacitance (D) Channel Length Modulation