EE 330 Lecture 17class.ece.iastate.edu/ee330/lectures/EE 330 Lect 17 Spring 2013.pdf · I- Cμ VV V VVVVV L2 W-Cμ VV VVVVV 2L I =I =0 ≥ = −−≤ > − − ≤ ≤− Source

EE 330 Lecture 17

CMOS Process Flow

Characteristics of Finer Feature Size Processes

Bipolar Process

Operation Regions by Applications

0

50

100

150

200

250

300

0 1 2 3 4 5

Id

Vds

Saturation Region

Triode Region

Cutoff Region

Analog Circuits

Digital Circuits

DI

DSV

Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception)

Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs

Review from Last Time

Model Status

Simple dc Model

Small Signal

Frequency Dependent Small

Signal

Better Analytical dc Model

Sophisticated Model for Computer Simulations

Simpler dc Model

Square-Law Model

Square-Law Model (with extensions for λ,γ effects)

Short-Channel α-law Model

BSIM Model

Switch-Level Models • Ideal switches • RSW and CGS


In the next few slides, the models we have developed will be listed and reviewed

• Square-law Model • Switch-level Models • Extended Square-law model • Short-channel model • BSIM Model • BSIM Binning Model • Corner Models


Square-Law Model ID

VDS

( )

GS T

DSD OX GS T DS GS DS GS T

2

OX GS T GS T DS GS T

0 V VVWI μC V V V V V V V V

L 2WμC V V V V V V V2L

T

≤ = − − ≥ < −

− ≥ ≥ −

VGS1

VGS3

VGS2

VGS4


Model Parameters : {μ,COX,VT0} Design Parameters : {W,L} but only one degree of freedom W/L

VGS

RSW

CGS

S

DG

Switch-Level Models

Switch-level model including gate capacitance and drain resistance

Switch closed for VGS=“1”

CGS and RSW dependent upon device sizes and process

For minimum-sized devices in a 0.5u process

1.5fFCGS ≅

−−

≅channelp6KΩchanneln2KΩ

Rsw

Considerable emphasis will be placed upon device sizing to manage CGS and RSW

Drain

Gate

Source


Model Parameters : {CGS,RSW}

Extended Square-Law Model

( ) ( )1

GS T

DSD OX GS T DS GS DS GS T

2

OX GS T DS GS T DS GS T

0 V VVWI μC V V V V V V V V

L 2WμC V V V V V V V V2L

T

λ

≤ = − − ≥ < −

− • + ≥ ≥ −

( )φφγ −−+= BST0T VVV

Model Parameters : {μ,COX,VT0,φ,γ,λ}

Design Parameters : {W,L} but only one degree of freedom W/L

0I0I

B

G

==


Short-Channel Model

( ) ( )

( ) ( )

1

1

GS T

2 2 2D OX GS T DS GS DS GS

1

22 OX GS T GS T DS GS

0 V VWI μC V V V V V V VL

WμC V V V V V VL

T T

T

V

V

α α

αα

θ θθ

θ θ

≤= − ≥ < −

− ≥ ≥ −

α is the velocity saturation index, 2 ≥ α ≥ 1

Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well


BSIM model

Note this model has 95 model parameters !


BSIM Binning Model - multiple BSIM models !

With 32 bins, this model has 3040 model parameters !

- Bin on device sizes


BSIM Corner Models - five different BSIM models !

With 4 corners, this model has 475 model parameters !

- Often 4 corners in addition to nominal TT, FF, FS, SF, and SS

TT: typical-typical FF: fast n, fast p FS: fast n, slow p SF: slow n, fast p SS: slow n, slow p


W

L

AccuracyComplexity

Switch-Level Models

Number of Model Parameters

0 to 2

Square-Law Models

Number of Model Parameters 3 to 6

BSIM Models


Approx 100

BSIM Binning Models


Approx 3000(for 30 bins)

Ana

lytic

alN

umer

ical

(for

sim

ulat

ion

only

)

Hierarchical Model Comparisons Review from Last Time

TTTypical-Typical

SS (Slow n, Slow p)

SF (Slow n, Fast p)

FS (Fast n, Slow p)

FF (Fast n, Fast p)

{Basic Model

Corner Model

Corner Models

Applicable at any level in model hierarchy (same model, different parameters)

Often 4 corners (FF, FS, SF, SS) used but sometimes many more

Designers must provide enough robustness so good yield at all corners


n-channel …. p-channel modeling

D

BG

S

VDS

VGSVBS

ID

IG IB

( )

GS Tp

DSD p OX GS Tp DS GS Tp DS GS Tp

2

p OX GS Tp GS Tp DS GS Tp

G B

0 V V

VWI -μ C V V V V V V V VL 2W-μ C V V V V V V V2L

I =I =0

≥

= − − ≤ > −

− ≤ ≤ −

Gate DrainSource

Bulk

p-channel MOSFET

(for enhancement devices)

( )

GS Tp


2


G B

0 V V

VWI μ C V V V V V V V VL 2Wμ C V V V V V V V2L

I =I =0

≤

= − − ≥ < −

− ≥ ≥ −

Alternate equivalent representation

These look like those for the n-channel device but with ||


D D

S S

G G

D

BG

S

D

BG

S

VDS

VGSVBS

IDIG IB

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5

VDS

ID

VGS1

VGS2

VGS4

VGS3

GS4 GS3 GS2 GS1V V V V > 0> > >

VDS

( )

GS Tn

DSD n OX GS Tn DS GS DS GS Tn

2

n OX GS Tn GS Tn DS GS Tn

G B

0 V VVWI μ C V V V V V V V V

L 2Wμ C V V V V V V V2L

I =I =0

Tn

≤ = − − ≥ < −

− ≥ ≥ −

D D

S S

G G

D

BG

S

D

BG

S

VDS

VGSVBS

ID

IG IB

( )

GS Tp


2


G B

0 V V

VWI -μ C V V V V V V V VL 2W-μ C V V V V V V V2L

I =I =0

≥

= − − ≤ > −

− ≤ ≤ −

n-channel …. p-channel modeling

Models essentially the same with different signs and model parameters


Modeling of the MOSFET Drain

Gate Bulk

ID

ID IBVDS

VBSVGS

Goal: Obtain a mathematical relationship between the port variables of a device.

Simple dc Model

Small Signal

Frequency Dependent Small

Signal

Better Analytical dc Model

Sophisticated Model for Computer Simulations

Simpler dc Model

( )( )( )

===

BSDSGS3B

BSDSGS2G

BSDSGS1D

V,,VVfIV,,VVfIV,,VVfI


Small-Signal Model

Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point

Operating point is often termed Q-point


Small-Signal Model y

x

Q-point

XQ

YQ

Analytical expressions for small signal model will be developed later


Technology Files • Design Rules

• Process Flow (Fabrication Technology)

• Model Parameters

n-well

n-well

n-

p-

Bulk CMOS Process Description

• n-well process • Single Metal Only Depicted • Double Poly

Components Shown

• n-channel MOSFET • p-channel MOSFET • Poly Resistor • Doubly Poly Capacitor

A A’

B’ B

C

C’

D

D’

Consider Basic Components Only

Well Contacts and Guard Rings Will be Discussed Later

A A’

B’ B

A A’

B’ B

A A’

B’ B

n-channel MOSFET

S

D

G

S

D

B G

Metal details hidden to reduce clutter

A A’

B’ B

S

D

B G

W L

A A’

B’ B

n-channel MOSFET

Capacitor

p-channel MOSFET

Resistor

n-well

n-well

n-

p-

A A’

B’ B

N-well Mask

A A’

B’ B

N-well Mask

Detailed Description of First Photolithographic Steps Only

• Top View • Cross-Section View

~

Blank Wafer

p-doped Substrate

Expose Develop

Photoresist n-well Mask Implant

~

A A’

B’ B

A-A’ Section

B-B’ Section

Photoresist N-well Mask Exposure Develop

A-A’ Section

B-B’ Section

Implant

N-well Mask

A-A’ Section

B-B’ Section n-well

n-well

n-well

n-

p-

A A’

B’ B

Active Mask

A A’

B’ B

Active Mask

Active Mask

A-A’ Section

B-B’ Section

Field Oxide Field Oxide Field Oxide

Field Oxide

n-well

n-well

n-

p-

A A’

B’ B

Poly1 Mask

A A’

B’ B

Poly1 Mask

A A’

B’ B

n-channel MOSFET

Capacitor

P-channel MOSFET

Resistor

Poly plays a key role in all four types of devices !

Poly 1 Mask

A-A’ Section

B-B’ Section

Gate Oxide Gate Oxide

n-well

n-well

n-

p-

A A’

B’ B

Poly 2 Mask

A A’

B’ B

Poly 2 Mask

Poly 2 Mask

A-A’ Section

B-B’ Section

n-well

n-well

n-

p-

A A’

B’ B

P-Select

A A’

B’ B

P-Select

P-Select Mask – p-diffusion

A-A’ Section

B-B’ Section

p-diffusion

Note the gate is self aligned !!

P-Select Mask – n-diffusion

A-A’ Section

B-B’ Section

n-diffusion

n-well

n-well

n-

p-

A A’

B’ B

Contact Mask

A A’

B’ B

Contact Mask

Contact Mask

A-A’ Section

B-B’ Section

n-well

n-well

n-

p-

A A’

B’ B

Metal 1 Mask

A A’

B’ B

Metal 1 Mask

Metal Mask

A-A’ Section

B-B’ Section

A A’

B’ B

A A’

B’ B

n-channel MOSFET

Capacitor

P-channel MOSFET

Resistor

How does the inverter delay compare between a 0.5u process and a 0.13u process?

VIN VOUT

VDD

VSS

VIN VOUT

How does the inverter delay compare between a 0.5u process and a 0.13u process?

VINVOUT

Assume n-channel and p-channel devices are minimum sized

End of Lecture 15

Documents

EE 330 Lecture 17class.ece.iastate.edu/ee330/lectures/EE 330 Lect 17 Spring 2013.pdf · I- Cμ VV V VVVVV L2 W-Cμ VV VVVVV 2L I =I =0 ≥ = −−≤ > − − ≤ ≤− Source