EE 5900 Advanced EE 5900 Advanced Algorithms for Robust Algorithms for Robust VLSI CAD, Spring 2009VLSI CAD, Spring 2009

CMOS Combinational GateCMOS Combinational Gate

Apr 19, 2023

PJF - 2Combinational Logic

CMOS Combinational CMOS Combinational CircuitsCircuits

Implementation of logic gates and other structures Implementation of logic gates and other structures using CMOS technology.using CMOS technology.

Basic element: Basic element: transistortransistor 2 types of transistors:2 types of transistors:

n-channel (nMOS) n-channel (nMOS) and and p-channel (pMOS)p-channel (pMOS) Type depends on the semiconductor materials used to Type depends on the semiconductor materials used to

implement the transistor.implement the transistor. We want to model transistor behavior at the We want to model transistor behavior at the logic levellogic level in in

order to study the behavior of CMOS circuits order to study the behavior of CMOS circuits view pMOS view pMOS and nMOS transistors as swithes.and nMOS transistors as swithes.

Apr 19, 2023

PJF - 3Combinational Logic

CMOS transistors as CMOS transistors as SwitchesSwitches

3 terminals in CMOS transistors: G: Gate D: Drain S: Source

nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF)

pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)

Apr 19, 2023

PJF - 4Combinational Logic

Networks of SwitchesNetworks of Switches Use switches to create networks that Use switches to create networks that

represent CMOS logic circuits.represent CMOS logic circuits. To implement a function F, create a To implement a function F, create a

network s.t. there is a path through the network s.t. there is a path through the network whenever F=1 and no path when network whenever F=1 and no path when F=0.F=0.

Two basic structures:Two basic structures: Transistors in SeriesTransistors in Series Transistors in ParallelTransistors in Parallel

Apr 19, 2023

PJF - 5Combinational Logic

Transistors in Transistors in Series/ParallelSeries/Parallel

nMOS in ParallelnMOS in Series

X

Y

a

b

X:X

Y:Y

a

b

pMOS in Series

X

Y

a

b

X:X’

Y:Y’

a

b

Path between points a and b exists if both X and Y are 1 X•Y

Path between points a and b exists if both X and Y are 0 X’•Y’

Path between points a and b exists if either X or Y are 1 X+Y

X Y

b

a

X:X Y:Y

b

a

pMOS in Parallel

X Y

b

a

X:X Y:Y

b

a Path between points a and b exists if either X or Y are 0 X’+Y’

Apr 19, 2023

PJF - 6Combinational Logic

Networks of Switches Networks of Switches (cont.)(cont.)

In general:In general:1.1. nMOS in series is used to implement AND logicnMOS in series is used to implement AND logic

2.2. pMOS in series is used to implement NOR logicpMOS in series is used to implement NOR logic

3.3. nMOS in parallel is used to implement OR logicnMOS in parallel is used to implement OR logic

4.4. pMOS in parallel is used to implement NAND logicpMOS in parallel is used to implement NAND logic Observe that:Observe that:

1 is the complement of 3, and vice-versa1 is the complement of 3, and vice-versa 2 is the complement of 4, and vice-versa2 is the complement of 4, and vice-versa

Apr 19, 2023

PJF - 7Combinational Logic

CMOS InverterCMOS Inverter

X F = X’X’

Logic symbol

X F = X’X’

+V

GRD

Transistor-level schematic

Operation: X=1 nMOS switch conducts (pMOS is open) and draws from GRD F=0 X=0 pMOS switch conducts (nMOST is open) and draws from +V F=1

Apr 19, 2023

PJF - 8Combinational Logic

Fully Complementary CMOS Fully Complementary CMOS NetworksNetworks

Basic GatesBasic Gates

Apr 19, 2023

PJF - 9Combinational Logic

Fully Complementary CMOSFully Complementary CMOSComplex GatesComplex Gates

Given a function F:Given a function F:

1.1. First take the complement of F to form F’First take the complement of F to form F’

2.2. Implement F’ as an nMOS net and connect it to Implement F’ as an nMOS net and connect it to GRD (pull-down net) and F.GRD (pull-down net) and F.

3.3. Find dual of F’, implement it as a pMOS net and Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F.connect it to +V (pull-up net) and F.

4.4. Connect switch inputs.Connect switch inputs.

Apr 19, 2023

PJF - 10Combinational Logic

Fully Complementary CMOS Fully Complementary CMOS NetworksNetworks

Complex Gates - ExampleComplex Gates - Example

F’ = A’B’+A’C=A’(B’+C)

F = (A+B)(A+C’)