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9/26/2005
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 11/9/2008
EE108A
Lecture 1:The Digital AbstractionCombinational LogicBoolean AlgebraVerilog Introduction
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 21/9/2008
Administrivia
• Course Notes Chapters 1-12 (on web)– Read 1, 3, 6.1-6.4 for today– Read 6.5-6.11, 7 for Monday
• Handouts– Lecture slides– Homework 1– Lab 0– Course Policy Sheet– Lab/Section Questionnaire
• Web page http://ee108a.stanford.edu, EEClass• E102E - writing in the major• Photos
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 31/9/2008
Today
• The Digital Abstraction– Representation– Noise
• Combinational Logic– Output function of current input– Acyclic composition– Representations - description, truth table, equation– Boolean algebra
• Verilog
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 41/9/2008
Moore’s Law
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 51/9/2008
Moore’s Law, Broadly Defined
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 61/9/2008
The Digital Abstraction
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 71/9/2008
Voltages Ranges of Binary Signals
0 1?
VoltageDamage Damage
Vmin V0 VIL VIH V1 Vmax
-0.3V 0.0V 0.7V 1.7V 2.5V 2.8V
2.5V LVCMOS Logic
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 81/9/2008
Representing Information with Digital Signals
Binary Information Light On/Off: 1/0
Element of a set
Yellow011Blue010Red001
White000
Black111Green110
Orange101Purple100
Continuous Quantities
74011720107000168000
82111801107810176100
740000111720000011700000001680000000
821111111800111111780011111760001111
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 91/9/2008
How would you represent
• A Date ?– Days since Jan 1 0000 (20 bits)– Month, day, year (4 + 5 + 12 bits)– Month, day, year, day of week (4 + 5 + 12 + 3 bits)
• This representation is _________
• A playing card ?– Number in deck (6 bits)– Suit, Number (2 + 4 bits)– Decoded suit, decoded number (4 + 13 bits)
• A 5-card hand ?
• Pick a representation based on operations required
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 101/9/2008
Example
• Pick representation of colors to support the operation of subtractivecolor mixing (e.g., red + blue = purple)– No colors: white– Primary colors: red, blue, yellow– Derived colors: orange, purple, green, black
• How about an additive color model?– No colors: black– Primary: red, green, blue– Derived: yellow, orange, purple, green, white
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 111/9/2008
Effect of Noise on Analog & Digital Signals
VInput +
ε
Noise
V+ε f f(V+ε) Output
Noise adds to input Error at output
Analog Signals
Digital Signals
V1Input +
ε
Noise
V1+ε ff(V1) Output
Noise added to input < noise margin Correct value at output
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 121/9/2008
Input & Output Voltage Ranges
Input
Output
0 1?
0 1Tran
VoltageVOL
Voltage
Damage Damage
VIH
VIL
VNML
VNMH
VOH
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 131/9/2008
Restoration of Digital Signals
Noise
+
ε1
Noise Accumulation
Va +ε1
Noise
+
ε2
Va+ε1+ε
2Va
Noise
+
ε3
Noise
+
ε1
Va+ε1
Noise
+
ε2
Va+ε2Va Va
Noise
+
ε3
Va +ε3Va Va
Signal Restoration
Va +ε1+ε
2+ε
3
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 141/9/2008
DC Transfer Curve for a Logic Module
0 1?
V0
V1
Vmin
VIL
VIH
Vmax
01
Tra
n
Ou
tpu
t V
olta
ge
V OL
V OH
V 0V 1
Input Voltage
1
?
0
Vmin
Vmax
VIL
VIH
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 151/9/2008
Combinational Logic
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 161/9/2008
Combinational Logic Circuit
• Output is a function of current input• Example – digital thermostat
Compare
Temp
Sensor 3
CurrentTemp
A
3
PresetTemp
B
A>BFanOn
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 171/9/2008
Sequential logic circuit
• Includes state (memory, storage)• Makes output a function of history as well as current inputs• Synchronous sequential logic uses a clock• Example, calendar circuit
Regist er
4
TodayMonth
5
TodayDoM
3
TodayDoW
ClockCompute
Tomorrow
TomorrowMonth
4
TomorrowDoM
5
TomorrowDoW
3
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 181/9/2008
CL
i1
in
o1
om
CL
i
n
o
m
o = f(i)
Combinational logic is memoryless
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 191/9/2008
Can compose digital circuits
Thermostat
Calendar
=
TodayDoW
Sunday
ItsSunday
TempHigh
ItsNotSundayFanOn
NOT AND
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 201/9/2008
Closure
• Combinational logic circuits are closed under acyclic composition.
CL1CL2
CL12
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 211/9/2008
CL
CL
a
b
c
o
YES
CL
CL
a
b
NO
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 221/9/2008
CombinationalNOT
Combinatorial
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 231/9/2008
Combinational not Combinatorial
Combinational Combinatorial
mathematics of counting
combinational logic circuit
combines inputs to generate
an output
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 241/9/2008
Several ways to describe a combinational logicfunction
Example – Majority Circuit1. English Language Description
• Outputs 1 if more inputs are 1 than are 02. Logic equation
• q = (a ∧ b) ∨ (a ∧ c) ∨ (b ∧ c)3. Truth table
11111110110101001011001000010000qabc
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 251/9/2008
Boolean Algebra
• Boolean Algebra:– algebra over 2 elements: {0,1}– 3 operators: AND (∧), OR (∨), NOT (¬)
• AND Operation:– a ∧ b = 1 iff a=1 and b=1
• OR Operation:– a ∨ b = 1 if a=1 or b=1
• NOT Operation:– ¬a = 1 iff a=0
1111100110100000
a|ba&bba
10~aa
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 261/9/2008
Note on Notation for Boolean Algebra
• For AND logic function:
– use ∧ or &– don’t use x or .
• For OR logic function:
– use ∨ or |– don’t use +
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 271/9/2008
Axioms of Boolean Algebra
• Axiom: a mathematical statement we assert to be true.• Identity:
– 0 ∧ x = 0– 1 ∨ x = 1
• Idempotence:– 1 ∧ x = x– 0 ∨ x = x
• Negation:– ¬0 = 1– ¬1 = 0
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 281/9/2008
Useful Boolean Properties(all can be derived from the axioms)
¬(x ∨ y) = ¬x ∧ ¬y¬(x ∧ y) = ¬x ∨ ¬yDeMorgan’s
(x ∨ y) ∧ (x ∨ ¬y) = x(x ∧ y) ∨ (x ∧ ¬y) = xCombining
x ∨ (x ∧ y) = xx ∧ (x ∨ y) = xAbsorption
x ∨ x = xx ∧ x = xIdempotence
x ∨ (y ∧ z) = (x ∨ y) ∧ (x ∨ z)x ∧ (y ∨ z) = (x ∧ y) ∨ (x ∧ z)Distributive
x ∨ (y ∨ z) = (x ∨ y) ∨ zx ∧ (y ∧ z) = (x ∧ y) ∧ zAssociative
x ∨ y = y ∨ xx ∧ y = y ∧ xCommunicative
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 291/9/2008
DeMorgan’s Law
• ¬(x ∧ y) = ¬x ∨ ¬y ¬(x ∨ y) = ¬x ∧ ¬y
• Proof by perfect induction
0011
1101
1110
1100
¬x ∨ ¬y¬(x ∧ y)yx
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 301/9/2008
DeMorgan Graphically
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 311/9/2008
Applying Boolean Properties
f(a,b,c) = (a ∧ c) ∨ (a ∧ b ∧ c) ∨ (¬a ∧ b ∧ c) ∨ (a ∧ b ∧ ¬c)
f(a,b,c) = (a ∧ c) ∨ (a ∧ b ∧ c) ∨ (¬a ∧ b ∧ c) ∨ (a ∧ b ∧ c) ∨ (a ∧ b ∧ ¬c) ∨ (a ∧ b ∧ c)
f(a,b,c) = (a ∧ c) ∨ (¬a ∧ b ∧ c) ∨ (a ∧ b ∧ c) ∨ (a ∧ b ∧ ¬c) ∨ (a ∧ b ∧ c)
f(a,b,c) = (a ∧ c) ∨ (b ∧ c) ∨ (a ∧ b)
Apply absorption property
Apply combining property
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 321/9/2008
Verilog
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 331/9/2008
Verilog
• A hardware description language (HDL)• Used as an input to:
– Synthesis – implement hardware with gates, cells, or FPGAs– Simulation – see what your hardware will do before you build it
• Basic unit is a module• Modules have
– Module declaration– Input and output declarations– Internal signal declarations– Logic definition
• Assign statements• Case statements• Module instantiations
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 341/9/2008
Example, Verilog for Thermostat
module Thermostat(presetTemp, currentTemp, fanOn) ; // temperature inputs, 3 bits each input [2:0] presetTemp, currentTemp ;
// one bit, true when current > preset output fanOn ;
wire fanOn ; assign fanOn = (currentTemp > presetTemp) ;endmodule
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 351/9/2008
module Thermostat(presetTemp, currentTemp, fanOn) ; // temperature inputs, 3 bits each input [2:0] presetTemp, currentTemp ;
// one bit, true when current > preset output fanOn ;
wire fanOn ; assign fanOn = (currentTemp > presetTemp) ;endmodule
Example, Verilog for ThermostatModule declaration I/O list
Declare I/Os
A wire is a signal set with an assignstatement or connected to a module
3-bit wide signals
An assign statement defines a signalwith an equation
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 361/9/2008
Example, Days in Month Function
module DaysInMonth(month, days) ; input [3:0] month ; // month of the year 1 = Jan, 12 = Dec output [4:0] days ; // number of days in month
reg [4:0] days ;
always @(month) begin // evaluate whenever month changes case(month) 2: days = 5’d28 ; // February has 28 4,6,9,11: days = 5’d30 ; // 30 days have September ... default: days = 5’d31 ; // all the rest have 31... endcase endendmodule
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 371/9/2008
Example, Days in Month Function
module DaysInMonth(month, days) ; input [3:0] month ; // month of the year 1 = Jan, 12 = Dec output [4:0] days ; // number of days in month
reg [4:0] days ;
always @(month) begin // evaluate whenever month changes case(month) 2: days = 5’d28 ; // February has 28 4,6,9,11: days = 5’d30 ; // 30 days have September ... default: days = 5’d31 ; // all the rest have 31... endcase endendmodule
Reg defines a signal set in analways block. It does NOTdefine a register.
Always block evaluates each timeactivity list changes. In this caseeach time month changes
Case statement selects statementdepending on value of argument.Like a truth table.
Can have multiplevalues per statement
Default covers values notlisted. Always have one!
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 381/9/2008
Verilog design style – for synthesizable modules
1. Combinational modules use only1. Assign statements2. Case or Casex statements (with default)3. If statements – only if all signals have a default assignment4. Instantiations of other combinational modules
2. Sequential modules use only1. Combinational logic2. Explicitly declared registers (flip-flops)
3. Do not use1. Loops2. Always blocks except with case or casex and If
4. Do use1. Signal concatenation, e.g., {a, b} = {c, d}2. Signal subranges, e.g., a[7:1] = b[6:0] ;
5. Organize logic into small modules1. Leaf modules not more than 40 lines2. If it could be made two modules, it should be
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EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 391/9/2008
Verilog design style – for synthesizable modules(page 2)
6. Use lots of comments1. Comments themselves2. Meaningful signal names – tempHigh, not th3. Meaningful module names – DaysInMonth, not Mod3
7. Activation lists for case statements include ALL inputs8. Constants
1. All constants are `defined if used more than once2. Width of all constants is specified 5’d31, not 31
9. Signals1. Buses (multi-bit signals) are numbered high to low
• e.g., wire [31:0] bus2. All signals should be high-true (except primary inputs and outputs)
10. Visualize the logic your Verilog will generate.• If you can’t visualize it, the result will not be pretty
Make your code easy to read, understand, and reason about.
EE 108A Lecture 1 (c) 2008, W. J. Dally and P. Levis 401/9/2008
Summary
• The world is digital– Systems are digital at their core, only analog on the edges
• Representing information– Binary signals, sets, continuous values
• Digital signals reject noise– Voltage range divided into discrete states– Noise margins
• Combinational logic– Output depends only on input (no state)
• Boolean algebra– Rules to manipulate logic equations
• Verilog– Describe hardware for simulation and synthesis