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7.1
Unit 7
Minterm and Canonical Sums
2- and 3-Variable Boolean Algebra Theorems
DeMorgan's Theorem
Simplification using Boolean Algebra
7.2
CHECKERS / DECODERS
7.3
Gates
• Gates can have more than 2 inputs but the functions stay the same– AND = output = 1 if ALL inputs are 1
• Outputs 1 for only 1 input combination
– OR = output = 1 if ANY input is 1 • Outputs 0 for only 1 input combination
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
3-input AND 3-input OR
Fx
y
z
Fx
y
z
7.4
Checkers / Decoders
• An AND gate only outputs ‘1’ for 1 combination– That combination can be changed by adding inverters to the inputs
– We can think of the AND gate as “checking” or “decoding” a specific combination and outputting a ‘1’ when it matches.
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Fx
y
z
X Y Z F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Fx
y
z
AND gate decoding
(checking for)
combination 101
AND gate decoding
(checking for)
combination 000
7.5
Checkers / Decoders
• Place inverters at the input of the AND gates such that– F produces ‘1’ only for input combination {x,y,z} = {010}
– G produces ‘1’ only for input combination {x,y,z} = {110}
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Fx
y
z
X Y Z G
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Gx
y
z
AND gate decoding
(checking for)
combination 010
AND gate decoding
(checking for)
combination 110
7.6
Checkers / Decoders
• An OR gate only outputs ‘0’ for 1 combination– That combination can be changed by adding inverters to the inputs
– We can think of the OR gate as “checking” or “decoding” a specific combination and outputting a ‘0’ when it matches.
OR gate decoding
(checking for)
combination 010
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Fx
y
z
OR gate decoding
(checking for)
combination 110
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
Fx
y
z
7.7
Decoder Exercise• Compilers translate software to instructions
that tell the processor to ADD, LOAD from Memory, Store to Memory, etc.
• These instructions are binary codes
• The processor must decode the instruction
• Create an AND gate decoder for each instruction type in the table that will produce '1' when that instruction is about to be executed
Instruction Type 6-bit OPCODEOP[5:0]
ADD 001000
LOAD 100011
STORE 101011
BRANCH 000100
ADD LOAD STORE
7.8
Circuit Design and Analysis
• There are two basic tasks as a digital design engineer…– Circuit Design/Synthesis: Take a set of requirements or functional
descriptions and arrive at a logic circuit
– Circuit Analysis: Given a logic circuit, find or verify the logic function it implements
Problem
specification and
requirements
Truth Tables
Circuits and
Equationsx
yz
zyx
zyx
F
A
B
C
Circuit Analysis
Circuit Design
Canonical Sums/Products
Boolean Algebra
Karnaugh Maps
CAD tools
7.9
Outcomes
• The goal of this unit is to teach you how you can construct a digital circuit to implement ANY combinational logic function (usually expressed as a truth table)
– Example: Given a truth table, build a circuit from ANDs and ORs that will implement the function specified by the truth table
7.10
SYNTHESIZING LOGIC FUNCTIONS
7.11
The Problem
• Given a logic function, how do we arrive at a circuit to implement this combinational function?
• Rather than trying to solve the problem all at once we will do it in two steps:– Use gates to convert raw inputs (e.g. x,y,z) to intermediate signals;
– Convert the intermediate signals to produce the output (e.g. P)
X Y Z P
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Pri
me
s b
etw
ee
n 0
-7
I3 I2 I1 C1 C0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
1’s
Co
un
t o
f In
pu
ts
7.12
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders/checkers
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
7.13
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
x
yz
A
7.14
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 0 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
x
yz
zyx
A
B
7.15
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B C
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 0 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 0 0 1
x
yz
zyx
zyx
A
B
C
7.16
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B C F
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 1 1
x
yz
zyx
zyx
F
A
B
C
7.17
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B C F
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 1 1
x
yz
zyx
zyx
F
A
B
C
F(1,0,0) = 1
1
00
001
001
1
0
1
0
7.18
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B C F
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 1 1
x
yz
zyx
zyx
F
A
B
C
F(0,1,0) = 1
0
10
010
010
1
1
0
0
7.19
Using Decoders to Implement Functions
• Given an any logic function, it can be implemented with the superposition of decoders
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
X Y Z A B C F
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 1
0 1 1 0 0 0 0
1 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 0
1 1 1 0 0 1 1
x
yz
zyx
zyx
F
A
B
C
F(0,1,1) = 0
0
11
110
110
0
0
0
0
7.20
Minterms
• An n-input combinational system can be described with 2n row truth table
• Each row in the truth table (input combination) has a unique logic expression that only evaluates to '1' for that combination– This logic expression is known as a minterm
n
inputs Circuit
2n row
truth table
ഥ𝒙 ∙ 𝒚 ∙ ത𝒛
𝒙 ∙ 𝒚 ∙ 𝒛
7.21
Defining Minterms
• We call an AND gate checking for one specific combination of all the inputs (one line in the truth table) a minterm
• Write the expression for each minterm of 3 variables: x,y,z
Minterms
Row # Abbrev Minterm Expression x y z m0 m1 m2 m3 m4 m5 m6 m7
0 m0 0 0 0 1 0 0 0 0 0 0 0
1 m1 0 0 1 0 1 0 0 0 0 0 0
2 m2 0 1 0 0 0 1 0 0 0 0 0
3 m3 0 1 1 0 0 0 1 0 0 0 0
4 m4 1 0 0 0 0 0 0 1 0 0 0
5 m5 1 0 1 0 0 0 0 0 1 0 0
6 m6 1 1 0 0 0 0 0 0 0 1 0
7 m7 1 1 1 0 0 0 0 0 0 0 1
7.22
Checkers / Decoders
• The mi functions on the previous slide are just AND gate checkers– That combination can be changed by adding inverters to the inputs
– We can think of the AND gate as “checking” or “decoding” a specific combination and outputting a ‘1’ when it matches.
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
m5x
y
z
X Y Z F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
m0x
y
z
AND gate decoding
(checking for)
combination 101
AND gate decoding
(checking for)
combination 000
7.23
Applying Minterms to Synthesize a Function
• Each numbered minterm checks whether the inputs are equal to the corresponding combination. When the inputs are equal, the minterm will evaluate to 1 and thus the whole function will evaluate to 1.
x y z P0 0 0 00 0 1 0 use…0 1 0 1 m2
0 1 1 1 m3
1 0 0 01 0 1 1 m5
1 1 0 01 1 1 1 m7
P = m2 + m3 + m5 + m7
= x’yz’ + x’yz + xy’z + xyz
when x,y,z = {0,1,0} = 2 then
P = 0’•1•0’ + 0’•1•0 + 0•1’•0 + 0•1•0
= 1 + 0 + 0 + 0 = 1
when x,y,z = {1,0,1} = 5 then
P = 1’•0•1’ + 1’•0•1 + 1•0’•1 + 1•0•1
= 0 + 0 + 1 + 0 = 1
when x,y,z = {0,0,1} = 1 then
P = 0’•0•1’ + 0’•0•1 + 0•0’•1 + 0•0•1
= 0 + 0 + 0 + 0 = 0
7.24
Definitions
• Literal: A single bit variable or its inverse– Good: x, y', ALARM'
– Bad: (x+y)
• Product Term: A single literal by itself or an AND'ing (not NAND'ing) of literals
– Good: z, x•y, ALARM•PANIC•ENABLED
– BAD: (x•y)', ALARM•(PANIC+ENABLED)
• Minterm: A product term where all the input variables of a function appear as exactly one literal
– f(x,y,z) => • x’y’z
• xyz
• x’y
• x+y+z
7.25
Minterms
• Consider F(A,B)
• One minterm per combination of the input variables
• Only one minterm can evaluate to 1 at any time
A B F A’•B’ A’•B A•B’ A•B
0 0 0 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 1
m0 m1 m2 m3
7.26
Finding Equations/Circuits
• Given a function and checkers (called decoders) for each combination, we just need to OR together the checkers where F = 1
Checker
for 000
Checker
for 001
Checker
for 010
Checker
for 011
Checker
for 100
Checker
for 101
Checker
for 110
Checker
for 111
3-bit
number
{x,y,z}
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
F
Assume we use AND-
gate decoders that
output a ‘1’ when the
combination is found
7.27
Canonical Sums
• Given a T.T., ___ together all the minterms where F = _
– ( = SUM or OR of all the minterms)
X Y Z F
0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
m0m1m2m3m4m5m6m7
F = xyz(2,3,5,7)
Canonical Sum:
List the minterms
where F is 1.
F = m2+m3+m5+m7=(X'YZ')+(X'YZ)+(XY'Z)+(XYZ)
7.28
AN ALTERNATIVEUsing OR-gate checkers
7.29
OR-Gate Checkers / Decoders
• An OR gate only outputs ‘0’ for 1 combination– That combination can be changed by adding inverters to the inputs
– We can think of the OR gate as “checking” or “decoding” a specific combination and outputting a ‘0’ when it matches.
OR gate decoding
(checking for)
combination 010
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Fx
y
z
OR gate decoding
(checking for)
combination 110
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
Fx
y
z
7.30
Finding Equations/Circuits
• Given a function and checkers (called decoders) for each combination, we just need to AND together the checkers where F = 0
Checker
for 000
Checker
for 001
Checker
for 010
Checker
for 011
Checker
for 100
Checker
for 101
Checker
for 110
Checker
for 111
3-bit
number
{x,y,z}
X Y Z F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
F
Assume we use OR-
gate decoders that
output a ‘0’ when the
combination is found
7.31
Defining Maxterms
• We call an OR gate checking for one specific combination of all the inputs (one line in the truth table) a maxterm
• Write the expression for each maxterm of 3 variables: x,y,z
Maxterms
Row # Abbrev Maxterm Expression x y z M0 M1 M2 M3 M4 M5 M6 M7
0 M0 x + y + z 0 0 0 0 1 1 1 1 1 1 1
1 M1 x + y + z' 0 0 1 1 0 1 1 1 1 1 1
2 M2 x + y' + z 0 1 0 1 1 0 1 1 1 1 1
3 M3 x + y' + z' 0 1 1 1 1 1 0 1 1 1 1
4 M4 x' + y + z 1 0 0 1 1 1 1 0 1 1 1
5 M5 x' + y + z' 1 0 1 1 1 1 1 1 0 1 1
6 M6 x' + y' + z 1 1 0 1 1 1 1 1 1 0 1
7 M7 x' + y' + z' 1 1 1 1 1 1 1 1 1 1 0
7.32
Applying Maxterms to Synthesize a Function
• Each output that should produce a '0' can be checked-for with an OR gate– We refer to that OR-gate checker as a Maxterm of the function (Mi)
• We then AND together the maxterms
x y z P use…0 0 0 0 M0
0 0 1 0 M1
0 1 0 10 1 1 11 0 0 0 M4
1 0 1 11 1 0 0 M6
1 1 1 1
P = M0 • M1 • M4 • M6
= (x+y+z) • (x+y+z’) • (x’+y+z) • (x’+y’+z)
when x,y,z = {0,0,1} = 1 then
P = (0+0+1) • (0+0+1’) • (0’+0+1) • (0’+0’+1)
= 1 • 0 • 1 • 1 = 0
when x,y,z = {1,1,0} = 6 then
P = (1+1+0) • (1+1+0’) • (1’+1+0) • (1’+1’+0)
= 1 • 1 • 1 • 0 = 0
when x,y,z = {1,1,1} = 7 then
P = (1+1+1) • (1+1+1’) • (1’+1+1) • (1’+1’+1)
= 1 • 1 • 1 • 1 = 1
7.33
Canonical Products
• Given a T.T., AND together all the maxterms where F = 0
X Y Z F
0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
F = M0•M1•M4•M6=(X+Y+Z)•(X+Y+Z')•(X'+Y+Z)•(X'+Y'+Z) M0
M1M2M3M4M5M6M7
F = xyz(0,1,4,6)
Canonical Product:
List the maxterms
where F is 0.
7.34
Definitions
• Literal: A single bit variable or its inverse– Good: x, y', ALARM'
• Sum Term: A single literal by itself or an OR'ing (not NOR'ing) of literals – Good: z, x'+y, ALARM+PANIC+ENABLED
– BAD: (x+y)', ALARM•(PANIC+ENABLED)
• Maxterm: A sum term where each input variable of a function appears as exactly one literal
– f(x,y,z) => • x’+y’+z
• x+y+z
• (x+y)'
• x•y•z
7.35
LOGIC FUNCTION NOTATIONYou are only responsible for Canonical Sums (not Products)
7.36
Boolean Algebra Terminology
• SOP (Sum of Products) Form: An SOP expression is a logical sum (OR) of product terms
– Correct Examples: [x’•y’•z + w + a’•b•c], [w + x’•z•y + y’z]
– Incorrect Examples: [ x’•y•z + w•(a+b) ], [ x•y + (y’•z)’ ]
• POS (Product of Sums) Form: A POS expression is a logical product (AND) of sum terms.
– Correct Examples: [(x+y’+z) • (w’+z) • (a)], [z’•(x+y)•(w’+y)]
– Incorrect Examples: [x’ + y•(x+w)], [(x+y)•(x+z)’ ]
• SOP equations yield 2-level circuits with AND gates in the 1st level with an OR gate in the 2nd (aka AND-OR circuits)
• POS equations yield 2-level circuits with OR gates in the 1st level with an AND gate in the 2nd (aka OR-AND circuits) =
=
AND-OR
OR-AND
7.37
Check Yourself
Expression SOP / POS / Both / Neither
w•x•(y•z)’ + xy’z + w
xy+xz+(w’yz)
(w+y’+z)(w+x)
(w+y)x(w’+z)
wy + wy + xy’
w+x+y
Neither (Can’t have complements of
sub-expressions…only literal)
SOP (parentheses are unnecessary)
POS
POS (a single literal is a sum term)
SOP (redundancy doesn’t matter)
Both (individual literals are both a
product and sum term)
7.38
Canonical Sums & Products
• Canonical Sum: An SOP expression where all the product terms are minterms (i.e. have each literal in each product term)
• Canonical Product: A POS expression where all the sum terms are maxterms (i.e. each literal in each sum term)
X Y Z F
0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
F = xyz(2,3,5,7)
Canonical Sum:
F = M0•M1•M4•M6 =(X+Y+Z)•(X+Y+Z')• (X'+Y+Z)•(X'+Y'+Z)
F = m2+m3+m5+m7 =(X'YZ’)+(X'YZ)+(XY’Z)+(XYZ)
F = xyz(0,1,4,6)
Canonical Product:
7.39
Logic Functions
• A logic function maps input combinations to an output value (‘1’ or ‘0’)
• 3 possible representations of a function
– Equation (canonical form or simplified)
– Schematic
– Truth Table
• Can convert betweenrepresentations
• Truth table is onlyunique representation*
* Canonical Sums/Products (minterm/maxterm) representationprovides a standard equation/schematic form that is unique per function
7.40
Unique Representations
= zyxP
,,)7,5,3,2(
• Truth Tables along with Canonical Sums and Products specify a function uniquely– Canonical => Same functions will have same representations
• Equations/circuit schematics are NOT inherently canonical
x y z P
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
= zyxP
,,)6,4,1,0(
Canonical
Sum
Canonical
Product
Truth
Table
ON-Set of P
(minterms)
OFF-Set of P
(maxterms)
Yields SOP equation,
AND-OR circuit
Yields POS equation,
OR-AND circuit
7.41
2- AND 3-VARIABLE THEOREMSFinding simplified equations and circuits
7.42
Why Boolean Algebra
• We can already convert any truth table that we derive into an equation and circuit by using canonical sums/products
• But canonical sums/products yield the LARGEST equation/circuit
• By starting with canonical form and then using Boolean algebra to simplify, we can arrive and smaller (even minimal) circuits
7.43
2 & 3 Variable Theorems
T6 X+Y = Y+X T6' X•Y = Y•X Commutativity
T7 (X+Y)+Z = X+(Y+Z) T7' (X•Y)•Z = X•(Y•Z) Associativity
T8 XY+XZ = X(Y+Z) T8’ (X+Y)(X+Z) = X+YZ Distribution &
Factoring
T9 X + XY = X T9’ X(X+Y) = X Covering
T10 XY + XY’ = X T10’ (X+Y)(X+Y’) = X Combining
T11 XY + X’Z + YZ =
XY + X’Z
T11’ (X+Y)(X’+Z)(Y+Z) =
(X+Y)(X’+Z)
Consensus
DM (X+Y)' = X'•Y' DM' (X•Y)'=X'+Y' DeMorgan's
7.44
Proofs Through Other Theorems
• Prove T9: X + XY = X– X(1 + Y) = X [T8]
– X(1) = X [T2]
– X = X [T1']
• Prove T10: XY + XY' = X– X(Y + Y') = X [T8]
– X(1) = X [T2]
– X = X [T1']
• Prove T10': (X+Y)(X+Y')=X– XX + XY' + XY + YY' = X [T8 / FOIL]
– X + XY' + XY + 0 = X [T3 and T5']
– X(1 + Y' + Y) = X [T1, T8]
– X = X [T2, T1']
T8 XY+XZ = X(Y+Z) T8’ (X+Y)(X+Z) = X+YZ
T9 X + XY = X T9’ X(X+Y) = X
T10 XY + XY’ = X T10’ (X+Y)(X+Y’) = X
T11 XY + X’Z + YZ =
XY + X’Z
T11’ (X+Y)(X’+Z)(Y+Z) =
(X+Y)(X’+Z)
X + YY' = X [T8']X + 0 = X [T5']X = X [T1]OR
7.45
DeMorgan’s Theorem
• Inverting output of an AND gate = inverting the inputs of an OR gate• Inverting output of an OR gate = inverting the inputs of an AND gate
A function’s inverse is equivalent to inverting all the inputs and changing AND to OR and vice versa
A B Out
0 0 1
0 1 1
1 0 1
1 1 0
A•B
A+B
A+B
A•B
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
A B Out
0 0 1
0 1 1
1 0 1
1 1 0
A B Out
0 0 1
0 1 0
1 0 0
1 1 0Analogy: Turning a gate "inside-out" (like your socks).
7.46
DeMorgan’s Theorem
F = (X+Y) + Z • (Y+W)
F = (X+Y) + Z • (Y+W)
F = (X+Y) • (Z • (Y+W))
F = (X•Y) • (Z + (Y+W))
F = (X•Y) • (Z + (Y•W))
Use DeMorgan’s theorem to simplify "move" inversions
(either to break-up "big bars" or join "small bars"
7.47
Generalized DeMorgan’s Theorem
F = (X+Y) + Z • (Y+W)
F = X•Y • (Z + (Y•W))
To find F’, swap AND’s and OR’s and complement each
literal. However, you must maintain the original order of
operations.
F’(X1,…,Xn,+,•) = F(X1’,…,Xn
’,•,+)
F = X+Y + (Z • (Y+W))Fully parenthesized to
show original order of ops.
AND’s & OR’s swapped
Each literal is inverted
Note: This parentheses
doesn’t matter (we are
just OR’ing X’, Y, and the
following subexpression)
7.48
DeMorgan’s Theorem Example
• Cancel as many bubbles as you can using DeMorgan’s theorem.
X
Z
Y
W
F
7.49
AND-OR / NAND-NAND
• Canonical Sums yield
– AND-OR Implementation
– NAND-NAND Implementation
=
7.50
OR-AND / NOR-NOR
• Canonical Products yield
– OR-AND Implementation
– NOR-NOR Implementation ==
7.51
DeMorgan's Practice
• Convert the circuits mux below to use only NAND or NOR gates?
B Warning
Buzzer
B = (K+H)·D
Key in Ignition
Door Opened
Headlights on
K
D
H
7.52
Logic Synthesis
• Describe the function – Usually with a truth table
• Find the sum of minterm (or product of maxterm) expression– In this class, you're only responsible for the sum of
minterm approach
• Use Boolean Algebra (T8-T11) to find a simplified expression
7.53
Synthesize/Simplify Exercise 1
• Synthesize this function– First generate the canonical sum
– Then use theorems to simplify
X Y Z P
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Pri
me
s b
etw
ee
n 0
-7
T8 XY+XZ = X(Y+Z) T8’ (X+Y)(X+Z) = X+YZ
T9 X + XY = X T9’ X(X+Y) = X
T10 XY + XY’ = X T10’ (X+Y)(X+Y’) = X
T11 XY + X’Z + YZ =
XY + X’Z
T11’ (X+Y)(X’+Z)(Y+Z) =
(X+Y)(X’+Z)
• P = X'YZ' + X'YZ + XY'Z + XYZ
– X'Y(Z' + Z) + XZ(Y'+Y) [T8]
– X'Y + XZ [T5, T1']
7.54
Synthesize/Simplify Exercise 2
• Synthesize each output separately– First generate the canonical sum
– Then use theorems to simplify
T8 XY+XZ = X(Y+Z) T8’ (X+Y)(X+Z) = X+YZ
T9 X + XY = X T9’ X(X+Y) = X
T10 XY + XY’ = X T10’ (X+Y)(X+Y’) = X
T11 XY + X’Z + YZ =
XY + X’Z
T11’ (X+Y)(X’+Z)(Y+Z) =
(X+Y)(X’+Z)
A B C M1 M0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
Encode the highest input ID
(ie. 3, 2, or 1) that is ON (=1)
• M1 = m2 + m3 + m4 + m5 + m6 + m7
– A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC
– [T3 (A = A + A) allows us to replicate m6 and m7 ( ABC' + ABC )]
– A'BC' + A'BC + ABC' + ABC + AB'C' + AB'C + ABC' + ABC
– B(A'C' +A'C + AC' + AC) + A(B'C' + B'C + BC' + BC) [T8]
– B(A'(C'+C) + A(C'+C) ) + A(B'(C+C') + B(C' + C)) [T8/T5 or T10]
– B(A'+ A ) + A(B' + B) [T8/T5] = B + A [Final Answer]
• M0 = m1 + m4 + m5 + m6 + m7
– A'B'C + AB'C' + AB'C + ABC' + ABC
– A'B'C + AB'C + AB'C' + AB'C + ABC' + ABC [Use T3 to replicate m5]
– B'C(A' + A) + A(B'C' + B'C + BC' + BC) [T8]
– B'C + A [T8/T5 or T10] = B'C + A [Final Answer]
7.55
Synthesize/Simplify Exercise 3 (Optional)
• Synthesize each output separately– First generate the canonical sum
– Then use theorems to simplify
T8 XY+XZ = X(Y+Z) T8’ (X+Y)(X+Z) = X+YZ
T9 X + XY = X T9’ X(X+Y) = X
T10 XY + XY’ = X T10’ (X+Y)(X+Y’) = X
T11 XY + X’Z + YZ =
XY + X’Z
T11’ (X+Y)(X’+Z)(Y+Z) =
(X+Y)(X’+Z)
A B C C1 C0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
1’s
Co
un
t o
f In
pu
ts
• C1 = m3 + m5 + m6 + m7
– A'BC + AB'C + ABC' + ABC
– [Replicate m7 twice so we can simplify the others: m3 + m7 + m5 + m7 + m6 + m7]
– A'BC + ABC + AB'C + ABC + ABC' + ABC
– BC(A'+A) + AC(B'+B) + AB(C'+C) = BC + AC + AB [Final Answer]
• C0 = m1 + m2 + m4 + m7
– A'B'C + A'BC' + AB'C' + ABC [Not much to factor that will cause simplification]
– A'(B'C + BC') + A(B'C' + BC) [But write the truth tables of B'C+BC' and B'C'+BC]
– A'(BꚚC) + A(BꚚC)' [But if we let W=BꚚC then we have A'W + AW'…write its TT]
– A Ꚛ B Ꚛ C [Final Answer]