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EE1411
Arithmetic Circuits
Chapter 14Chapter 14
Arithmetic Circuits (I):Arithmetic Circuits (I):Adder DesignsAdder Designs
Rev. 1.0 05/12/2003Rev. 2.0 06/05/2003Rev. 2.1 06/12/2003
EE1412
Arithmetic Circuits
A Generic Digital ProcessorA Generic Digital Processor
MEMORY
DATAPATH
CONTROL
INP
UT
-OU
TP
UT
EE1413
Arithmetic Circuits
Building Blocks for Digital ArchitecturesBuilding Blocks for Digital Architectures
Arithmetic and Unit
- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
EE1414
Arithmetic Circuits
Intel MicroprocessorIntel Microprocessor
9-1
Mux
9-1
Mux
5-1
Mux
2-1
Mux
ck1
CARRYGEN
SUMGEN+ LU
1000um
b
s0
s1
g64
sum sumb
LU : LogicalUnit
SU
MS
EL
a
to Cache
node1
RE
G
Itanium has 6 integer execution units like this
EE1415
Arithmetic Circuits
Bit-Sliced DesignBit-Sliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Reg
iste
r
Add
er
Shif
ter
Mul
tipl
exer
ControlD
ata-
In
Dat
a-O
ut
Tile identical processing elements
EE1416
Arithmetic Circuits
Itanium Integer DatapathItanium Integer Datapath
Fetzer, Orton, ISSCC’02
EE1417
Arithmetic Circuits
AddersAdders
EE1418
Arithmetic Circuits
Several Implementations of AddersSeveral Implementations of Adders
One-Bit Full Adder (Cell) Carry-Ripple Adder Bit-Serial Adder Mirror Adder Transmission-Gate Adder Manchester Adder Carry lookahead Adder Carry-Select Adder
EE1419
Arithmetic Circuits
Full-Adder (FA)Full-Adder (FA)A B
Cout
Sum
Cin Fulladder
Generate (G) = AB
Propagate (P) = A B
Delete = A B
EE14110
Arithmetic Circuits
Boolean Function of Binary Full-Adder Boolean Function of Binary Full-Adder
iiii
i
ABCCBACBACBA
CBAS
ACBCABC iiO
A B
Cout
Sum
Cin Fulladder
)( iOi CBACABCS
)( BACABC iO CMOS Implementation
EE14111
Arithmetic Circuits
Express Sum and Carry as a function of P, G, DExpress Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A B
Delete = A B
Can also derive expressions for S and Co based on D and P
Propagate (P) = A BNote that we will be sometimes using an alternate definition for
EE14112
Arithmetic Circuits
Carry-Ripple AdderCarry-Ripple Adder
Worst-case delay is linear with the number of bits
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(Ci,1)
Co,1 Co,2 Co,3
td = O(N)tadder = (N-1)tcarry + tsum
CriticalPath
•Propagation delay (or critical path) is the worst-case delay over all possible input patterns•A= 0001, B=1111, trigger the worst-case delay•A: 0 1, and B= 1111 fixed to set up the worst-case delay transition.
EE14113
Arithmetic Circuits
Complimentary Static CMOS Full AdderComplimentary Static CMOS Full Adder
•Logic effort of Ci is reduced to 2 (c.f., A and B signals)•Ci is late arrival signal near the output signal •Co needs to be inverted Slow down the ripple propagate
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
OC
28 Transistors
EE14114
Arithmetic Circuits
Inversion PropertyInversion Property
A B
S
CoCi FA
A B
S
CoCi FA
S A B Ci S A B Ci
=
Co A B Ci Co A B Ci
=
EE14115
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting StagesMinimize Critical Path by Reducing Inverting Stages
•Exploit Inversion Property•Reduce One inverter delay in each Full-adder (FA) unit
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3C
EE14116
Arithmetic Circuits
SubtractorSubtractor
EE14117
Arithmetic Circuits
Bit-Serial AdderBit-Serial Adder
ia
ib
isOC
inC
)( 01234567 aaaaaaaaA
)( 01234567 bbbbbbbbB
A
B
EE14118
Arithmetic Circuits
A Better Structure: The Mirror AdderA Better Structure: The Mirror Adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
Exploring the “Self-Duality” of the Sum and Carry functions
EE14119
Arithmetic Circuits
Mirror Adder: Stick DiagramMirror Adder: Stick Diagram
CiA B
VDD
GND
B
Co
A Ci Co Ci A B
S
EE14120
Arithmetic Circuits
Mirror Adder DesignMirror Adder Design•The NMOS and PMOS chains are completely symmetrical
•A maximum of two series transistors can be observed in the carry-generation circuitry for good speed.
•When laying out the cell, the most critical issue is the minimization of the capacitance at node Co.
•The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
•The transistors connected to Ci are placed closest to the
output.
EE14121
Arithmetic Circuits
Transmission-Gate 6T XOR GateTransmission-Gate 6T XOR Gate
A B F
0 0 0
0 1 1
1 0 1
1 1 0
B
B
Truth Table
A=0: Pass B Signal
A=1: Inverting B Signal
B
B
EE14122
Arithmetic Circuits
Transmission-Gate Full Adder (24T)Transmission-Gate Full Adder (24T)
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
•Same delay for Sum and Carry Multiplier design
BAP
ii
i
PCCP
CPS
APCPC iO
EE14123
Arithmetic Circuits
Manchester Carry-Chain AdderManchester Carry-Chain Adder
CoCi
Gi
Di
Pi
Pi
VDD
CoCi
Gi
Pi
VDD
Static Circuits Dynamic Circuits
iiiO DGCPC )(
iiiO
O
GCPC
C
,1
1,0
EE14124
Arithmetic Circuits
Manchester Carry ChainManchester Carry Chain
G2
C3
G3
Ci,0
P0
G1
VDD
G0
P1 P2 P3
C3C2C1C0
EE14125
Arithmetic Circuits
Manchester Carry-Chain AdderManchester Carry-Chain Adder
Pi + 1 Gi + 1
Ci
Inverter/Sum Row
Propagate/Generate Row
Pi Gi
Ci - 1Ci + 1
VDD
GND CCRR
RCNN
RCt
ij
i
jj
N
iiP
, where2
)1(69.0
69.011
EE14126
Arithmetic Circuits
Manchester Adder Circuits (Weste)Manchester Adder Circuits (Weste)
Dynamic Static Mux-based
4-bitSection
sum<n>
EE14127
Arithmetic Circuits
Manchester Adder Circuits (Cont.)Manchester Adder Circuits (Cont.)
Dynamic stage When CLK is low, the output node is pre-charged by the p
pull-up transistor. When CLK goes high, the pull-down transistor turns on. If carry generate G=AB is true the output node
discharges. If carry propagate P=A+B is true a previous carry may
be coupled to the output node, conditionally discharging it. Static stage
This requires P to be generated as AB The Manchester adder stage improves on the carry-
lookahead implementation.
EE14128
Arithmetic Circuits
Carry-Bypass Adder DesignCarry-Bypass Adder Design
Idea: If ( )then CO,3 = C I,0
else Kill or Generate
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
tipl
exer
BP=PoP1P2P3
Also called Carry-Skip
13210 PPPP
EE14129
Arithmetic Circuits
Manchester Adder Circuits (Cont.)Manchester Adder Circuits (Cont.)
Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free
The control signals T1,T2,and T3 shown in Fig6(b) are generated by:
T1 = -(P0P1P2)P3
T2 = -P3
T3 = P0P1P2P3
Wired OR
EE14130
Arithmetic Circuits
Manchester Adder Circuits (Cont.)Manchester Adder Circuits (Cont.)
The worst case propagation time of a Manchester
adder can be improved by bypassing the four stages
if all carry-propagate signals are true.
Fig. 6(b) uses a “conflict -free” bypass circuit, which
improves the speed by using a 3-input multiplexer that
prevents conflicts at the wired OR node in the adder.
In Fig. 6(b), the inverter presented on the Cin signal
has been moved to the center of the carry chain to
improve speed.
EE14131
Arithmetic Circuits
Carry-Bypass Adder (cont.)Carry-Bypass Adder (cont.)
Carrypropagation
Setup
Bit 0–3
Sum
M bits
tsetup
tsum
Carrypropagation
Setup
Bit 4–7
Sum
tbypass
Carrypropagation
Setup
Bit 8–11
Sum
Carrypropagation
Setup
Bit 12–15
Sum
tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum
M bits form a Section (N/M) Bypass Stages
EE14132
Arithmetic Circuits
Carry Ripple versus Carry BypassCarry Ripple versus Carry Bypass
N
tp
ripple adder
bypass adder
4..8
Wordlength (N) > 4~8 is better for Bypass Adder
EE14133
Arithmetic Circuits
Carry-Select AdderCarry-Select AdderSetup
"0" Carry Propagation
"1" Carry Propagation
2-to-1 Multiplexer
Sum Generation
Co,k-1 Co,k+3
"0"
"1"
P,G
Carry Vector
EE14134
Arithmetic Circuits
Carry-Select AdderCarry-Select Adder
Fig7. Carry-select adder:(a) basic architecture (b) 32-bit carry-select adder example
EE14135
Arithmetic Circuits
Carry Select Adder: Critical PathCarry Select Adder: Critical Path
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry
Setup
Ci,0 Co,3 Co,7 Co,11 Co,15
S0–3
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry
Setup
S4–7
0
1
Sum Generation
Multiplexer
1-Carry
0-Carry 0-Carry
Setup
S8–11
0
1
Sum Generation
Multiplexer
1-Carry
Setup
S
EE14136
Arithmetic Circuits
Linear Carry Select Linear Carry Select
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
S0-3 S4-7 S8-11 S12-15
Ci,0
(1)
(1)
(5)(6) (7) (8)
(9)
(10)
(5) (5) (5)(5)
EE14137
Arithmetic Circuits
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Setup
"0" Carry
"1" Carry
Multiplexer
Sum Generation
"0"
"1"
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13
S0-1 S2-4 S5-8 S9-13
Ci,0
(4) (5) (6) (7)
(1)
(1)
(3) (4) (5) (6)
Mux
Sum
S14-19
(7)
(8)
Bit 14-19
(9)
(3)
Square Root Carry SelectSquare Root Carry Select
N-bit adder with P stages: 1st stage adds M bits, 2nd has (M+1) bits
NPMPP
N 2)2
1(
2
2
EE14138
Arithmetic Circuits
Adder Delays - Comparison Adder Delays - Comparison
Square root select
Linear select
Ripple adder
20 40N
t p(in
un
it de
lays
)
600
10
0
20
30
40
50
EE14139
Arithmetic Circuits
Carry-Lookahead AddersCarry-Lookahead Adders
The linear growth of adder carry-delay with the size of the input word for n-bit adder maybe improved by calculation the carries to each stage in parallel.
EE14140
Arithmetic Circuits
Carry of the ith stage ---
Expanding:
For four stages, the appropriate term:
C0= G0 + P0CI
C1= G1 + P1G0 + P1P0CI
C2= G2 + P2G1 + P2P1G0 + P2P1P0CI
C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI
Fig1. Generic carry-lookahead adder
Carry-Lookahead Adders (cont’d)Carry-Lookahead Adders (cont’d)
0,01211
211 )(
iiiiiiii
iiiiii
CPPPGPPGPG
CPGPGC
signal Propagate --
signal Generate -- 1
iii
iii
iiii
BAP
BAG
CPGC
EE14141
Arithmetic Circuits
EE14142
Arithmetic Circuits
Look-ahead Adder - Basic IdeaLook-ahead Adder - Basic Idea AN-1, BN-1A1, B1
P1
S1
• • •
• • • SN-1
PN-1Ci, N-1
S0
P0Ci,0 Ci,1
A
)))(((
)(
),,(
0,00111,
2,11,
1,1,,
ikkkkkO
kOkkkkkO
kOkkkOkkkO
CPGPPGPGC
CPGPGC
CPGCBAfC
EE14143
Arithmetic Circuits
Static CMOS CircuitsStatic CMOS Circuits
Co k Gk Pk Gk 1– Pk 1– Co k 2–+ +=
Co k Gk Pk Gk 1– Pk 1– P1 G0 P0 Ci 0+ + + +=
Expanding Lookahead equations:
All the way:
Co,3
Ci,0
VDD
P0
P1
P2
P3
G0
G1
G2
EE14144
Arithmetic Circuits
Dynamic CMOS CircuitsDynamic CMOS Circuits
• The worst-case delay path in this circuit has six
n-transistor in series.
EE14145
Arithmetic Circuits
Carry-Lookahead Adders
• Size and fan-in of the gates needed to
implement this carry-lookahead scheme can
clearly get out of hand
• Number of stages of lookahead is usually
limited to about 4.
• The circuit and layout are quite irregular
compared with ripple adder designs.
EE14146
Arithmetic Circuits
SummarySummary
Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs.
Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.
For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks