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EE1411
VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 1
Chapter 9Chapter 9
Memory Diagnosis and Built-In Memory Diagnosis and Built-In Self-RepairSelf-Repair
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 2
What is this chapter about?What is this chapter about? Why diagnostics?
Yield improvement– Repair and/or design/process debugging
BIST design with diagnosis support MECA: a system for automatic
identification of fault site and fault type Built-in self-repair (BISR) for embedded
memories Redundancy analysis (RA) algorithms Built-in redundancy analysis (BIRA)
EE1413
VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 3
How to Identify Faults?How to Identify Faults?RAM Circuit/Layout Tester/BIST Output
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 4
Fault Model SubtypesFault Model Subtypes
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 5
March Signature & DictionaryMarch Signature & DictionaryMarch 11N
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 6
Memory Error Catch and Analysis (MECA)Memory Error Catch and Analysis (MECA)
Source: Wu, et al., ICCAD00
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 7
BIST with Diagnosis SupportBIST with Diagnosis Support
Source: Wang, et al., ATS00
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 8
Test ModeTest Mode In Test Mode it runs a fixed algorithm for
production test and repair. Only a few pins need to be controlled, and BGO
reports the result (Go/No-Go).
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 9
CTR State Diagram in Test ModeCTR State Diagram in Test Mode
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 10
Fault Analysis Mode (FSI Timing)Fault Analysis Mode (FSI Timing) In Fault Analysis Mode, we can apply a
longer March algorithm for diagnosis FSI captures the error information of the faulty
cells
EOP format:
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 11
CTR State Diagram in Analysis ModeCTR State Diagram in Analysis Mode
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 12
Fault AnalysisFault Analysis Derive analysis equations from the fault dictionary
Convert error maps to fault maps by the equations
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 13
TPG State DiagramTPG State Diagram
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 14
Waveform Generated by TPGWaveform Generated by TPG
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 15
Diagnostic Test Algorithm GenerationDiagnostic Test Algorithm Generation Start from a base test: generated by TAGS, or user-specified Generation options reduced to Read insertions Diagnostic resolution: percentage of faults that can be
distinguished
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 16
Fault Bitmap ExamplesFault Bitmap Examples
Idempotent Coupling Fault Stuck-at 0
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 17
Redundancy and RepairRedundancy and Repair Problem:
We keep shrinking RAM cell size and increasing RAM density and capacity. How do we maintain the yield?
Solutions: Fabrication
– Material, process, equipment, etc. Design
– Device, circuit, etc. Redundancy and repair
– On-line EDAC (extended Hamming code; product code)
– Off-line Spare rows, columns, blocks, etc.
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 18
From BIST to BISRFrom BIST to BISR
BISTBIST BISDBISD BIRABIRA BISRBISR
• BIST: built-in self-test• BIECA: built-in error catch & analysis
-BISD: built-in self diagnosis-BIRA: built-in redundancy analysis
• BISR: built-in self-repair
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 19
RAM Built-In Self-Repair (BISR)RAM Built-In Self-Repair (BISR)
RAM
MU
XBIST
Redundancy
Analyzer
Reconfiguration MechanismS
pare
Ele
me
nts
EE14120
VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 20
RAM Redundancy AllocationRAM Redundancy Allocation 1-D: spare rows (or columns) only
SRAM Algorithm: Must-Repair
2-D: spare rows and columns (or blocks) Local and/or global spares NP-complete problem Conventional algorithm:
– Must-Repair phase
– Final-Repair phase Repair-Most (greedy) [Tarr et al., 1984]
Fault-Driven (exhaustive, slow) [Day, 1985]
Fault-Line Covering (b&b) [Huang et al., 1990]
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 21
Redundancy ArchitecturesRedundancy Architectures
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 22
Redundancy Analysis SimulationRedundancy Analysis SimulationMemory
Defect InjectionFault Translation
Faulty Memory
Test AlgorithmSimulation
RA Simulation
RAAlgorithm
SpareElements
ResultFail bit map and sub-maps
Ref: MTDT02
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 23
DefinitionsDefinitions Faulty line: row or column with at least one
faulty cell A faulty line is covered if all faulty cells in the line
are repaired by spare rows and/or columns. A faulty cell not sharing any row or column
with any other faulty cell is an orthogonal faulty cell
r: number of (available) spare rows c: number of (available) spare columns F: number of faulty cells in a block F’:number of orthogonal faulty cells in a block
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 24
Example Block with Faulty CellsExample Block with Faulty Cells
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 25
Repair-Most (RM)Repair-Most (RM)
1. Run BIST and construct bitmap
2. Construct row and column error counters
3. Run Must-Repair algorithm
4. Run greedy final-repair algorithm
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 26
Worst-Case Bitmap (After Must-Repair)Worst-Case Bitmap (After Must-Repair)
r=2; c=4
• Max F=2rc
• Max F’=r+c
• Bitmap size: (rc+c)(cr+r)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 27
Essential Spare Pivoting (ESP)Essential Spare Pivoting (ESP) Maintain high repair rate without using a
bitmap Small area overhead
Fault Collection (FC) Collect and store faulty-cell address using row-
pivot and column-pivot registers– If there is a match for row (col) pivot, the pivot is an
essential pivot– If there is no match, store the row/col addresses in the
pivot registers If F > r+c, the RAM is irreparable
Spare Allocation (SA) Use row and column pivots for spare allocation
– Spare rows (cols) for essential row (col) pivots SA for orthogonal faults Ref: Huang et al., IEEE TR, 11/03
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 28
ESP ExampleESP Example
(1,0) (1,6) (2,4) (3,4) (5,1) (5,2) (7,3)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 29
Cell Fault Size DistributionCell Fault Size Distribution
Mixed Poisson-exponential distribution
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 30
Repair Rate (r=10)Repair Rate (r=10)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 31
SC
G0
SC
G1
Redundancy OrganizationRedundancy Organization
SEG0
SEG1
SR: Spare Row; SCG: Spare Column Group; SEG: Segment
SR0SR1
ITC03
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 32
Main Memory
Spare Memory
BIRA
BIST
Wrapper
Q
D
A
BISR ArchitectureBISR Architecture
MAO
POR
MAO: mask address output; POR: power-on resetRef: ITC03
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 33
Power-On BISR ProcedurePower-On BISR Procedure
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 34
Subword A subword is consecutive bits of a word. Its length is the same as the group size.
Example: a 32x16 RAM with 3-bit row address and 2-bit column address
Subword DefinitionSubword Definition
A word with 4 subwords A subword with 4 bits
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 35
To reduce the complexity, we use two row-repair rules If a row has multiple faulty, we repair the faulty row by a spare row
if available.
If there are multiple faulty subwords with the same column address and different row addresses within a segment, the last detected faulty subword should be repaired with an available spare row.
Examples:
Row-Repair RulesRow-Repair Rules
subword subword
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 36
BIRA ProcedureBIRA Procedure
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 37
Basic BIST ModuleBasic BIST Module
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 38
BIRA ModuleBIRA Module
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 39
State Diagram of PEState Diagram of PE
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 40
Block Diagram of ARUBlock Diagram of ARU
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 41
Repair Rate AnalysisRepair Rate Analysis Repair rate
The ratio of the number of repaired memories to the number of defective memories
A simulator has been implemented to estimate the repair rate of the proposed BISR scheme
[Huang et al., MTDT02] Industrial case:
SRAM size: 8Kx64 # of injected random faults: 1~10 # of memory samples: 534 RA algorithms: proposed and exhaustive search
algorithms
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 42
An Industrial CaseAn Industrial Case
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 43
Redundancy: 4 spare rows and 2 spare column groupsGroup size: 4
A 8Kx64 Repairable SRAMA 8Kx64 Repairable SRAM
Technology: 0.25umSRAM area: 6.5 mm2
BISR area : 0.3 mm2
Spare area : 0.3 mm2
HOspare: 4.6%HObisr: 4.6%Repair rate: 100% (if # random faults is no more than 10)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 44
Waveform of EMA & MAOWaveform of EMA & MAO
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 45
Normal Mode WaveformNormal Mode Waveform
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 46
Repair Rate (Group Size 2)Repair Rate (Group Size 2)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 47
Repair Rate (Group Size 4)Repair Rate (Group Size 4)
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 48
Yield vs. Repair RateYield vs. Repair Rate
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VLSI Test Principles and Architectures Ch. 9 - Memory Diagnosis & BISR - P. 49
Concluding RemarksConcluding Remarks BIST with diagnosis support
Fault type identification done by an offline diagnosis process using MECA
RAM design and process debugging for yield enhancement
From BIST to BIRA Effective implementation by ESP
– Greedy algorithm
An industrial case has been experimented Full repair achieved (for # random faults no more
than 10) Only 4.6% area overhead for the 8Kx64 SRAM