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Feb 7, 2022 Lecturer Name [email protected] Contact Number IT2001PA Engineering Essentials (2/2) Chapter 17 - Monostable Operation of the 555 IC Timer

Ee2 chapter17 monstable_operation

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Apr 11, 2023

Lecturer Name [email protected]

Contact Number

IT2001PAEngineering Essentials (2/2)

Chapter 17 - Monostable Operation of the 555 IC Timer

2

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

Lesson Objectives

Upon completion of this topic, you should be able to: Students should be able to describe and verify the

circuit operation and applications of a monostable multivibrator.

Calculate the pulse width of a monostable multivibrator circuit.

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

Specific Objectives

Students should be able to : Draw the circuit of a monostable multivibrator using IC

555. Explain the operation of the monostable multivibrator. State the applications of monostable multivibrator.

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Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

Monostable Multivibrator It is also known as one-shot multivibrator. Is stable in only one of two voltage levels. When a trigger is received it switches to the other state

for a period of time (t ) and then returns to the stable state.

Application as a timer.

Output

MonostableMultivibrator

CircuitInput

t

5

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

555 as Monostable Multivibrator

555

R

C

7

6

2

83

5

1 0.01F

Output

+V

t = 1.1RC

Duration of output pulse at HIGH state, t = 1.1 RC

Trigger input

Vout

Vo

Vcc

tp

0 t

Vcc

Vcc13

Trigger input

Output

6

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

Example : To calculate the duration of the quasi-stable state of the monostable multivibrator. Given that C = 0.001µf and R = 10K.

T = 1.1 RC = 1.1(10 K x 0.001µf ) = 1.1(10 x 103 ) ( 0.001 x 10-6f ) = 0.000 011s = 11µs

Solution :

Output

MonostableMultivibrator

CircuitInput

t

7

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

Internal Circuitry of a 555 in the Monostable Mode

When power is applied initiallyComparator 2 output is driven Low by positive High at the trigger input.Comparator 1 output is driven High by the voltage charged across the external capacitor.S = 1 , R = 0, Q = 1 and output is Low.

+

_S Q

R+

_

R

C

3

2

1

2

Vcc

Vcc

Vcc

13

23

1

0

1

0

OUTPUT

INPUT

8

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

+

_S Q

R+

_

R

C

2

1

2

Vcc

Vcc

Vcc

13

23

1

0

1

0

OUTPUT

INPUT

When the transistor is ONThis set the flip-flop, Q=1 and the transistor is ON.The capacitor then discharges to the ground through the transistor and causes the output of comparator 1 to go Low.The flip-flop will now remain set because both inputs are Low (unchanged state).•The output will remain at this stable state until a Low trigger inputs is received.

9

Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

+

_S Q

R+

_

R

C

3

2

1

2

Vcc

Vcc

Vcc

13

23

1

0

1

0

OUTPUT

INPUT

When a Low trigger input is applied at pin 2Inverting input of comparator 2 from pin 2 will go Low.This is lower than the non inverting input which is 1/3Vcc.The output of comparator 2 is driven High.S = 0, R = 1, Q = 0, and it turns OFF the transistor.The circuit is now in its unstable state, output is logic ‘1’.

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Chapter 17 - Monostable Operation of the 555 IC Timer

IT2001PA Engineering Essentials (2/2)

+

_S Q

R+

_

R

C

3

2

1

2

Vcc

Vcc

Vcc

13

23

1

0

1

0

OUTPUT

INPUT

When the transistor is OFFInput has returned to High, Logic “1” . The external capacitor will charge through resistor R.When the voltage across the capacitor exceeds 2/3Vcc, the output of comparator 1 is driven High.Therefore S = 1, R = 0 and this sets the flip-flop. Q = 1.The circuit returns to its stable state, output is logic ‘0’.