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EE321Computer Architecture
Chap 01 : Review of Digital DesignChap. 01 : Review of Digital Design
Dr. Abdelhakim KhouasEmail : [email protected]
ab khouas@univ boumerdes [email protected] (ex. INELEC)
University M’hamed Bougara of Boumerdes
Course chapters
1. Review of Digital Design2 T L l f C t2. Top Level of Computer3. Central Processing Unit (CPU)4. Control Unit5. Memory5. Memory6. Instruction Set and Addressing Modes7 Input/Output Devices7. Input/Output Devices
EE321 - Chap. 01 – Review © A. Khouas1
Lecture Outline
1 Di it l t1. Digital systems2. Binary representations3. Combinational logic circuits4. Sequential circuits4. Sequential circuits5. Logic families
EE321 - Chap. 01 – Review © A. Khouas2
1. Digital Systems
What is Digital Circuit (Logic Circuit)?a g a u ( og u )To solve some everyday problems, we use electronic circuitselectronic circuits.Two large groups of electronic circuits:
1. Analog circuits: continues-valued signals2. Digital (logic) circuits: discrete-values signalg ( g ) g
Word is analog, we use DAC and ADC to convert analog and digital signals
EE321 - Chap. 01 – Review © A. Khouas3
1. Digital Systems
Different designs to solve the sameDifferent designs to solve the same problem:1. Software design: We write a program1. Software design: We write a program
than can be executed by a processor (uprocessor, ucontroller, DSP, GPU, ... etc )etc.)
2. Hardware Design: We design electronic circuit
1 P i t d Ci it B d (PCB)1. Printed-Circuit Board (PCB)2. Application Specific Integrated Circuit (ASIC or
IC)3 P bl L i D i (PLD CPLD3. Programmable Logic Devices (PLD, CPLD,
FPGA, ...)3. Hardware/Software Design
EE321 - Chap. 01 – Review © A. Khouas4
Copyright @ 2005 Intel Corporation.
1. Digital Systems
Why Digital Circuit?1 Easy to design1. Easy to design2. High performances3 R b t t i3. Robustness to noise4. Low cost5.66.7.
EE321 - Chap. 01 – Review © A. Khouas5
1. Digital Systems
Bits and BytesIn digital systems we use a two-level logic component called a bit to represent digital signalcomponent called a bit to represent digital signal
One bit can take two logic values: ‘0’ and ‘1’ or High (H) and Low (L)and Low (L)
EE321 - Chap. 01 – Review © A. Khouas6
1. Digital Systems
Bits and BytesBits and BytesA group of bit is called bit-vectorLeftmost bit is referred to as MSB (Most Significant Bit)g )Rightmost is LSB (Least Significant Bit)A group of 8 bits (10011101) is called ByteA group of 8 bits (10011101) is called Byte1 Kbyte = 1024 Bytes = 8192 bits1 Mbyte = 1024 Kbyte = 1048576 Bytes1 Gbyte = 1024 Mbyte
EE321 - Chap. 01 – Review © A. Khouas
y y
7
1. Digital Systems
Logic value vs. Physical valueLogic values ‘L’ and ‘H’ are represented in the realLogic values L and H are represented in the real circuit by physical valuesIn fact the physical values for ‘L’ and ‘H’ areIn fact, the physical values for L and H are ranges of values
VOH: minimum output voltage for HighVOH: minimum output voltage for HighVOL: maximum output voltage for LowVIH i i i t lt t d t b Hi hVIH : minimum input voltage guaranteed to be HighVIL : maximum input voltage guaranteed to be Low
EE321 - Chap. 01 – Review © A. Khouas8
1. Digital Systems
Logic value vs. Physical valueLogic value vs. Physical valueOH = [VOH,VDD]OL= [0 , VOL]IH = [VIH,VDD]IL = [0,VIL]
Example: 5V HCMOS
VOL 0 26 VVOL = 0.26 VVOH = 4.48 VVIL = 1VVIH = 3.5VNoise Margin L = 0.74Noise Margin H = 0.96V
EE321 - Chap. 01 – Review © A. Khouas
g
9
Source: Digital Design Principles and practices, by J. F. Wakerly
1. Digital SystemsComparison of logic levels of some technologies
EE321 - Chap. 01 – Review © A. Khouas10
Source: Digital Design Principles and practices, by J. F. Wakerly
2. Binary Representation
Positional Number SystemsyIn positional number system, each position has a weight based on powers of the base (e.g. 57 = 5 10 7)5x10+7)
Base 2k
1101 = 1+0+4+8 = 13
1 1 0 20
... *2 ik k i i
i
N a a a a a avec 0 a 1−=
= = ≤ ≤∑1101 1+0+4+8 13
Hexadecimal Numbers (base 16)Bits are grouped by 4Bits are grouped by 4 Hex is used just to simplify Human-system communication
EE321 - Chap. 01 – Review © A. Khouas
co u ca o
11
2. Binary Representation
Conversion: Decimal --> Base 2Conversion: Decimal > Base 2Division successives par 2
53 21 26 2
0 13 2
End of divisionsLSB
1 6 20 3 2
1 1 25310 = 1101012
Conversion: Base 2 -->Decimal
1 1 21 0MSB
Multiplication by power of 211012 = 1*20 + 0*21 + 1*22 + 1*23 = 1+4+8 = 1316
EE321 - Chap. 01 – Review © A. Khouas
2 16
12
2. Binary Representation
carry
1 1 11 1
1 1 1 0
1
1 4
+ 0 1 1 1
1 0 1 0 1
+ 7
2 11 0 1 0 1 2 1
Decimal Addition Binary Addition
Binary addition
EE321 - Chap. 01 – Review © A. Khouas13
y
2. Binary Representation
5 1 0 1
x 6 x 1 1 0
0 0 0 0 * 101
+ 1 0 1 .
+ 1 0 1
1* 101 + left shift
1* 101 + 2 left shifts
= 30
+ 1 0 1 . .
= 1 1 1 1 0
1* 101 + 2 left shifts
Binary multiplication
EE321 - Chap. 01 – Review © A. Khouas14
y p
2. Binary Representation
In computers and digital systems, the number of bits used to store binary numbers is limitedbits used to store binary numbers is limited==> operation overflow occurs when the result is
t l t b t d b th li it d btoo large to be represented by the limited number of bits
Solution:In unsigned arithmetic the Carry bit generated at theIn unsigned arithmetic the Carry bit generated at the
MSB is used for overflow
EE321 - Chap. 01 – Review © A. Khouas15
2. Binary Representation
Last carry indicate overflowLast carry indicate overflowCarry bit saved in
flag registers
1 1 1 1 11 0 1 1 1 0 0 1 1851 0 1 1 1 0 0 1 185
+ 0 1 1 0 1 0 0 0 + 104= 0 0 1 0 0 0 0 1 = 33 2890 0 0 0 0 0 33 89
Decimal addition 8-bit binary addition
8 bit unsigned binary addition with overflow
EE321 - Chap. 01 – Review © A. Khouas16
8-bit unsigned binary addition with overflow
2. Binary Representation
Signed binary numbersSigned binary numbersSign-magnitude representation1’s complement representation2’s complement representationp pExcess 2n-1-1
Example: 4 bitExample: 4-bit (5)10 = (0101)sm = (0101)1’C = (0101)2’C = (1100)E7( )10 ( )sm ( )1 C ( )2 C ( )E7
(-5)10 = (1101)sm = (1010)1’C = (1101)2’C = (0010)E7=
EE321 - Chap. 01 – Review © A. Khouas
(0010)E7
17
2. Binary Representation
2’s complement is the preferred representation2 s complement is the preferred representation for arithmetic operations
We have:
1 0 0 0 (ignore MSB carry bit)Z + Z = 1...1
Z Z⇒ + +1 0...0 0 (ignore MSB carry bit)1
Z ZZ Z
⇒ + + = =
⇒ − = +
2’s complement numbers can be added by ordinary binary addition ignoring MSB carry bit
EE321 - Chap. 01 – Review © A. Khouas18
2. Binary Representation
Signed binary addition using 2’s complementSigned binary addition using 2 s complement representation
Examples of 4 bit signed binary addition
EE321 - Chap. 01 – Review © A. Khouas19
Examples of 4-bit signed binary addition Source: Digital Design Principles and practices, by J. F. Wakerly
2. Binary Representation
How to detect overflow in signed arithmetic gaddition?
Overflow can occur only with the addition of two numbers of same signIf overflow occur, the sign of the result is different from the sign of the numbers. Also overflow can be gdetected if the carry in and the carry out of the LSB bit are different
EE321 - Chap. 01 – Review © A. Khouas20
Source: Digital Design Principles and practices, by J. F. Wakerly
3. Combinational Logic Circuits
Combinational vs Sequential circuitsCombinational vs. Sequential circuitsCombinational circuits: output depends only on its
t i t ( l )present input (memoryless)
Sequential circuits: output depends on its present and previous inputs (depends on its state)p p ( p )
EE321 - Chap. 01 – Review © A. Khouas21
3. Combinational Logic Circuits
Each combinational circuit can be described as:Equation : sum of products product of sumsEquation : sum of products, product of sums, factorial formT th t blTruth tableLogic diagramBinary Decision DiagramTiming diagramTiming diagram…etc
EE321 - Chap. 01 – Review © A. Khouas22
3. Combinational Logic Circuits
Timing diagram of logic circuitTiming diagram of logic circuitIt shows how the circuit respond to a pattern of input signalsTrans., delay, ytr: rising delaytf: falling delaytf: falling delaytpHL: tpLH:
EE321 - Chap. 01 – Review © A. Khouas23
Electronics – Second Edition, Copyright © 2000 Prentice Hall, Inc.
3. Combinational Logic Circuits
d f lTiming diagram of logic circuitWhy propagation delays are important in digitalWhy propagation delays are important in digital design?
Glitch example: s = A and not(A)
EE321 - Chap. 01 – Review © A. Khouas24
Electronics – Second Edition, Copyright © 2000 Prentice Hall, Inc.
3. Combinational Logic Circuits
Basic logic gatesCircuits implementing basic functions are called
gates. Any digital function can be realized with the g y gfollowing gates:
EE321 - Chap. 01 – Review © A. Khouas25
Source: Digital Design Principles and practices, by J. F. Wakerly
3. Combinational Logic Circuits
Basic logic gatesBasic logic gates
NAND() NOT(AND ()) oNAND() NOT(AND ()) or AND() NOT (NAND ()) ?
EE321 - Chap. 01 – Review © A. Khouas26
Source: Digital Design Principles and practices, by J. F. Wakerly
3. Combinational Logic Circuits
Basic logic gates74LS00: Quad 2-inputs NAND gate74LS02: Quad 2-inputs NOR gateQ p g74LS04: Hex inverter74LS08: Quad 2 inputs AND gate74LS08: Quad 2 inputs AND gate74LS32: Quad 2 inputs OR gate74LS86: Quad 2 inputs XOR gate
EE321 - Chap. 01 – Review © A. Khouas27
Source: Digital Design Principles and practices, by J. F. Wakerly
3. Combinational Logic Circuits
Circuit synthesis and optimization usingCircuit synthesis and optimization using Karnaugh-map
EE321 - Chap. 01 – Review © A. Khouas28
3. Combinational Logic Circuits
Multiplexer/DemultiplexerMultiplexer/Demultiplexer
Connection diagram, truth table and equations of the dual 4-input
EE321 - Chap. 01 – Review © A. Khouas29
g , q pmultiplexer (74LS153)
3. Combinational Logic Circuits
Decoder/Encoder
Pin diagram and truth table of the 3-to-8 table of the 3 to 8 decoder (74LS138).Note 1: G2= G2A + G2B
EE321 - Chap. 01 – Review © A. Khouas30
G2= G2A + G2B
3. Combinational Logic Circuits
ffTristate buffer
Circuit diagram, function table and logic symbol of the CMOS 3-state b ff
EE321 - Chap. 01 – Review © A. Khouas31
Source: Digital Design Principles and practices, by J. F. Wakerly
buffer.
3. Combinational Logic Circuits
Tristate buffer
Pin diagram and function table of the 3-state octal buffer (74LS244)
EE321 - Chap. 01 – Review © A. Khouas32
Pin diagram and function table of the 3 state octal buffer (74LS244).
3. Combinational Logic Circuits
Binary addition: Half Adder (HA)
EE321 - Chap. 01 – Review © A. Khouas33
3. Combinational Logic Circuits
Binary addition: Full Adder (FA)y ( )Sum = A xor B xor CinC t AB Ci B Ci ACout = AB+CinB+CinA
= AB+Cin(AxorB)
Karnaugh-map for CoutKarnaugh map for CoutCin\AB 00 01 11 100 0 0 1 00 0 0 1 01 0 1 1 1
EE321 - Chap. 01 – Review © A. Khouas34
3. Combinational Logic Circuits
Binary addition: n-bit adder (Ripple-carry Adder)
EE321 - Chap. 01 – Review © A. Khouas35
3. Combinational Logic Circuits
Binary addition: n bit adder/subtractorBinary addition: n-bit adder/subtractor
EE321 - Chap. 01 – Review © A. Khouas36
3. Combinational Logic Circuits
Arithmetic and logic unit (ALU)Arithmetic and logic unit (ALU)
EE321 - Chap. 01 – Review © A. Khouas37
4. Sequential Circuits
LatchD Clk Q+ Qn+
X 0 Q Qn
0 1 0 1
1 1 1 0
Memorisation Update
SClk
QnQ
EE321 - Chap. 01 – Review © A. Khouas38
4. Sequential Circuits
Logic and pin diagram and function table of the quad latch (74LS75)
EE321 - Chap. 01 – Review © A. Khouas39
of the quad latch (74LS75).
4. Sequential Circuits
Logic diagram and function table of the octal transparent latch with 3-state poutputs (74LS373).
EE321 - Chap. 01 – Review © A. Khouas40
4. Sequential Circuits
D-type Flip-Flop (DFF)
S b l
D Clk Q+
Symbol
X 0 Q
X 1 Q
0 0
Master-slave positive-edgetriggered DFF
0 0
1 1
Function tableP iti d
EE321 - Chap. 01 – Review © A. Khouas41
Function tablePositive edge
4. Sequential Circuits
D-type Flip-Flop (DFF)
S b l
D Clk Q+
Symbol
X 0 Q
X 1 Q
0 00 0
1 1
Function tablePositive-edge triggered DFF designed using
EE321 - Chap. 01 – Review © A. Khouas42
Function tableNAND gates
4. Sequential CircuitstHtSU
Setup time Hold timeSetup time Hold time
D
Clk
D
Q
D should be stable here
l d h
tPD
Setup time, hold time, and propagation delay for positive edge
Output is valide herePropagation delay
EE321 - Chap. 01 – Review © A. Khouas43
p , , p p g y f p gtriggered DFF
4. Sequential Circuits
D t Fli Fl (DFF)D-type Flip-Flop (DFF)Equation: Q = D q QTableTiming diagram?Timing diagram?
DFF with enable signalgQ = D when En=1Table?Table?Timing diagram?
EE321 - Chap. 01 – Review © A. Khouas44
4. Sequential Circuits
DFF ith bl d h t i lDFF with enable and asynchronous reset signalsEquation? qTable?Timing diagram?Timing diagram?
DFF with enable and synchronous set signalsy gEquation?Table?Table?Timing diagram?
EE321 - Chap. 01 – Review © A. Khouas45
4. Sequential Circuits
Pin diagram and function table of the Dual Positive-Edge-Triggered DFF with Preset, Clear and Complementary Outputs (74LS74)
EE321 - Chap. 01 – Review © A. Khouas46
Preset, Clear and Complementary Outputs (74LS74).
4. Sequential Circuits
Logic and pin diagram and function table of the octal
EE321 - Chap. 01 – Review © A. Khouas47
Logic and pin diagram and function table of the octal transparent DFF with 3-state outputs (74LS374).
4. Sequential Circuits
N-bit Register :E quationsN bit Register Inputs : D(n-1:0) 0 0
:( ) ( )( ) ( )
E quationsQ t D tQ t D t
+ =
Output: Q[n-1:0]Symbol?
1 1
2 2
( ) ( )( ) ( )
Q t D tQ t D t
+ =+ =
yTiming Diagram? 3 3( ) ( )Q t D t+ =
EE321 - Chap. 01 – Review © A. Khouas48
4. Sequential Circuits
Shift RegisterShift Register
0 1
:( 1) ( )( 1) ( )
E quationsQ t Q tQ t Q t
+ =
+ =
CLK D Q3 Q2 Q1 Q0
0 1 U U U U
1 0 1 U U U
1 2
2 3
3
( 1) ( )( 1) ( )( 1) ( )
Q t Q tQ t Q tQ t D t
+ =+ =+ =
2 0 0 1 U U
3 1 0 0 1 U
4 0 1 0 0 1
EE321 - Chap. 01 – Review © A. Khouas49
3 ( ) ( )Q5 0 0 1 0 0
4. Sequential Circuits
CounterQ2 Q1 Q0 Q2+ Q1+ Q0+
Counter 0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 01 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
:
( 1) ( )
Equations
Q t Q t+0 0
1 0 1
( 1) ( )( 1) ( ) ( )( 1) ( ) ( ) ( )
Q t Q tQ t Q t Q tQ t Q t Q t Q t
+ =+ = ⊕
+ = ⊕
EE321 - Chap. 01 – Review © A. Khouas50
2 0 1 2( 1) ( ). ( ) ( )Q t Q t Q t Q t+ = ⊕
5. Logic Families
TTL (Transistor-Transistor Logic) family( g ) yBased on Bipolar transistorReplaced by CMOS family in 1990Replaced by CMOS family in 1990
CMOSBased on MOSFET (Metal-Oxide Semiconductor Field Effect Transistor)Field Effect Transistor)
EE321 - Chap. 01 – Review © A. Khouas51
5. Logic Families
N-Channel MOS TransistorIf V 0 NMOS i OFFIf VGS=0, NMOS is OFFIf VGS=VDD, NMOS is ON
P Channel MOS TransistorP-Channel MOS TransistorIf VSG=0, PMOS is OFFSG
If VSG=VDD, PMOS is ON
EE321 - Chap. 01 – Review © A. Khouas52
5. Logic Families
CMOS InverterCMOS Inverter
EE321 - Chap. 01 – Review © A. Khouas53
Source: Digital Design Principles and practices, by J. F. Wakerly
5. Logic Families
CMOS InverterCMOS Inverter
EE321 - Chap. 01 – Review © A. Khouas54
Source: Digital Design Principles and practices, by J. F. Wakerly
5. Logic Families
CMOS 2-input NAND gateCMOS 2 input NAND gate
EE321 - Chap. 01 – Review © A. Khouas55
Source: Digital Design Principles and practices, by J. F. Wakerly
5. Logic Families
CMOS 2-input NOR gateCMOS 2 input NOR gate
EE321 - Chap. 01 – Review © A. Khouas56
Source: Digital Design Principles and practices, by J. F. Wakerly
5. Logic Families
CMOS GatesCMOS GatesWhat about AND and OR gates?
EE321 - Chap. 01 – Review © A. Khouas57
5. Logic Families
Other CMOS GatesOther CMOS GatesY = not(AB+C) ?
Y = A(B+C) ?Y = A(B+C) ?
EE321 - Chap. 01 – Review © A. Khouas58
Summary
Digital systemsDigital systemsAnalog vs digital systemsHardware vs software designHardware vs. software design
Binary representationsTwo’s complement representationTwo s complement representation
Combinational logic circuitsSeq ential ci c itsSequential circuitsLogic families
NMOS and PMOS transistorsCMOS Family
EE321 - Chap. 01 – Review © A. Khouas59