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1514
13
12
11
10
9 8
01
2
3
4
5
6
7
00000001
0010
0011
0100
0101
0110011110001001
1010
1011
1100
1101
11101111
Unsigned NumbersError point:C bit is set
1514
13
12
11
10
9 8
01
2
3
4
5
6
7
00000001
0010
0011
0100
0101
0110011110001001
1010
1011
1100
1101
11101111
Unsigned NumbersError point:C bit is set
- 1- 2
- 3
- 4
- 5
- 6
- 7 - 8
+0+1
+2
+4
+5
+6
+7
00000001
0010
0011
0100
0101
011001111000
10011010
1011
1100
1101
11101111
Error Point:V bit is set
Signed numbers (2’s complement)
+3
- 1- 2
- 3
- 4
- 5
- 6
- 7 - 8
+0+1
+2
+4
+5
+6
+7
00000001
0010
0011
0100
0101
011001111000
10011010
1011
1100
1101
11101111
Error Point:V bit is set
Signed numbers (2’s complement)
+3
- 1- 2
- 3
- 4
- 5
- 6
- 7 - 8
+0+1
+2
+4
+5
+6
+7
00000001
0010
0011
0100
0101
011001111000
10011010
1011
1100
1101
11101111
Error Point:V bit is set
Signed numbers (2’s complement)
+3
- 1- 2
- 3
- 4
- 5
- 6
- 7 - 8
+0+1
+2
+4
+5
+6
+7
00000001
0010
0011
0100
0101
011001111000
10011010
1011
1100
1101
11101111
Error Point:V bit is set
Signed numbers (2’s complement)
+3
- 1- 2
- 3
- 4
- 5
- 6
- 7 - 8
+0+1
+2
+4
+5
+6
+7
00000001
0010
0011
0100
0101
011001111000
10011010
1011
1100
1101
11101111
Error Point:V bit is set
Signed numbers (2’s complement)
+3
