Embed Size (px)
Citation preview
2
Course Overview• Targeted for graduate students who have
already taken basic VLSI design classes• Real world challenges and solutions in
designing high-performance and low-power circuits
• Relations to VLSI Design– Recent developments in digital IC design– Project oriented– Student participation: class presentation
3
Prerequisite• MOS VLSI Design or equivalent
– MOS transistor– Static, dynamic logic– Adder
• Familiarity with VLSI CAD tools– Magic or Cadence: LVS, DRC– HSPICE
• Basic knowledge on solid-state physics
4
Class Materials• Lecture notes: primary reference• K. Roy, S. Prasad, Low Power CMOS VLSI
Circuit Design, John Wiley• A. Chandrakasan, W. Bowhill, F. Fox, Design of
High-Performance Microprocessor Circuits, IEEE Press, 2001.
• Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2002.
• J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition, 2003. (prerequisite)
5
Class Organization• One exam (40% of overall grade)• Term-long project (60%)
– Proposal (5%)– Midterm presentation (15%) – background
material and proposed work– Final presentation (20%)– Final report (20%)
6
CAD Tools• Cadence
– Schematic editor, layout editor, DRC, LVS• HSPICE, awaves• Technology files
– TSMC 0.18μm, BPTM 70nm, …• Synopsys design compiler, library compiler• Taurus-device, Taurus-medici
• Everyone should have some experience with these tools
7
Term Project• Single person project• Proposal (~week 3)
– 2 pages– Topic, problem statement, research plan, references
• Midterm presentation (~week 7)– 15 mins– Literature survey– Off campus students can give presentations over the
phone• Final presentation (early December)
– 20 mins– Background, final results, contributions
• Final report (Dec. 10) – Publishable quality
8
Project Topic• Students pick the research topic they want to work on• After the literature survey, choose a paper that you
would like to evaluate yourself• Has to be on digital VLSI circuit DESIGN
– Op-amp design alone is not acceptable– Op-amp design for digital applications is acceptable
• Show the paper’s claim using your own simulations• Your contribution must be clearly shown at the end
– Improve previous design– New circuit, modeling technique– Show limitation of previous techniques
• Talk to the instructor in case you need help
9
How to Find a Project Topic?• Conferences
– International Solid-State Circuits Conference (ISSCC, top conference!): slides posted on IEEExplore
– Symposium on VLSI Circuits (VLSIC), DAC, ICCAD– Custom Integrated Circuits Conference (CICC)
• Journal– IEEE TVLSI, IEEE TCAD, IEEE TED– IEEE Journal of Solid-State Circuits (JSSC)– Intel Technology Journal– IBM Journal on R & D
10
How to Find a Project Topic?• Funding agencies
– Research needs document (www.src.org)• Presentation
– University of Michigan VLSI seminar series (www.eecs.umich.edu/vlsi_seminar/)
– Design automation conference (www.dac.com)
• Pick a recent issue in VLSI design (< 5 years)• I suggest you start doing the literature survey
ASAP (deadline coming up in 3 weeks)
11
Acknowledgements• Prof. Chris Kim• Intel circuit research labs (S. Borkar and many
others)• IBM• Copy right 2002 J. Rabaey et al.
12
Academic Misconduct• Students caught engaging in an academically
dishonest practice will receive a failing grade for the course.
• University policy on academic dishonesty will be followed strictly.
13
Course Topics• Scaling issues• High performance design
– High performance logic family, clocking strategies, interconnects
• Low power design– Low voltage designs, leakage control techniques,
circuit/device/technology issues, low power SRAM• Variation tolerant design
– Process compensating techniques• Power delivery, interconnect, reliability• Bulk and SOI
14
A physical system as a computing medium
• We need to create a bit first. Information processing always requires physical carrier, which are material particles.
• First requirement to physical realization of a bit implies creating distinguishable states within a system of such material particles.
• The second requirement is conditional change of state.
• The properties of distinguishability and conditional change of state are two fundamental properties of a material subsystem to represent information. These properties can be obtained by creating energy barriers in a material system.
15
Particle Location is an Indicator of State
1 1 0 0 1 0
16
Two-well bit
a
a
Eb
Eb
w w
17
Barrier engineering in semiconductors
By doping, it is possible to create a built-in field and energy barriers of controllable height and length within semiconductor. It allows one to achieve conditional complex electron transport between different energy states inside semiconductors that is needed in the physical realization of devices for information processing.
n n
p
18
Kroemer’s Lemma of Proven Ignorance
• If in discussing a semiconductor problem, you cannot draw an Energy-Band-Diagram, this shows that you don’t know what are you talking about
• If you can draw one, but don’t, then your audience won’t know what are you talking about
19
Moore’s Law
Intel founder and chairman Gordon Moore predicted in 1965 that the number of transistors on a chip will double every 18-24 months
20
Transistor Scaling
Constant E-field scaling: voltage and dimensions (both horizontal and vertical) are scaled by the same factor k, (~1.4), such that the electrical field remains unchanged.
21
Technology Scaling
22 7.0
reduction)delay (30% 7.07.0
7.07.0 )(
,,7.0
β
ββ
ββ
ββ
→=
=×
→=
=× →−=
→ →→
scalesdd
scalesdd
scalestdd
scalest
scalesdd
scale
CVE
ICV
D
VVTkWI
VVDimensions
ox
22
IC Frequency & Power Trends
1.0 0.8 0.6 .35 .25 .18
Technology Generation (µm)
0.01
0.1
1
10
100
1000
1 2 3 4 5 6 7
Chi
p Po
wer
(W)
0
200
400
600
800
1000
Freq
uenc
y (M
Hz)
Frequency
Power
486DX CPU
Pentium Processor
386
Pentium IIProcessor
R
R
1000
100
10
1
0.1
0.01
Chi
p Po
wer
(W
)
1000
800
600
400
200
0
• Clock frequency improves 50%
• Gate delay improves ~30%
• Power increases 50%
• Power =CL V2 f
Freq
uenc
y (M
Hz)
Active switched capacitance “CL” is increasing.
23
Vdd vs. Vt scaling
• Recently: constant e-field scaling, akavoltage scaling
• VCC ⌫ 1V
• VCC & modest VT
scaling• Loss in gate
overdrive (VCC-VT) 1.4 1.0 0.8 0.6 .35 .25 .18Technology Generation (µm)
0
1
2
3
4
5
0 1 2 3 4 5 6 7
VC
C o
r VT (V
)VT=.45V
VCC=1.8V
VCC
VT
(VCC- VT)Gate over drive
V CC o
r V T
(V)
5
4
3
2
1
0
Voltage scaling is good for controlling IC’s active power, but it requires aggressive VT scaling for high performance
24
Delay2)1()
2(
DD
TDDox
Ld
VVVC
LW
C
−=
µτ Long Channel MOSFET
D
DDLd I
VC=τ
)1(DD
TSATox
Ld
VV
WC
C
−=
υτ Short Channel MOSFET
2WW
1 .τ =
−+
CL Tox
VDDVTVDD
n p
05 05
0 3 0 9 13
2. .
. ( . ) .( ) [1]
[1] C. Hu, “Low Power Design Methodologies,”Kluwer Academic Publishers, p. 25.
Performance significantly degrades when VDD approaches 3VT.
25
VT Scaling: VT and IOFF Trade-offPerformance vs Leakage:
VT ↓ IOFF ↑ ID(SAT) ↑ Low VT
High VT
VGVTL VTH
I DS
IOFFL
IOFFH
VD = VDDfixed Tox
ID(SAT)
)()( 3 TGSSAToxeffD VVCWKSATI −∝ υ
22 )()( TGS
eff
effD VVK
LW
SATI −∝
)(1
TGS VV
eff
effsubthOFF eK
LW
II −∝∝
As VT decreases, sub-threshold leakage increases
Leakage is a barrier to voltage scaling
26
Constant Field Scaling
11/k1/k1
Electric field (E)Capacitance (C=εA/t)Current (I)Channel resistance (Rch)
Device parameters
1/k1/k2
1/k3
k2
1
Delay (CV/I)Power (VI)Switching energy (CV2)Circuit density (1/A)Power density (P/A)
Circuit parameters
1/kk
1/k
Device dimensions (tox, L, W, Xj)Doping concentration (Na, Nd)Voltage (V)
Scaling assumptions
FactorDevice and circuit parameters
27
Scaling in the Vertical Dimension
• Transistor Vt rolls off as the channel length is reduced
• Shallow junction depth reduces Vt roll-off• However, sheet resistance increases
28
Scaling in the Vertical Dimension
• Vertical dimension scales less than horizontal• Aggravates short channel effect (Vt roll-off)
29
Constant Voltage Scaling
k1/kk
1/k
Electric field (E)Capacitance (C=εA/t)Current (I)Channel resistance (Rch)
Device parameters
1/k2
k1/kk2
k3
Delay (CV/I)Power (VI)Switching energy (CV2)Circuit density (1/A)Power density (P/A)
Circuit parameters
1/kk1
Device dimensions (tox, L, W, Xj)Doping concentration (Na, Nd)Voltage (V)
Scaling assumptions
FactorDevice and circuit parameters
30
Constant Voltage Scaling• More aggressive scaling than constant field• Limitations
– Reliability problems due to high field– Power density increases too fast
• Both constant field and constant voltage scaling have been followed in practice
• Field and power density has gone up as a byproduct of high performance, but till now designers are able to handle the problems
31
ITRS Roadmap
• International Technology Roadmap for Semiconductors 2002 projection (http://public.itrs.net/)
32
Transistor Scaling
90nm is in production, 65nm in research phaseNew technology generation introduced every 2-3 years
33
Cost per Transistor
You can buy 10M transistors for a buckThey even throw in the interconnect and package for free
34
Transistors Shipped Per Year
Today, there are about 100 transistors for every ant - Gordon Moore, ISSCC ‘04
35
Transistors per Chip
1.7B transistors in Montecito (next generation Itanium)Most of the devices used for on-die cache memory
36
Moore’s Wrong Prediction
37
Chip Frequency
30% higher frequency every new generation
38
Die Size
~15% larger die every new generationThis means more than 2X increase in transistors per chip
39
Supply Voltage Scaling
Supply voltage is reduced for active power controlfVCP ddactive
2∝
40
4 Decades of Transistor Scaling:Itanium 2 Processor
41
Power Density
Year
Pow
er d
ensi
ty (W
/cm
2 )
High-end microprocessors: Packaging, coolingMobile/handheld applications: Short battery life
42
Active and Leakage Power
Year
Pow
er (W
)
Transistors are becoming dimmersdd
t
L
VVCdelay
−∝
1)
/exp(
qmkTV
I tleak
−∝
43
Leakage Power Crawling Up in Itanium 2
Transistor leakage is perhaps the biggest problem
44
Leakage Power versus Temp.
0.18µ, 15mm die, 1.4V
0% 0% 1% 1% 2% 3% 5% 7% 9%
-10203040506070
30 40 50 60 70 80 90 100
110
Temp (C)
Pow
er (W
atts
) LeakageActive
0.1µ, 15mm die, 0.7V
6% 9% 14% 19%26%
33%41%
49%
56%
-10203040506070
30 40 50 60 70 80 90 100
110
Temp (C)Po
wer
(Wat
ts)
LeakageActive
Leakage power is problematic in active mode for high performance microprocessors
45
Thermal RunawayIncreased
heating
Destructive positive feedback mechanismLeakage increases exponentially with temperatureMay destroy the test socket thermal sensors required
Higher leakage
Higher power dissipation
Increased static current
46
Gate Oxide Thickness
Electrical tox > Physical toxDue to gate depletion and carrier quantization in the channel
47
Gate Tunneling Leakage
MOSFET no longer have infinite input resistanceImpacts both power and functionality of circuits
48
Process Variation in Microprocessors
Fast chips burn too much powerSlow chips cannot meet the frequency requirement
49
Process Variation in Transistors
0.4
0.6
0.8
1.0
1.2
1.4
0.01 0.1 1 10 100
Normalized IOFF
Nor
mal
ized
I ON
NMOSPMOS
100X
2X
150nm, 110°C
More than 2X variation in Ion, 100X variation IoffWithin-dies, die-to-die, lot-to-lot
50
Sources of Process Variation
Intrinsic parameter variation (static)- Channel length, random dopant fluctuation
Environmental variation (dynamic)- Temperature, supply variations
51
Sub-wavelength Lithography
52
Line Edge/Width Roughness
• Ioff and Idsat impacted by LER and LWR
53
Random Dopant Fluctuation
Vt variation caused by non-uniform channel dopant distribution
54
Supply Voltage Integrity
• IR noise due to large current consumption• Ldi/dt noise due to new power reduction
techniques (clock gating, power gating, body biasing) with power down mode
55
Supply Voltage Integrity• Degrades circuit
performance• Supply voltage
overshoot causes reliability issues
• Power wasted by parasitic resistance causes self-heating
• Vdd fluctuation should be less than 10%
Courtesy IBM
56
Productivity Gap
Design complexity surpasses manpowerEffective CAD tools, memory dominated chips
57
Lithography Tool Cost
What will end Moore’s law, economics or physics?
58
Interconnect Scaling• Global interconnects get longer due to larger
die size• Wire scaling increases R, L and C
• Example: local vs. global interconnect delay
59
Local interconnect has sped up (shorter wires)Global interconnect has slowed down (RC doesn’t scale)
1997 SIA technology roadmap
Interconnect Delay Problem
60
Interconnect Metal Layers
Local wires have high density to accommodate the increasing number of devicesGlobal wires have low RC (tall, wide, thick, scarce wires)
M1M2M3M4
M5
M6
Interconnect distribution scaling trends• RC/µm scaling trend is only one side of the story...
10 100 1,000 10,000 100,000Length (u)
No
of n
ets
(Log
Sca
le)
Pentium Pro (R)Pentium (R) IIPentium (MMX)Pentium (R)Pentium (R) II
Sour
ce: I
ntel
62
Power Delivery & Distribution Challenges
• High-end microprocessors approaching > 10 GHz• How to deliver and distribute ~100A at < 1V for < $20!• On-die power density >>> hot-plate power density
• crossover happened back in 0.6µm technology! • di/dt noise only worsening with scaling: drivers are one of the sources.
P6P5
P4P3
1.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+071.E+08
1.5 1
0.8
0.6
0.35
0.25
0.18
0.13
0.09
0.06
di/d
t in
AU
Lead Processors
First compaction
Second compaction
0
10
20
30
40
50
60
70
Wat
ts/c
m2
Example multi-layer system
0.80 x 1.6µm
0.64µm
1.6µm
0.32 x 0.64µm0.64µm0.25 x 0.48µm0.50µm
M4
M5
M3
M2
M1PolySubstrate
0.32 x 0.64µm
1.00 x 1.80µm2.00µm
M6
1.00 x 1.80µm2.00µm
M7 Al
0.80 x 1.6µm1.6µm
K. Soumyanath et. al. [2]
64
As wires are brought closer with scaling, capacitive coupling becomes significantAdjacent wires on same layer have stronger coupling
Cross Talk Noise
65
Cross Talk Noise
Multiple aggressors multiple victims possibleCross talk noise can cause logic faults in dynamic circuits
66
Cross Talk and DelayCapacitive cross talk can affect delayIf aggressor(s) switch in opposite direction, effective coupling capacitance is doubled On the other hand, if aggressor(s) switch in the same direction, Cc is eliminatedSignificant difference in RC delay depending on adjacent switching activity
67
Soft Error In Storage Nodes
Logic 1 Logic 0
Vinduced
• Soft errors are caused by – Alpha particles from package materials– Cosmic rays from outer space
68
Soft Error In Storage Nodes
• Error correction code• Shielding• SOI• Radiation-hardened
cell
69
More RoadblocksMemory stabilityLong term reliabilityMixed signal design issuesMask costTesting multi-GHz processorsSkeptics: Do we need a faster computer?…
Eventually, it all boils down to economics
70
SummaryDigital IC Business is Unique
Things Get Better Every Few YearsCompanies Have to Stay on Moore’s Law Curve to Survive
Benefits of Transistor ScalingHigher Frequencies of OperationMassive Functional Units, Increasing On-Die MemoryCost/MIPS Going Down
Downside of Transistor ScalingPower (Dynamic and Static)Process VariationDesign/Manufacturing Cost….
