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EECS 470 Lab 6SystemVerilog
Department of Electrical Engineering and Computer ScienceCollege of EngineeringUniversity of Michigan
March 5th, 2021
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 1 / 31
Overview
Administrivia
Motivation
Multidimensional Arrays
Unique and Priority
Assertions
For Loops
Generate Blocks
Assignment
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 2 / 31
Administrivia
Crazy times are here
ProjectI Project Milestone 1 Due 3/11
I You should have at least one module fully completed and debugged(we recommend the Reservation Station)
I Turn in: progress report, one module, testbench, and coverage reportfor us to grade
I You will submit via a branch named milestone_1 and must submit avalid Makefile that synthesizes with make syn
I We will modify your submitted module and see if the testbench candetect the faulty behavior.
I Keep an eye on piazza for explicit turn in directionsI Some resources (like fast priority selector) are available on the course
site
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 3 / 31
Motivation
Motivation
Why SystemVerilog? Why now?I Extra features that will be useful in your projectsI Not all features are easy to use: many have a steep learning curveI The goal isn’t to go wild and try to use everything...I Instead, think about which are worthwhile to incorporate
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 4 / 31
Motivation
What is SystemVerilog?
1. 1995 – Verilog HDL2. 2001 – Verilog 20013. 2005 – SystemVerilog
I Emphasis on creating a combined Hardware Description Language andHardware Verification Language
I Ability to debug at the “system” levelI Provides the basis for very powerful, object-oriented testbenchesI The framework for industry verification tools, e.g. UVM
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 5 / 31
Multidimensional Arrays
Multidimensional Arrays
ExampleI logic [127:0] [63:0] multi_d_array [3:0];I assign multi_d_array[3][101] = 64’hFFFF_FFFF;
ExplanationI “[127:0]” and “[63:0]” are called “packed” dimensionsI “[3:0]” is an “unpacked” dimensionI When referencing for read/write, unpacked dimensions come first,
then packed dimensions
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 6 / 31
Multidimensional Arrays
Multidimensional Arrays
ExampleI logic [127:0] [63:0] multi_d_array [3:0];I assign multi_d_array[3][101] = 64’hFFFF_FFFF;
ExplanationI Old Verilog only allows one packed dimensionI SystemVerilog allows as many as you needI We recommend packed arrays for most designs
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 7 / 31
Multidimensional Arrays
Multidimensional Arrays
ExampleI logic [31:0] one_d_array;I logic [15:0] [1:0] two_d_array;I assign two_d_array = one_d_array;
ExplanationI Packed arrays are laid out as a contiguous set of bitsI Allows easy copying from one array to another
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 8 / 31
Unique and Priority
Unique/priority if/case
input a, b, c;input [1:0] sel;output z;case (sel)
2'b00: z = a;2'b01: z = b;2'b10: z = c;
endcase
How will the synthesis tool convert this design to hardware?
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 9 / 31
Unique and Priority
Unique/priority if/case
input a, b, c;input [1:0] sel;output z;case (sel)
2'b00: z = a;2'b01: z = b;2'b10: z = c;
endcase
A latch will be generated, since a value for z was not specified whensel == 2’b11
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 10 / 31
Unique and Priority
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 10 / 31
Unique and Priority
Unique/priority if/case
What if you know sel will never equal 2’b11?I You could add a dummy state, but that adds unnecessary logic and
potentially hides errorsI SystemVerilog has a “priority” construct for exactly this problem
I Tells synthesis tool not to generate a latchI Checks at run-time that each state is reachable
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 11 / 31
Unique and Priority
Unique/priority if/case
input a, b, c;input [1:0] sel;output z;priority case (sel)
2'b00: z = a;2'b01: z = b;2'b10: z = c;
endcase
During behavioral simulation, if sel is 2’b11, a warning will be generated:
RT Warning: No condition matches in priority case statement.
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 12 / 31
Unique and Priority
Unique/priority if/case
Another code example:
input [1:0] sel;output logic [1:0] z;if (sel[1])
z = a;else if (sel[0])
z = b;else
z = c
What hardware will be generated by this code?
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 13 / 31
Unique and Priority
Unique/priority if/case
Another code example:
input [1:0] sel;output logic [1:0] z;if (sel[1])
z = a;else if (sel[0])
z = b;else
z = c
Tool will give priority to higher bits, since it assumes multiple bitscould be high?I But what if we’re using one-hot encoding?
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 14 / 31
Unique and Priority
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 14 / 31
Unique and Priority
Unique/priority if/case
SystemVerilog has “unique” if/case statement
input [1:0] sel;output logic [1:0] z;unique if (sel[1])
z = a;else if (sel[0])
z = b;else
z = c
I Tells synthesis tool to assumeone-hot encoding
I Ignores priority logic and doesn’tgenerate any latches
I Generates simulation warningif multiple bits are high
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 15 / 31
Unique and Priority
Unique/priority if/case
Unique & Priority used for both if and case statementsI Replaces “full_case” and “parallel_case” pragmas from old VerilogI Useful for simplifying logic and clarifying design choices
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 16 / 31
Assertions
Assertions
AssertionsI Strategy for automated testing: check that certain conditions are trueI Statements declaring some kind of invariantI Can be inserted in testbenches or RTL (ignored by synthesis)I Two types:
I Immediate: directly called in codeI Concurrent: running in background
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 17 / 31
Assertions
Immediate Assertions
Need to check that some expression is true...
adder a1(a, b, c);initial begin
if ((a+b) != c)$display("Error!");
end
Better done by immediate assertion...
adder a1(a, b, c);initial begin
assert ((a+b) == c);end
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 18 / 31
Assertions
Concurrent Assertions
I Much more interesting (and challenging)I Describe high-level functional correctness of your design...I ...and have simulator check these invariants in the background
I SystemVerilog supports an entire assertion language (!)I (beyond the scope of what we will do in class)
I ImplicationI s1 |-> s2
I If s1 is true, then s2 must also be trueI Timing windows
I (a && b) |-> ##[1:3] c;I On the posedge of the clock, if a and b are true, then 1-3 cycles later,
c will be true
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 19 / 31
Assertions
Assertions
AssertionsI For more information on assertions, look into the book A Practical
Guide to SystemVerilog Assertions
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 20 / 31
For Loops
“For” loops
“You want ‘for’ loops? You can’t handle ‘for’ loops!”I We told you earlier in the semester that “for” loops are not a thingI We lied, sort of... but they don’t work the way they do in softwareI In software we think about iterations of loops
I Iteration 1, then Iteration 2, then Iteration 3... etc...I In hardware, loops need to unroll completely at design time
I Self-modifying hardware is still not a thing...I So either everything runs in parallel (good)I Or loop can “break” when a certain condition is true (can get ugly)
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 21 / 31
For Loops
For loops
Does this make sense for actual hardware?parity = 0;for (int i=0; i<32; i++) begin
if (in[i])parity = ~parity;
end
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 22 / 31
For Loops
For loops
Designing synthesizable “for” loopsI “For” loops can be valuable, just different than software
I Just another way of doing combinational logic, not a replacement forsequential logic
I Very limited ability to change signals referenced in the loop
I Great for condensing repetitive code, because everything will be donein parallel
I Visualize how a loop can be built into hardware at synthesis time
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 23 / 31
For Loops
For loops
Blocking assignment in loopsalways_comb begin
for (int i=0; i<32; i++)a = i;
endI What will a equal?I 31, because if we unrolled the loop, the assignment to 31 would be last
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 24 / 31
For Loops
For loops
Break Statementsalways_comb begin
for (int i=0; i<32; i++)a = i;if (condition[i]) break;
endI Effect: break out of loop once condition is true
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 25 / 31
For Loops
For loops
Max loop iterationsI Design Compiler sets a maximum number of loop iterations to prevent
infinite loopsI This is configured to be 1024 by defaultI If you need more, add this line to your .tcl file:
set hdlin_while_loop_iterations (iterations)
Final adviceI Remember: don’t use Verilog as a way to avoid thinking about actual
hardwareI This results in synthesis problems or overly complex designs
I First think about how to build the hardware, then think about theVerilog constructs that can allow you to describe your design easily
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 26 / 31
Generate Blocks
Generic Designs
Goal: complex designs with a single parameterI Want to make designs where we can easily change certain features
I For example, the number of ROB entries
I The multiplier in P2 could be modified using parametersI We can build complex designs... remember module arrays?
one_bit_adder add_8 [7:0] (.a(a), .b(b), .cin({carries, cin}),.sum(sum), .cout({cout, carries}));
I What if we couldn’t condense everything to a single parameter?I An adder is simple, just an array of smaller addersI What about more complex structures like the priority selectors from P1
that are trees of smaller selectors?
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 27 / 31
Generate Blocks
Generate Blocks
Generate blocks give controlI Using a generate block to build hardware:
generategenvar i;for (i=0; i<N; i++) begin
one_bit_adder (.a(a[i]), .b(b[i]),.cin(carries[i]),.sum(sum[i]),.cout(carries[i+1]));
endendgenerate
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 28 / 31
Generate Blocks
Generic Designs
Goal: complex designs with a single parameterI How does this work?
I The tool will “elaborate” the designI Evaluate “if” statements and unroll “for” loops
I Important: all conditions must be deterministic at compile time
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 29 / 31
Generate Blocks
Generate Blocks
Another example: the Priority selectors from P1:
generategenvar i;for (i=0; i<N; i++) begin
localparam left_right = i[0];
ps2 (.req (sub_reqs[i]),.en (sub_gnts[i/2][left_right]).gnt (sub_gnts[i]),.req_up (sub_reqs[i/2][left_right]))
endendgenerate
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 30 / 31
Assignment
Lab Assignment
I Assignment is posted to the course website.I If you get stuck. . .
I Put yourself in the help queue
I When you finish the assignment, sign up in the help queue and markthat you would like to be checked off.
I You will need to submit this lab to Canvas by 11:59pm on March 12th.
(University of Michigan) Lab 6: SystemVerilog March 5th, 2021 31 / 31